Ultra Low Voltage Low Power

8/2/2019 Ultra Low Voltage Low Power

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ULTRA LV/LP NEUROMORPHICULTRA LV/LP NEUROMORPHICULTRA LV/LP NEUROMORPHICULTRA LV/LP NEUROMORPHICCIRCUIT DESIGN USINGCIRCUIT DESIGN USINGCIRCUIT DESIGN USINGCIRCUIT DESIGN USING

FGMOS & CADENCE TOOLSFGMOS & CADENCE TOOLSFGMOS & CADENCE TOOLSFGMOS & CADENCE TOOLS

.

Guided by:Guided by: ProfProf Dr.S.S.GajreDr.S.S.Gajre

Presented by:Presented by: SyedSyed MuffassirMuffassir M.S.AliM.S.Ali


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CONTENTS

1)1)1)1) LV/LP DesignLV/LP DesignLV/LP DesignLV/LP Design

2)2)2)2) NeuromorphicNeuromorphicNeuromorphicNeuromorphic Circuit DesignCircuit DesignCircuit DesignCircuit Design3)3)3)3) Multiplier DesignMultiplier DesignMultiplier DesignMultiplier Design

13-Apr-12SGGS IE & T,Nanded.

5)5)5)5) The Design of NeuronThe Design of NeuronThe Design of NeuronThe Design of Neuron6)6)6)6) ReferencesReferencesReferencesReferences


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Chapter 1:

LV /LP DESIGN



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WHY LV / LP ?Greater portability and long battery life meansGreater portability and long battery life meansGreater portability and long battery life meansGreater portability and long battery life means

LV /LP circuit design.LV /LP circuit design.LV /LP circuit design.LV /LP circuit design.LV: To meet requirements of subLV: To meet requirements of subLV: To meet requirements of subLV: To meet requirements of sub----micronmicronmicronmicron fabfabfabfab


.

..

.

Previously now its [1].Previously now its [1].Previously now its [1].Previously now its [1].

The other is Magnitude of electric fields.The other is Magnitude of electric fields.The other is Magnitude of electric fields.The other is Magnitude of electric fields.

LP: To meet battery longevity requirement.LP: To meet battery longevity requirement.LP: To meet battery longevity requirement.LP: To meet battery longevity requirement.


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TECHNIQUES FOR LV/LP:Techniques for voltage reduction:Techniques for voltage reduction:Techniques for voltage reduction:Techniques for voltage reduction:

Circuits with railCircuits with railCircuits with railCircuits with rail----rail operating range.rail operating range.rail operating range.rail operating range.Techniques of cascading stages instead of a singleTechniques of cascading stages instead of a singleTechniques of cascading stages instead of a singleTechniques of cascading stages instead of a singlecascodecascodecascodecascode stage.stage.stage.stage.


Supply multipliers.Supply multipliers.Supply multipliers.Supply multipliers.NonNonNonNon----linear processing of the signals.linear processing of the signals.linear processing of the signals.linear processing of the signals.

Techniques for current reduction:Techniques for current reduction:Techniques for current reduction:Techniques for current reduction:

Adaptive biasing.Adaptive biasing.Adaptive biasing.Adaptive biasing.

SubthresholdSubthresholdSubthresholdSubthreshold biasingbiasingbiasingbiasing ....


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INTRODUCING FGMOS DEVICEKahngKahngKahngKahng andandandand SzeSzeSzeSze in 1967 first introducedin 1967 first introducedin 1967 first introducedin 1967 first introducedthe FGMOS and mostly used forthe FGMOS and mostly used forthe FGMOS and mostly used forthe FGMOS and mostly used forEPROMsEPROMsEPROMsEPROMs

C.MeadC.MeadC.MeadC.Mead used it in analog circuits called itused it in analog circuits called itused it in analog circuits called itused it in analog circuits called itas neuron MOS for silicon retina andas neuron MOS for silicon retina andas neuron MOS for silicon retina andas neuron MOS for silicon retina and


cochlea [3].cochlea [3].cochlea [3].cochlea [3].Pioneers:Pioneers:Pioneers:Pioneers: T.ShibataT.ShibataT.ShibataT.Shibata &&&& T.OhmiT.OhmiT.OhmiT.Ohmi (Japan)(Japan)(Japan)(Japan)C.Mead,ChrisC.Mead,ChrisC.Mead,ChrisC.Mead,Chris Diorio,B.A.MinchDiorio,B.A.MinchDiorio,B.A.MinchDiorio,B.A.Minch &&&&P.HaslerP.HaslerP.HaslerP.Hasler((((Caltech,USACaltech,USACaltech,USACaltech,USA),Rodriguez),Rodriguez),Rodriguez),Rodriguez

VillageasVillageasVillageasVillageas(Spain)(Spain)(Spain)(Spain)Institutes: Caltech(USA) and Institute ofInstitutes: Caltech(USA) and Institute ofInstitutes: Caltech(USA) and Institute ofInstitutes: Caltech(USA) and Institute ofNeuroinformaticsNeuroinformaticsNeuroinformaticsNeuroinformatics (Swiss) and others.(Swiss) and others.(Swiss) and others.(Swiss) and others.


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Fig: Layout of FGMOS Fig: Schematic of FGMOS

Why FGMOSWhy FGMOSWhy FGMOSWhy FGMOS ????

1)1)1)1)Controllability.Controllability.Controllability.Controllability.2)2)2)2)Flexibility.Flexibility.Flexibility.Flexibility.3)3)3)3)TunabilityTunabilityTunabilityTunability....


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EQUATIONS [13]13-Apr-12SGGS IE & T,Nanded.

Fig: Equivalent Schematic of FGMOS


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FGMOS IN WEAK

INVERSION(SUBTHRESHOLD)



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SIMULATIONS


Fig: Subthreshold MOS Vds-Id Chararacteristics. Fig: Subthreshold FGMOS Vds-Id Chararacteristics.


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Chapter 2

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NEUROMORPHIC CIRCUIT DESIGN

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BACKGROUNDWhat isWhat isWhat isWhat is NeuromorphicNeuromorphicNeuromorphicNeuromorphic ???? Neuromorphic engineering is anew interdisciplinary discipline that takes inspiration frombiology, physics, mathematics, computer science, andengineering to design artificial neural systems

Wh analo ?Wh analo ?Wh analo ?Wh analo ? The nervous s stem accepts fuzz , poorl


conditioned inputs, performs a computation that is illdefined, and produces an approximate output. [3].[3].[3].[3].

WhyWhyWhyWhy SubthresholdSubthresholdSubthresholdSubthreshold ???? The force which drive electriccurrents in a subthreshold MOSFET(i.e diffusion), is thesame force which drive ionic currents through ionchannels in neurons ....


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NEURON CIRCUIT DESIGN

FGMOS structures are also known as neuronFGMOS structures are also known as neuronFGMOS structures are also known as neuronFGMOS structures are also known as neuron

MOS because of functional similarity of theMOS because of functional similarity of theMOS because of functional similarity of theMOS because of functional similarity of theneuronneuronneuronneuron


Fig:Neuron Model [11] . Fig: Neuron Circuit [11].


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N-INPUT NEURON CIRCUIT DESIGN



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Chapter 3

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THE MULTIPLIERTHE MULTIPLIERTHE MULTIPLIERTHE MULTIPLIER

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MATHEMATICS [14]



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MULTIPLIER DESIGN[15]



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DC CHARACTERISTICS



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TRANS RESPONSE OF INPUTS



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TRANS RESPONSE OF OUTPUT



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Chapter 4

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THE ACTIVATION

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STEP & SIGMOID FUNCTIONSThe sigmoid has the property of being similar to the stepThe sigmoid has the property of being similar to the stepThe sigmoid has the property of being similar to the stepThe sigmoid has the property of being similar to the stepfunction, but with the addition of a region of uncertainty.function, but with the addition of a region of uncertainty.function, but with the addition of a region of uncertainty.function, but with the addition of a region of uncertainty.Sigmoid functions in this respect are very similar to the inputSigmoid functions in this respect are very similar to the inputSigmoid functions in this respect are very similar to the inputSigmoid functions in this respect are very similar to the input----output relationships of biological neurons, although not exactlyoutput relationships of biological neurons, although not exactlyoutput relationships of biological neurons, although not exactlyoutput relationships of biological neurons, although not exactlythe samethe samethe samethe same.



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SIGMOIDAL CIRCUIT



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SIMULATION OF SIGMOIDAL CKT



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Chapter 5

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THE DESIGN OF NEURON

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DESIGN OF NEURON(APPROX)



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CONCLUSION

Successfully designed &Successfully designed &Successfully designed &Successfully designed &


implemented the multiplier circuit,implemented the multiplier circuit,implemented the multiplier circuit,implemented the multiplier circuit,SigmoidalSigmoidalSigmoidalSigmoidal circuit and single neuroncircuit and single neuroncircuit and single neuroncircuit and single neuron

in Analog VLSI usingin Analog VLSI usingin Analog VLSI usingin Analog VLSI usingCadence 180 nm process technology.Cadence 180 nm process technology.Cadence 180 nm process technology.Cadence 180 nm process technology.


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13 12SGGS &


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13-Apr-12

THANK YOU !!

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Ultra Low Voltage Low Power