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Universität Dortmund
Laboratory Exercise 1
Davide Rossi
DEI University of Bologna
AA 2016-2017
Universität Dortmund
Objectives
• Design and simulation of a simplecombinational circuit (4-bit adder)
Goals:• Execute all design steps and simulate with
Mentor Modelsim• Analyze main constructs of Synthesizable
SystemVeilog (RTL)• Analyze main constructs of testbench
SystemVerilog (not synthesizable)• Provide an example of hierachical
implementation
Universität Dortmund
4 bit adder
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Half Adder
A B Sum Couti
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sumi= Ai + Bi
Couti=AiBi
Universität Dortmund
Full Adder
Sumi= Ai + Bi + Cini
Ai Bi Cini Couti Sumi
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Arithmetical sum
between two 1-bit
operands
Couti=AiBi+Cini(Ai + Bi)
= AiBi+Cini(Ai + Bi)
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Hierarchical Project
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The Ripple-Carry Adder
Universität Dortmund
Half Adder (HA)module half_adder
(
input logic A,
input logic B,
output logic SUM,
output logic COUT
);
assign SUM = A ^ B;
assign COUT = A & B;
endmodule
Declaration of module
name and ports
Functional specifications
of module
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Full Adder (Structural+Behavioral)
module full_adder(input logic A,input logic B,input logic CIN,output logic SUM,output logic COUT);
logic S1,C1,C2;
half_adder ha_0_i ( .A(A), .B(CIN), .SUM(S1), .COUT(C1) );half_adder ha_1_i ( .A(B), .B(S1), .SUM(SUM), .COUT(C2) );
assign COUT = C1 ^ C2;
endmodule
Declarations of
internal signals
Instantiation
of hierarchical modules
Declaration of module
name and ports
+ behavioral specifications
of module functionality
NAME OF THE MODULE
NAME OF THE INSTANCE
Universität Dortmund
Ripple Carry Adder (Structural)module ripple_carry_adder
(
input logic [3:0] A,
input logic [3:0] B,
input logic CIN,
output logic [3:0] SUM,
output logic COUT
);
logic [2:0] INT;
full_adder fa_0_i ( .A(A[0]), .B(B[0]), .CIN(CIN), .SUM(SUM[0]), .COUT(INT[0]) );
full_adder fa_1_i ( .A(A[1]), .B(B[1]), .CIN(INT[0]), .SUM(SUM[1]), .COUT(INT[1]) );
full_adder fa_2_i ( .A(A[2]), .B(B[2]), .CIN(INT[1]), .SUM(SUM[2]), .COUT(INT[2]) );
full_adder fa_3_i ( .A(A[3]), .B(B[3]), .CIN(INT[2]), .SUM(SUM[3]), .COUT(COUT) );
endmodule
Universität Dortmund
module ripple_carry_adder
(
input logic [3:0] A,
input logic [3:0] B,
input logic CIN,
output logic [3:0] SUM,
output logic COUT
);
logic [4:0] INT;
genvar i;
generate
begin
for ( i=0; i<4; i++ )
begin
full_adder fa_i ( .A(A[i]), .B(B[i]), .CIN(INT[i]), .SUM(SUM[i]), .COUT(INT[i+1]) );
end
end
endgenerate
assign INT[0] = CIN;
assign COUT = INT[4];
endmodule
Ripple Carry Adder (a smarter way)
DECLARATION OF A GENERATION VARIABLE
GENERATE / ENDGENERATE
FOR LOOP
MODULE INSTANTIATED MULTIPLE TIMES
LOOP INDEX USED TO
ROUTE SIGNALS
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Testbench`timescale 1ns/1ps
module testbench ();
logic [3:0] A;
logic [3:0] B;
logic [3:0] SUM;
logic CIN,COUT;
ripple_carry_adder DUT ( .A(A), .B(B), .CIN(CIN), .SUM(SUM), .COUT(COUT) );
initial
begin
A = 0;
B = 0;
CIN = 0;
#2;
A = 2;
B = 5;
CIN = 0;
#2;
$stop;
end
endmodule
DECLARATION OF INTERNAL SIGNALS
INSTANTIATION OF DEVICE UNDER TEST
TIME UNIT / TIME PRECISION
DECLARATION OF MODULE
INITIAL = DO THIS ONCE (BEHAVIORAL, NOT SYNTHESIZABLE)
TIMING CONTROL FOR SIMULATION
STOP SIMULATION
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Structure of a Project Directory
RTL contains register transfer level, synthesizable code
TB contains the testbench, not synthesizable code
SETUP contains setup scripts for Mentor Modelsim
SIM simulation directory
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Compilation and Simulation of System Verilog Files with Mentor Modelsim
rm -rf work
vlib work
vlog -sv -work work -quiet module1.sv
vlog -sv -work work -quiet module2.sv
...
vlog -sv -work work -quiet testbench.sv
vsim testbench -novopt
CLEANS THE WORKING DIRECTORY
CREATES WORKING LIBRARY (DEFAULT = WORK)
COMPILES RTL FILES INTO WORKING DIRECTORY
SV = SYSTEM VERILOG COMPILES TESTBENCH
LAUNCH MODELSIM
NAME OF TOP-LEVEL MODULE (TESTBENCH)
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Modelsim
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Add Signals to Wave Window and Run a Simulation
Enter run -all in the VSIM> prompt in transcript window
Universität Dortmund
Exercise: 4-bit RCA
Design a 4-bit ripple carry adder using abehavioral description for the full adder. Createa testbench and use Mentor Modelsim to verifythat the design has the expected behavior.
