University Of Central FloridaDepartment Of Computer Science

The CRAY-1 Computer SystemPresented By: Hatim Boustique

Summer 2003

Content

- Characteristics of Cray 1- Computation Section- Software- Comparison and Evolution- Conclusion

Cray Seymour

Created in 1976

The Cray-1 consists of :

The CPU mainframeA power CabinetA Maintenance Control Unit ( MCU)One or more Disk SystemsAn interface to a front-end computer

Basic Computer System

Characteristics of Cray 1 Cont.COMPUTATION SECTION

12.5 nanosecond clock period

Scalar and vector processing modes

Twelve fully segmented functional units

Vector ,Scalar and Address registers

Four instruction buffers of 64 16-bit parcels each

128 Instruction codes

Characteristics of Cray 1Cont.MEMORY SECTION

Up to 1,048,576 words of bi-polar memory (64 data bits and eight error correction bits)

sixteen banks of 65,536 words each

Four-clock-period bank cycle time

Characteristics of Cray 1 Cont.INPUT/OUTPUT SECTION

12 input channels and 12 output channels

Channels are grouped ( 1 group = 6 channels )

Channel groups served equally by memory (scanned every four clock periods)

Channel priority resolved within channel groups

Lost data detection

Computation Section

Computation Section consists of

- Instruction Control Network- Operating registers - Functional Units ( Or pipelined Units)- Instruction buffers

Computation Section ( cont.)Instruction format

Example: Arithmetic operations

gh : operation code

i : the result register

j and k : the two operand registers

Computation Section ( cont.)Operating registers

- V Registers for Vector processing

- 8 V registers ( 1 V Register = 64 elemt)( 1 Element = 64 bits)

- Suited for vector quantities ( i.e. rows/columns of matrices)

- Used for vector chaining

M

E

M

O

R

Y

Example of ChainingDO I = 1, 64

D(I) = A(I) * B(I) + C(I)

Computation Section ( cont.)Operating registers

Computation Section ( cont.)Operating registers

- S Registers for Scalar processing

- 8 S-registers ( 1 Register = 64 bits)

- Source and destination for scalar arithmetic

- Furnish one operand in vector instructions

Computation Section ( cont.)Operating registers

- A Registers ( Address )- 8 24-bit registers

Primarily for - Memory references

Also for- Loop control- Channel I/O operations

Hardware organizations Each implements a portion of the Instruction Set 12 independent functional units = parallelism grouped into

Vector units Floating point Scalar units Address units

Computation Section ( Cont. ) Functional Units

Computation Section ( Cont.) Functional Units

Computation Section ( Cont. ) Functional Units

Software

Cray Operating System (COS) — up to63 jobs in a multiprog. Environment

Cray Fortran Compiler (CFC) —optimizes Fortran IV (1966) for the Cray-1Automatically vectorizes loops thatmanipulate arrays

Front-end computer

Any computer, such as a Data General Eclipse or IBM 370/168

HP9000/735 workstation

1992

Cray-1 Vector Supercomputer

1976

>130 MIPS < 10 MIPS

41 MFLOPS 27 MFLOPS

Price $ 40,000 $ 4,000,000

99 MHz 80 MHz

Cache 128 kB 0.25 kB

Mem 400 MB 32 MB

Comparison with HP9000/735

CRAY-1 CRAY-2 CRAY-3 CRAY-4

1976 1984 1988-89 1992

CP: 12.5ns CP: 4.1ns CP: 2ns CP: 1ns

1 CPU 4 CPUs 16 CPUs 64 CPUs

80 MIPS 480 MIPS 8000 MIPS Cray Computer Corporation declared bankruptcy

160 MFLOPS

1800 MFLOPS

16000 MFLOPS

Evolution Of Cray

Conclusion

To which category of architectures The Cray 1 Computer does belong ?

Load – Store Parallel functional unitsPipeline processing

References

- Russell, R. M., "The CRAY-1 Computer System", Communications of the ACM, (21) 1, January 1978, pp. 63-72

- Cray-1 Computer System

Hardware Reference Manual 2240004

By CRAY RESEARCH, INC. 1976.