Upload
others
View
9
Download
1
Embed Size (px)
Citation preview
9/23/04 EECS150 F04 Culler Lec 8 1
EECS 150 - Components and Design Techniques for Digital Systems
Lec 08 – Using, Modeling and Implementing FSMs
9-23-04David Culler
Electrical Engineering and Computer SciencesUniversity of California, Berkeley
http://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150
9/23/04 EECS150 F04 Culler Lec 8 2
Review: What’s an FSM?
• Next state is function of state and input
• Moore Machine: output is a function of the state
• Mealy Machine: output is a function of state and input
Often PLAs
State / outputinputA
inputB
State inputA/outputA
inputB/outputB
9/23/04 EECS150 F04 Culler Lec 8 3
Review: Formal Design Process
• Circuit Diagram:
– XOR gate for ns calculation– DFF to hold present state– no logic needed for output
Logic equations from table:
OUT = PSNS = PS xor IN
nsps
• Review of Design Steps:1. Circuit functional specification2. State Transition Diagram3. Symbolic State Transition Table4. Encoded State Transition Table5. Derive Logic Equations6. Circuit Diagram
FFs for stateCL for NS and OUT
9/23/04 EECS150 F04 Culler Lec 8 4
������
������
������������
���
���
���
������
Review: Finite State Machine Representations• States: determined by possible values in
sequential storage elements• Transitions: change of state• Clock: controls when state can change by
controlling storage elements
• Sequential Logic– Sequences through a series of states– Based on sequence of values on input signals– Clock period defines elements of sequence
9/23/04 EECS150 F04 Culler Lec 8 5
Outline
• Review• Typical uses of FSMs• Synchronous Seq. Circuits – safe composition• Timing• FSMs in verilog (reinforcing lab lecture)• State reduction and state assignment
9/23/04 EECS150 F04 Culler Lec 8 6
Recall: Parallel to Serial Converter
//Parallel to Serial convertermodule ParToSer(LD, X, out, CLK);
input [3:0] X;input LD, CLK;output out; reg out;reg [3:0] Q;assign out = Q[0];always @ (posedge CLK) begin
if (LD) Q <= X;else Q <= {1’b0,Q[3:1]};
endendmodule // ParToSer
One common use of FSMs is in adapters from one subsystem to another.
• different data widths
• different bit rates
• different protocols, …
9/23/04 EECS150 F04 Culler Lec 8 7
Example: Byte-bit stream
Byte FIFO
pop
Serial link
Shift register
controller
LD
bit 0/pop
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7 / LD
init / LD
9/23/04 EECS150 F04 Culler Lec 8 8
Byte-bit stream with Rate Matching
• How would you implement this FSM?
Byte FIFO
pop
Serial link
Shift register
controller
LD
bit 0/pop
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7 / LD
init / LD
rdy
bit 0’
~rdy
~rdyrdy
~rdyrdy
~rdyrdy
~rdyrdy
~rdyrdy
~rdyrdy
~rdyrdy
~rdyrdy
9/23/04 EECS150 F04 Culler Lec 8 9
Another example: bus protocols• A bus is:
– shared communication link– single set of wires used to connect multiple subsystems
• A Bus is also a fundamental tool for composing large, complex systems (more later in the term)
– systematic means of abstraction
Control
Datapath
Memory
ProcessorInput
Output
9/23/04 EECS150 F04 Culler Lec 8 10
Example: Pentium System Organization
Processor/MemoryBus
PCI Bus
I/O Busses
9/23/04 EECS150 F04 Culler Lec 8 11
Arbitration for the bus…
• Central arbitration shown here– Used in essentially all processor-memory busses and in high-
speed I/O busses
BusArbiter
Device 1 Device NDevice 2
Grant Req
9/23/04 EECS150 F04 Culler Lec 8 12
Simple Synchronous Protocol
• Even memory busses are more complex than this– memory (slave) may take time to respond– it need to control data rate
BReq
BG
Rd+AddrCMDAddress
Data1 Data2Data
I want the bus
nopeYou got it
I still want the bus
Mem grabs addr
Proc grabs data
I’m done after this
9/23/04 EECS150 F04 Culler Lec 8 13
Processor Side of Protocol - sketch
• Memory waits?• Additional outputs?• Memory side?
Idle
~BR
Request bus
BR
Address
BR,RD, addr_enable
proc read
BG
Data 1
BR, MDR_enable
Data 2
~BR, MDR_enable
~BG
9/23/04 EECS150 F04 Culler Lec 8 14
Simple Synchronous Protocol (cont)
BReq
BG
Rd+AddrCMDAddress
Data1 Data2Data
I want the bus
nopeYou got it
I still want the bus
Mem grabs addr
Proc grabs data
I’m done after this
idle req req w-addr r-data1 r-data2 idle
9/23/04 EECS150 F04 Culler Lec 8 15
Fundamental Design Principle
• Divide circuit into combinational logic and state• Localize feedback loops and make it easy to break
cycles• Implementation of storage elements leads to various
forms of sequential logic
�� ��� ����������
� ��������� �� �
� � �� �
� � ��� � �� �� � ������ �
���� �
9/23/04 EECS150 F04 Culler Lec 8 16
Forms of Sequential Logic
• Asynchronous sequential logic – “state” changes occur whenever state inputs change (elements may be simple wires or delay elements)
• Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock)
�����
9/23/04 EECS150 F04 Culler Lec 8 17
General Model of Synchronous Circuit
• All wires, except clock, may be multiple bits wide.
• Registers (reg)– collections of flip-flops
• clock– distributed to all flip-flops– typical rate?
• Combinational Logic Blocks (CL)– no internal state (no feedback)– output only a function of inputs
• Particular inputs/outputs are optional
• Optional Feedback• ALL CYCLES GO THROUGH A REG!
reg regCL CL
clock input
output
option feedback
input output
9/23/04 EECS150 F04 Culler Lec 8 18
Composing FSMs into larger designs
CL
FSM FSM
CL
9/23/04 EECS150 F04 Culler Lec 8 19
Composing Moore FSMs
• Synchronous design methodology preserved
CL
Moore Moore
CL
state
outputnext
state
state
outputnext
state
9/23/04 EECS150 F04 Culler Lec 8 20
Composing Mealy FSMs …
• Synchronous design methodology violated!!!• Why do designers used them?
– Few states, often more natural in isolation– Safe if latch all the outputs
» Looks like a mealy machine, but isn’t really» What happens to the timing?
CL
Mealy FSM
CLstate
Output
Next
state
state
Output
Next
state
9/23/04 EECS150 F04 Culler Lec 8 21
FSM timing
Clock
Inputs
Outputs
State Time(Clock Period)
State register propagation delay
Output logic propagation delay
How long must this be?
State (internal)
• What determines min FSM cycle time (max clock rate)?
What determines this?
9/23/04 EECS150 F04 Culler Lec 8 22
Announcements
• Reading 8.4,7.4, 8.1• We touched on ideas from chapter 11, not in
reader. Will be available on line.
9/23/04 EECS150 F04 Culler Lec 8 23
Finite State Machines in Verilog
inputsMoore outputs
Mealy outputs
next state
current state
combinationallogic
combinationallogic
9/23/04 EECS150 F04 Culler Lec 8 24
module Reduce(Out, Clock, Reset, In);output Out;input Clock, Reset, In;
reg Out;reg [1:0] CurrentState; // state registerreg [1:0] NextState;
// State assignmentlocalparam STATE_Zero = 2’h0,
STATE_One1 = 2’h1,STATE_Two1s = 2’h2,STATE_X = 2’hX;
Verilog FSM - Reduce 1s example
• Change the first 1 to 0 in each string of 1’s– Example Moore machine implementation
�
�
�
�
��
����
���
���
���
����
���
9/23/04 EECS150 F04 Culler Lec 8 25
always @(In or CurrentState) beginNextState = CurrentState;Out = 1’b0;case (CurrentState)
STATE_Zero: begin // last input was a zeroif (In) NextState = STATE_One1;
endSTATE_One1: begin // we've seen one 1
if (In) NextState = STATE_Two1s;else NextState = STATE_Zero;
endSTATE_Two1s: begin // we've seen at least 2 ones
Out = 1;if (~In) NextState = STATE_Zero;
enddefault: begin // in case we reach a bad state
Out = 1’bx;NextState = STATE_X;
endendcase
end
Moore Verilog FSM: combinational part
�
�
�
�
��
����
���
���
���
����
���
�������������������� �� ��������� � ��� � �������� �� ����� ����
Compute: output = G(state)
next state = F(state, in) 9/23/04 EECS150 F04 Culler Lec 8 26
// Implement the state registeralways @ (posedge Clock) begin
if (Reset) CurrentState <= STATE_Zero;else CurrentState <= NextState;
endendmodule
Moore Verilog FSM: state part
�
�
�
�
��
����
���
���
���
����
���Note: posedge Clock requires NONBLOCKING ASSIGNMENT.
Blocking Assignment <-> Combinational Logic
Nonblocking Assignment <-> Sequential Logic (Registers)
9/23/04 EECS150 F04 Culler Lec 8 27
module Reduce(Clock, Reset, In, Out);input Clock, Reset, In;output Out;reg Out;reg CurrentState; // state registerreg NextState;
localparam STATE_Zero = 1’b0,STATE_One = 1’b1;
always @(posedge Clock) beginif (Reset) CurrentState <= STATE_Zero;else CurrentState <= NextState;
end
always @ (In or CurrentState) beginNextState = CurrentState;Out = 1’b0;case (CurrentState)
zero: if (In) NextState = STATE_One;one: begin // we've seen one 1
if (In) NextState = STATE_One;else NextState = STATE_Zero;Out = In;
endendcase
endendmodule
Mealy Verilog FSM for Reduce-1s example
� �� �
� �
� �
����
���
���
���
Note: smaller state machine
Output = G(state, input)
9/23/04 EECS150 F04 Culler Lec 8 28
Restricted FSM Implementation Style
• Mealy machine requires two always blocks– Register needs posedge Clock block– Input to output needs combinational block
• Moore machine can be done with one always block, but….– E.g. simple counter– Very bad idea for general FSMs
» This will cost you hours of confusion, don’t try it» We will not accept labs with this style for general FSMs
– Use two always blocks!
• Moore outputs– Share with state register, use suitable state encoding
9/23/04 EECS150 F04 Culler Lec 8 29
module reduce (clk, reset, in, out);input clk, reset, in;output out;reg out;reg [1:0] state; // state registerparameter zero = 0, one1 = 1, two1s = 2;
Single-always Moore Machine (Not Allowed!)
�
�
�
�
��
����
���
���
���
����
���
9/23/04 EECS150 F04 Culler Lec 8 30
always @(posedge clk)case (state)zero: begin
out <= 0;if (in) state <= one1;else state <= zero;
endone1:
if (in) beginstate <= two1s;out <= 1;
end else beginstate <= zero;out <= 0;
endtwo1s:
if (in) beginstate <= two1s;out <= 1;
end else beginstate <= zero;out <= 0;
enddefault: begin
state <= zero;out <= 0;
endendcase
endmodule
� ���������������� � ���� �� �������� ��������� ��� �����! �������"���
Single-always Moore Machine (Not Allowed!)
# ����� �� ����������� ����
9/23/04 EECS150 F04 Culler Lec 8 31
Finite State Machines
•
• Recommended FSM implementation style– Implement combinational logic using one always block– Implement an explicit state register using a second always
block
inputsMoore outputs
Mealy outputs
next state
current state
combinationallogic
combinationallogic
9/23/04 EECS150 F04 Culler Lec 8 32
FSM Optimization
• State Reduction:Motivation:
lower cost» fewer flip-flops in one-
hot implementations» possibly fewer flip-
flops in encoded implementations
» more don’t cares in NS logic
» fewer gates in NS logic
Simpler to design with extra states then reduce later.
• Example: Odd parity checker.Two machines - identical behavior.
S0[0]
S1[1]
S2[0]
0
1
11
0
0
S0[0]
S1[1]
0
1
0
1
9/23/04 EECS150 F04 Culler Lec 8 33
State Reduction• State Reduction is based
on:Two states are equivalent if, for
each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.
If two states are equivalent, one can be eliminated without effecting the behavior of the FSM.
• Several algorithms exist:– Row matching method.– Implication table method.
• “Row Matching” is based on the state-transition table:
If two states have the same output, and both transition to the same next state, orboth transition to each other, or both self-loop, then they are equivalent.
Combine the equivalent states into a new renamed state.
Repeat until no more states are combined.
– Note: This algorithm is slightly different than the book.
9/23/04 EECS150 F04 Culler Lec 8 34
Row Matching Example
NS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f g f 0 1g a f 0 1
State Transition Table
9/23/04 EECS150 F04 Culler Lec 8 35
Row Matching Example (cont)NS output
PS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f e f 0 1
NS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e d 0 1e a d 0 1
Reduced State Transition Diagram
9/23/04 EECS150 F04 Culler Lec 8 36
State Reduction
• The “row matching” method is not guaranteed to result in the optimal solution in all cases, because it only looks at pairs of states.
• For example:
• Another (more complicated) method guarantees the optimal solution:
• “Implication table” method:cf. Mano, chapter 9
• What ‘rule of thumb”heuristics?
S0
S1
S2
0/1
1/0
1/01/0
0/1
0/1
9/23/04 EECS150 F04 Culler Lec 8 37
State Maps
S0
S2
S3
S1
S4 00 01 11 10
0 S0 S4 S3
1 S1 S2
q1 q0
q2 00 01 11 10
0 S0 S1 S3 S2
1 S4
q1 q0
q2
AssignmentState q2 q1 q0
S0 0 0 0S1 1 0 1S2 1 1 1S3 0 1 0S4 0 1 1
AssignmentState q2 q1 q0
S0 0 0 0S1 0 0 1S2 0 1 0S3 0 1 1S4 1 1 1
• “K-maps” are used to help visualize good encodings.• Adjacent states in the STD should be made adjacent in
the map.
9/23/04 EECS150 F04 Culler Lec 8 38
State AssignmentAlternative heuristics based on input and output behavior as well
as transitions:Adjacent assignments to:
states that share a common next state(group 1's in next state map)
states that share a common ancestor state(group 1's in next state map)
states that have common output behavior(group 1's in output map)
Highest Priority
Medium Priority
Lowest Priority
i/j i/k
i/j i/j
αααα
αααα
αααα
ββββ
ββββ
ββββ
9/23/04 EECS150 F04 Culler Lec 8 39
Summary
• FSMs are critical tool in your design toolbox– Adapters, Protocols, Datapath Controllers, …
• They often interact with other FSMs• Important to design each well and to make them
work together well.• Keep your verilog FSMs clean
– Separate combinational part from state update
• Good state machine design is an iterative process– State encoding– Reduction– Assignment