by Dominic Plunkett Chief Technical OfficerXJTAG dominic.plunkett@xjtag.com

Pádraig KellyIC Design EngineerXilinx, Inc.padraig.kelly@xilinx.com

Engineers typically use the boundary scanchain to program devices such as CPLDsor flash memories. But more engineersshould be tapping into the power ofboundary scan as a way of extractingdetailed information about how boards orsystems are functioning.

With the recent introduction of theXilinx® System Monitor function insidethe latest Virtex™-5 FPGAs, you can nowcollect voltage and temperature informa-tion from within the FPGA using the sameJoint Test Action Group (JTAG) test accessport (TAP) traditionally used for boundaryscan functions and programming devices.

And by using equipment and test scriptsprovided by Xilinx partner XJTAG, or bywriting your own scripts, you can more eas-ily verify analog signals at various points inthe circuit from within the boundary scan

test environment. XJTAG’s boundary scantest system helps engineers test devicessuch as discrete temperature sensors,DACs, or VGA ports.

System Monitor: A Device-Level Test ProbeThe System Monitor is analog circuitrywithin the Xilinx Virtex-5 FPGA architec-ture that samples on-chip temperature andvoltage (Figure 1). The dedicated SystemMonitor circuitry – which is built arounda 200-ksps ADC by default – performs acontinuous sequence of measurements onthe FPGA die temperature, as well asVCCINT and VCCAUX supply voltage levels.This feature in Virtex-5 devices eliminatesthe added complexity and cost of imple-menting external monitoring componentsto a system.

Moreover, the System Monitor featureallows you to take power supply meas-urements from the die itself (inside thepackage), which is not possible using anexternal ADC.

You can also use System Monitor to getaccurate thermal readings. Traditionally,engineers used thermal diodes to monitordie temperatures, but they had to pay care-ful attention to the PCB layout becausediode measurements are highly sensitive to

noise from other devices and features onthe PCB, as well as other implementationdetails such as signal offsets and tolerances.The new System Monitor gets around thatissue. It incorporates a temperature sensoron the FPGA die to allow you to take accu-rate temperature readings from the dieitself (Figure 2).

These power and thermal monitoringcapabilities allow for the implementationof safety functions such as power-on self-check or over-temperature power down.System Monitor’s internal power supplymeasurements are accurate to within±1%, while monitoring of the on-chiptemperature sensor is accurate to ±4 °C inthe -40 °C to 125 °C range.

The System Monitor circuitry alsoincludes an integrated multiplexer that notonly supports inputs for the two on-chipvoltage-sensing channels and temperaturesensor, but also accepts inputs from asmany as 17 additional analog sources exter-nal to the FPGA. This means that you canuse System Monitor to monitor variousoff-chip analog signals. It supports off-chipinputs that are single-ended or differentialsignals, up to 1.0V in amplitude; thus, youcan connect to many types of sensors,including shunt resistor-based current sen-

32 Xcell Journal Third Quarter 2008

Using the JTAG Chain for Accurate System and Intra-Die Power and Thermal Analysis

Using the JTAG Chain for Accurate System and Intra-Die Power and Thermal Analysis New boundary scan techniques using Xilinx System Monitor test more aspects of system behavior.New boundary scan techniques using Xilinx System Monitor test more aspects of system behavior.

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sors, accelerometers, position sensors, andexternal temperature sensors.

The System Monitor control systemalso includes an automatic channelsequencer that allows you to define whichparameters you want to monitor. You con-figure System Monitor by setting up itscontrol registers. To do this, simply instan-tiate System Monitor in your design orwrite to the control registers over JTAG.The Xilinx ISE™ software tool suite alsoincludes a utility called the System Monitorarchitecture wizard to walk you throughthe instantiation process.

Turning on the TAPBy designing System Monitor to deliverthis data directly to the FPGA’s JTAG TAP,Xilinx has opened up many new opportu-nities for extracting detailed informationfrom prototype or production systems.Moreover, you can import the data intoboundary scan test gear that operates at ahigh level of abstraction.

type device packages because the ballpitch is so fine and is located under thedevice’s body. And as the industryincreasingly uses these packages in newICs, it is effectively reducing the amountof test coverage you can achieve usingconventional test techniques.

Boundary scan testing, as defined by theJoint Test Action Group and ratified asIEEE1149.1, specifies a four-wire TAP andboundary scan architecture that engineerscan implement in their IC designs to facil-itate product testing later in the IC devel-opment cycle. The four-wire TAP interfaceallows engineers to read values into and outof pins or internal registers of JTAGdevices. And with access to these pins, youcan debug and test other devices on the cir-cuit board, such as FPGAs, EEPROMs,RAMs, and flash memory.

Using boundary scan test equipment,you can perform quick net-level diagnos-tics without having to rely on embeddedtest software or functional tests. The PCBdoesn’t need to be running for you to useit, so you can quickly verify basic func-tionality as soon as first prototypes returnfrom assembly, even if the board will notboot up. You can also carry out basicchecks, toggling individual pins or buses

Although most engineers are familiarwith using boundary scan to programdevices in situ, many remain unaware of itspower as an unobtrusive debugging andtest solution. Applying tests through theJTAG TAP means that you no longer needto physically attach test probes to a devel-opment board or production assembly.Attaching probes is time-consuming andleaves the test strategy vulnerable to errors.

More importantly, it is impossible tophysically probe modern BGA- and CSP-

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System Monitor

ADCMUX

On-ChipSensors

StatusRegisters

ControlRegisters

DRP

ArbitratorJTAG

Inteconnect

17 External Channels

Virtex-5 FPGA System Monitor

System MonitorLocated in the

Center of the Die

On-Chip Temperature andSupply Measurement

Easy Access to On-Chip Measurements at Any Time

JTAG TAP

.....11101010100010101001010111...

Figure 1 – System Monitor allows you to monitor voltages and temperature of a Virtex-5 FPGA die and as many as 17 other analog sources that can impact overall system performance.

Thrid Quarter 2008 Xcell Journal 33

Figure 2 – The System Monitor sensor,located in the center of the Virtex-5device die, provides valuable on-chipvoltage and temperature data accessibleduring product development, when thedevice is in mass production, or evenafter deployment in the field.

to locate shorts, breaks, poor joints, orincorrect connections.

The test ports of all JTAG devices in thesystem are interconnected at the boardlevel, setting up a serial scan chain that youcan access through a single connector at theedge of the board. As the numbers ofJTAG-compliant devices per boardincrease, emerging JTAG testers can accessa greater proportion of the total nets, there-by increasing overall test coverage.

By manipulating the scan chain to set upsuitable test patterns, you can also collect

responses from components that do notoffer a boundary scan test interface, provid-ed that the components you want to accessare connected to the same net as a compli-ant device. This technique is sometimesreferred to as cluster testing, and provides away to test non-JTAG devices such as exter-nal connectors, video chips, IIC devices,Ethernet controllers, LEDs, or switches.

For example, you can also use the JTAGchain to drive an Ethernet test packet to anon-JTAG Ethernet controller on theboard and verify its response (Figure 3).Similarly, it is possible to test SRAMdevices, as well as SDRAM, DDR, andDDR2 chips – even though these are notJTAG-enabled. These examples show how

modern boundary scan equipment, such asthe XJTAG system, has raised achievabletest coverage by using the JTAG chain to itsmaximum potential. In practice, XJTAGcustomers are now achieving more than90% test coverage for complex boards.

Extending Boundary Scan CapabilitiesNow that Xilinx System Monitor allowsyou to easily collect analog values frominside Virtex-5 FPGAs, those of youalready familiar with boundary scan testingcan apply yet another valuable set of tests

through the TAP. Virtex-5 device users canimport data from the 17 external analogchannels into the boundary scan test envi-ronment through System Monitor.

The use of the Virtex-5 SystemMonitor feature requires PCB designengineers to follow a certain minimal setof design guidelines. These guidelines aredocumented in the applications section ofthe Virtex-5 System Monitor User Guide(www.xilinx.com/support/documentation/user_guides/ug192.pdf).

Once the PCB support is in place, it’stime to take advantage of System Monitor’smany capabilities. For example, becausethe System Monitor ADC is operational onpower-up, you can extract valuable system

information using the boundary scan chaineven before configuring the FPGA. Thisallows development engineers, for example,to verify system power rails and assess basiccooling provisions before finalizing theFPGA configuration.

Because Xilinx implemented the sam-pling circuitry in hardware on the FPGAsilicon, you can apply the System Monitorfunctions at any time in the product lifecy-cle. For example, if a system exhibits per-sistent overheating or if a power supplystarts to exhibit signs that it is defective inthe lab or even in the field, you can imme-diately apply a test to read the SystemMonitor data through the JTAG TAP with-out reconfiguring the FPGA.

XJTAG Simplifies Emerging Uses of Boundary ScanEngineers at XJTAG, working with Xilinxand the Virtex-5 LXT ML505 develop-ment board, developed several turnkey testscripts that allow XJTAG boundary scantest solution users to access data fromSystem Monitor. XJTAG can display dietemperature, supply voltages, and off-chipanalog values directly onto a workstation,and it allows you to verify that the valuesSystem Monitor and XJTAG collect arewithin specified tolerances.

Figure 4 is a code snippet of a simpleset of tests that users can generate inXJTAG’s high-level scripting language,XJEase, to check the operating parametersof the Virtex-5 FPGA. In the function callTest, you first configure System Monitor.The test then reads individual inputs andchecks them.

Figure 5 shows code that checks thedevice’s temperature. If the temperature isout of tolerances, the test displays an error.This example shows how you can accessVirtex-5 System Monitor using simplefunctions provided on the XJTAG website.

XJTAG also supports customized teststhat can, for example, record System

36 Xcell Journal Third Quarter 2008

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FPGA CPLD

MICROor

DSP

Address

Data

JTA

G P

ort

LED I2C

EEPROM

Flas

h

Loop

back

RJ4

5

ETH

ERN

ET

SDR

AM

Figure 3 – Thanks to the growing JTAG compliance in modern PCB design, you can use boundary scan to perform many more types of tasks and tests.

Engineers at XJTAG, working with Xilinx and the Virtex-5 LXT ML505 development board, developed several turnkey test scripts that allow XJTAG

boundary scan test solution users to access data from System Monitor.

Third Quarter 2008 Xcell Journal 37

Monitor data for fault detection or trace-ability purposes. You can also write scriptsto have XJTAG check for peak values,respond to thresholds, or apply an averagingalgorithm to the data from System Monitor.

You can create scripts using XJEase,which XJTAG includes as part of theXJTAG environment. XJEase allows you towork at a high level of abstraction from theraw boundary scan data. You can also writetest scripts specifically for devices, whetheror not the devices are in the boundary scanchain. You can store these scripts and evenreuse them for future projects.

XJTAG will generate a new testsequence automatically each time thenetlist data indicates a change to theboard, which saves you from manuallyrewriting the test routine. In contrast,older types of boundary scan test equip-ment typically produce board-centric testsequences that are laborious to updatewith each design change.

As this device-centric scan approach totest development increases in popularitywithin the engineering community, manyXJTAG users have begun posting theirproven pre-written scripts on XJTAG’swebsite. Customers who have current sup-port contracts with XJTAG can downloadthese scripts from www.xjtag.com free ofcharge and incorporate them into their testroutines. And if the website does not havethe exact device you are looking for, simplydownload a similar script and customize itfor the device you want to test.

Scanning the FutureThe scope of the interactions possiblebetween System Monitor and XJTAGhighlights the potential for boundary scantest systems to support innovative on-chipfeatures supporting verification, debug-ging, parameterization, and calibration. Byaccessing silicon features implemented inthe core of FPGAs – or other devices suchas processors, memories, or control ICs – itbecomes possible for boundary scan to per-form functions such as virtualizing DIPswitches, calibrating digital filters, oradjusting analog settings or threshold val-ues. Plus, you can now achieve this quick-ly, whether the product is at thedevelopment stage, in volume production,or operating in the field.

For engineers already using the bound-ary scan chain to test the functional nets ofprototype or production assemblies, SystemMonitor now allows vital-signs monitoringfrom within the boundary scan environ-ment. Those of you who are more ambi-tious will certainly step up and takeadvantage of this new ability to see evenmore deeply into the system. And in thefuture, as the technique becomes moremainstream, expect to see customized testscripts that reach into even the most inac-cessible aspects of product designs.

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//----------------------------

Test()(INT result)

//----------------------------

INT temp;

result := 0;

Config_SysMon()();

Read_Internal_Temp()(result);

Read_VAUX()(result);

Read_VINT()(result);

Read_RefP()(result);

Read_RefN()(result);

IF (result != 0) THEN

result := RESULT_FAIL;

ELSE

result := RESULT_PASS;

END;

END;

//----------------------------------------------------------------------------------

Read_Internal_Temp()(INT result)

//----------------------------------------------------------------------------------

INT temp;

Read_Temp()(temp);

IF ((temp < (Die_Temp - Temp_Margin)) || (temp > (Die_Temp + Temp_Margin))) THEN

PRINT("Die temperature = ",temp,"C. ** OUTSIDE LIMITS **\n");

result := result + 1;

ELSIF (DEBUG) THEN

PRINT("Die temperature = ",temp,"C\n");

END;

END;

//----------------------------------------------------------------------------------

Read_Temp()(INT temp)

//----------------------------------------------------------------------------------

Read_Channel(0)(temp);

temp := ((temp * 20159) / 40960) - 273;

END;

Figure 4 – Code snippet showing how to set up and test some of the System Monitor inputs using the XJEase scripting language.

Figure 5 – Code snippet for testing the temperature of the Virtex-5 FPGA