V8/Issue 2/2013 2 6 32 - Applied Materials

Fabs in the Internet of Things era

2 6 32

F a b S o l u t i o n S

Fab-wide Effort Increases Yield at CMOS Imager Facility in Italy

Partnering with Customers to Improve Yield

Power Struggle: As Mobile Systems Offer Additional MEMS Sensors, Power Is a Primary Challenge

V8/Issue 2/2013

Solutions for Factory and Equipment Efficiency

NaNochip 1

So we hope you’re now enjoying our December 2013 issue in one of its two new online versions, each designed to give you the most enjoyable and efficient reader experience possible.

Our Nanochip Fab Solutions electronic flipbook includes high-resolution images and makes it easy to select, read, print or download a PDF of articles that interest you. In addition to the flipbook, the email we send you announcing each issue features individual links to every article. Clicking on an article title will take you directly to a web page where you can read a simplified version. No downloading, no waiting, and formatted for reading on a phone, tablet or computer.

Rest assured, though, that we will continue to print Nanochip Fab Solutions for anyone who prefers to receive a hard copy. If you’ve already registered to receive a printed copy we’ll keep sending to you as usual. If you’ve changed companies or have new contact information, or if you’d like to start receiving print copies, just e-mail us at [email protected]. There’s no charge to subscribe, and doing so will ensure that you receive a copy of every issue.

Although traditionally we publish Nanochip Fab Solutions twice a year (summer and winter), we understand that many of you would like us to publish more frequently. This fall we piloted a new electronic-only edition called Nanochip Express. This streamlined email version of the magazine features a handful of shorter articles, and will be published in the fall and spring, in between our semi-annual issues of the full-length magazine.

As for the content of our publications, we’ll continue to make it as engaging and relevant as we can. This issue of Nanochip Fab Solutions focuses on how the Internet of Things is challenging manufacturers to create connected fabs, and we look at the struggle to power sensors and other components for mobile devices without compromising battery life.

We also consider yield improvement, with three articles that examine this critical issue from different perspectives. On the personal side, STMicroeletronics executive Orio Bellezza tells us how his company is using “clusters of competencies” to take the lead in several key markets. And an in-depth interview with Applied Global Services (AGS) chief, Charlie Pappis discusses the growing complexity of fab operations and how AGS is “retooling” its service offerings and delivery to keep pace. Finally, we wrap-up with Dave Lammers’ insightful look at the technology transitions that lie ahead in 2014.

Speaking of technology transitions, we encourage you to email us at the address above to let us know what you think of our new electronic formats—and the kinds of articles you’d like to see next year. Whether you read Nanochip Fab Solutions as a flipbook, a series of web articles, or a printed magazine, what’s important is that you keep reading. As long as you do, we’ll keep publishing.

Dana tribulaVP, Strategy anD CMo,

aPPlieD global SerViCeS; exeCutiVe PubliSher,

nanoChiP Fab SolutionS

Our new electrOnic delivery system Will Make you flip

A Message from Our Publisher

Contents

PluS:

31: Helping Customers Improve Equipment and Fab Productivity

32: METHODOLOGY FEATURE: Partnering With Customers to Improve Yield

37: The Last Word: A Look at 2014


E x E c u t i v E p u b l i s h E r Dana Tribula

[email protected]

p u b l i s h E r Peggy Marcucci

[email protected]

E D i t O r - i N - c h i E F Liz Baird

[email protected]

c O N t r i b u t i N G E D i t O r s Gary Dagastine David Lammers

Jill O’Nan

D E s i G N Jane Olson Graphic Design

NANOCHIP is published by Applied Materials, Inc.

© Copyright Applied Materials, Inc., 2013

www.appliedmaterials.com

Nanochip Fab Solutions is now delivered in an environment-friendly online version. Printed copies are available upon request.

For a free subscription, or to add colleagues to the mailing list,

please send an email to [email protected]

with the following information: • Name • Title • Company • Business address • Business email*

*Sorry—no general accounts, e.g., Gmail, AOL, Yahoo

All trademarks so designated or otherwise indicated as product names

or services are trademarks of Applied Materials, Inc. in the U.S. and other countries. All other product and

service marks contained herein are trademarks of their respective owners.

nanoChipf a B s o l u t i o n s

—pages that is. For more than a year now we’ve given our readers the option of receiving Nanochip Fab Solutions in PDF format. You loved the idea of going green and saving trees, but scrolling through a PDF document just wasn’t the same as flipping through the pages of a magazine.

When Good Parts Go Bad:

Repair or Replace? 18

6Power Struggle: As Mobile Systems Offer

Additional MEMS Sensors, Power Is a Primary Challenge

10STMicroelectronics:

On Top of Key Markets

14New Controller Extends Life of 200mm Tools

2 Fab-wide Effort Increases Yield at CMOS Imager Facility in Italy

20 Fabs in the Internet of Things Era

24Improving Yield with

Fleet Chamber Matching

Charlie Pappis: Serving Up a Better Outcome

28

1A Message from

Our Publisher

NaNochip 1

So we hope you’re now enjoying our December 2013 issue in one of its two new online versions, each designed to give you the most enjoyable and efficient reader experience possible.

Our Nanochip Fab Solutions electronic flipbook includes high-resolution images and makes it easy to select, read, print or download a PDF of articles that interest you. In addition to the flipbook, the email we send you announcing each issue features individual links to every article. Clicking on an article title will take you directly to a web page where you can read a simplified version. No downloading, no waiting, and formatted for reading on a phone, tablet or computer.

Rest assured, though, that we will continue to print Nanochip Fab Solutions for anyone who prefers to receive a hard copy. If you’ve already registered to receive a printed copy we’ll keep sending to you as usual. If you’ve changed companies or have new contact information, or if you’d like to start receiving print copies, just e-mail us at [email protected]. There’s no charge to subscribe, and doing so will ensure that you receive a copy of every issue.

Although traditionally we publish Nanochip Fab Solutions twice a year (summer and winter), we understand that many of you would like us to publish more frequently. This fall we piloted a new electronic-only edition called Nanochip Express. This streamlined email version of the magazine features a handful of shorter articles, and will be published in the fall and spring, in between our semi-annual issues of the full-length magazine.

As for the content of our publications, we’ll continue to make it as engaging and relevant as we can. This issue of Nanochip Fab Solutions focuses on how the Internet of Things is challenging manufacturers to create connected fabs, and we look at the struggle to power sensors and other components for mobile devices without compromising battery life.

We also consider yield improvement, with three articles that examine this critical issue from different perspectives. On the personal side, STMicroeletronics executive Orio Bellezza tells us how his company is using “clusters of competencies” to take the lead in several key markets. And an in-depth interview with Applied Global Services (AGS) chief, Charlie Pappis discusses the growing complexity of fab operations and how AGS is “retooling” its service offerings and delivery to keep pace. Finally, we wrap-up with Dave Lammers’ insightful look at the technology transitions that lie ahead in 2014.

Speaking of technology transitions, we encourage you to email us at the address above to let us know what you think of our new electronic formats—and the kinds of articles you’d like to see next year. Whether you read Nanochip Fab Solutions as a flipbook, a series of web articles, or a printed magazine, what’s important is that you keep reading. As long as you do, we’ll keep publishing.

Dana tribulaVP, Strategy anD CMo,

aPPlieD global SerViCeS; exeCutiVe PubliSher,

nanoChiP Fab SolutionS

Our new electrOnic delivery system Will Make you flip

A Message from Our Publisher

Contents

PluS:

31: Helping Customers Improve Equipment and Fab Productivity

32: METHODOLOGY FEATURE: Partnering With Customers to Improve Yield

37: The Last Word: A Look at 2014


E x E c u t i v E p u b l i s h E r Dana Tribula

[email protected]

p u b l i s h E r Peggy Marcucci

[email protected]

E D i t O r - i N - c h i E F Liz Baird

[email protected]

c O N t r i b u t i N G E D i t O r s Gary Dagastine David Lammers

Jill O’Nan

D E s i G N Jane Olson Graphic Design

NANOCHIP is published by Applied Materials, Inc.

© Copyright Applied Materials, Inc., 2013


Nanochip Fab Solutions is now delivered in an environment-friendly online version. Printed copies are available upon request.

For a free subscription, or to add colleagues to the mailing list,

please send an email to [email protected]

with the following information: • Name • Title • Company • Business address • Business email*

*Sorry—no general accounts, e.g., Gmail, AOL, Yahoo

All trademarks so designated or otherwise indicated as product names

or services are trademarks of Applied Materials, Inc. in the U.S. and other countries. All other product and

service marks contained herein are trademarks of their respective owners.

nanoChipf a B s o l u t i o n s

—pages that is. For more than a year now we’ve given our readers the option of receiving Nanochip Fab Solutions in PDF format. You loved the idea of going green and saving trees, but scrolling through a PDF document just wasn’t the same as flipping through the pages of a magazine.

When Good Parts Go Bad:

Repair or Replace? 18

6Power Struggle: As Mobile Systems Offer

Additional MEMS Sensors, Power Is a Primary Challenge

10STMicroelectronics:

On Top of Key Markets

14New Controller Extends Life of 200mm Tools

2 Fab-wide Effort Increases Yield at CMOS Imager Facility in Italy

20 Fabs in the Internet of Things Era

24Improving Yield with

Fleet Chamber Matching

Charlie Pappis: Serving Up a Better Outcome

28

1A Message from

Our Publisher

NaNochipNaNochip2 3

The goal of Applied’s FabVantage consulting group is to help customers increase their operational capability with respect to cost, efficiency and yield. FabVantage consultants address customer productivity and yield issues by combining the skills and knowledge of seasoned fab experts with state-of-the-art modeling and analysis tools, and Applied’s deep systems and technology roots.

A good example of the benefits of this collaboration are the results of an extensive fab-wide engagement encompassing about 10 separateprojects that took place at a CMOS image sensor array fab in Avezzano, Italy. The fab is run by Marsica Innovation & Technology srl (MIT), an operating company of the joint venture between LFoundry Europe and Marsica Innovation SpA.

For each of 12 tool-types, the team audited tools and recipes, and used sensor- and on-wafer data to pinpoint key issues. By leveraging best known practices and specific expertise, the team made recommendations toimprove performance. In most cases, proposed solutions were first tested on a golden tool. Successful solutions then were fanned out to the entire fleet. As the work progressed, the team evaluated not only individual

chambers and tools, but also looked at some aspects of production from a more integrated perspective, examining several tools that together were engaged in carrying out specific process steps.

Here are a few examples showing how yield improvements were achieved.

mOdiFied etcH PrOcess reduces device leAKAGe

On one etch tool, excessivetransistor current leakage was observed following an oxide spacer etch step. When fab personnel tried to address the problem through preventive maintenance and auto-cleanings, the leakage became even worse.

A detailed recipe and process audit was initiated. The FabVantage team determined the root cause of the problem to be a recipe with low oxide-to-polysilicon sensitivity, which sometimes led to over-etching into the silicon substrate. Further complicating the matter, this over-etching was not uniform across the tool’s chambers.

Applied and the customer identified an optimized recipe as the best solution (see figure 1). It was also determined that the chamber lid temperature set point varied from

chamber to chamber, which caused nonuniform etching across chambers. In addition, sensor trace analysis and Applied’s best known methods (BKMs) were used to optimize the etch process to eliminate voltage spikes that are known to lead toyield loss.

Better cOntrOl OF vAriABility in rtP PrOcess

Elsewhere, there was significant variability in the performance of a rapid thermal processing (RTP)tool at a new technology node, with resulting transistor performanceissues across wafers.

Audits of hardware, maintenancepractices, process recipes, and fault detection and classification(FDC) analyses identified the tool’stemperature profile as the root cause of the process variability. Excessivetemperatures during ramp-up turned out to be the specific cause of the transistor performance problems. Additionally, the team found other temperature issues that impacted the tool’s ability to achieve targeted yields. These were excessive temperaturedifferences among heater zonesduring the stabilization phase of the process, and poor temperature control during spike anneal.

Figure 1. A recipe with low oxide-to-polysilicon sensitivity sometimes led to over-etching into the silicon substrate (figure 1a left). A new recipe eliminated the problem (figure 1a right). The graph compares the oxide-to-polysilicon sensitivity of several of Applied’s proposed recipe changes with the customer’s original recipe (figure 1b).

(1a) (1b)

Manufacturers must continually refine and improve their operations in order to meet increasingly difficult device performance and yield goals. This article describes a fab-wide engagement in which Applied Materials’ FabVantage consulting group helped one customer solve a variety of yield challenges across a fleet of tools. The result has been a significant and sustainable increase in the fab’s overall yield.

byliMing Zhang anD helen arMer

at CMoS iMager FaCility in italy

faB-WiDe effoRt inCReases yielD

a cAse stuDy

NaNochipNaNochip2 3

The goal of Applied’s FabVantage consulting group is to help customers increase their operational capability with respect to cost, efficiency and yield. FabVantage consultants address customer productivity and yield issues by combining the skills and knowledge of seasoned fab experts with state-of-the-art modeling and analysis tools, and Applied’s deep systems and technology roots.

A good example of the benefits of this collaboration are the results of an extensive fab-wide engagement encompassing about 10 separate projects that took place at a CMOS image sensor array fab in Avezzano, Italy. The fab is run by Marsica Innovation & Technology srl (MIT), an operating company of the joint venture between LFoundry Europe and Marsica Innovation SpA.

For each of 12 tool-types, the team audited tools and recipes, and used sensor- and on-wafer data to pinpoint key issues. By leveraging best known practices and specific expertise, the team made recommendations to improve performance. In most cases, proposed solutions were first tested on a golden tool. Successful solutions then were fanned out to the entire fleet. As the work progressed, the team evaluated not only individual

chambers and tools, but also looked at some aspects of production from a more integrated perspective, examining several tools that together were engaged in carrying out specific process steps.

Here are a few examples showing how yield improvements were achieved.

mOdiFied etcH PrOcess reduces device leAKAGe

On one etch tool, excessive transistor current leakage was observed following an oxide spacer etch step. When fab personnel tried to address the problem through preventive maintenance and auto-cleanings, the leakage became even worse.

A detailed recipe and process audit was initiated. The FabVantage team determined the root cause of the problem to be a recipe with low oxide-to-polysilicon sensitivity, which sometimes led to over-etching into the silicon substrate. Further complicating the matter, this over-etching was not uniform across the tool’s chambers.

Applied and the customer identified an optimized recipe as the best solution (see figure 1). It was also determined that the chamber lid temperature set point varied from

chamber to chamber, which caused nonuniform etching across chambers. In addition, sensor trace analysis and Applied’s best known methods (BKMs) were used to optimize the etch process to eliminate voltage spikes that are known to lead to yield loss.

Better cOntrOl OF vAriABility in rtP PrOcess

Elsewhere, there was significant variability in the performance of a rapid thermal processing (RTP) tool at a new technology node, with resulting transistor performance issues across wafers.

Audits of hardware, maintenance practices, process recipes, and fault detection and classification (FDC) analyses identified the tool’s temperature profile as the root cause of the process variability. Excessive temperatures during ramp-up turned out to be the specific cause of the transistor performance problems. Additionally, the team found other temperature issues that impacted the tool’s ability to achieve targeted yields. These were excessive temperature differences among heater zones during the stabilization phase of the process, and poor temperature control during spike anneal.

Figure 1. A recipe with low oxide-to-polysilicon sensitivity sometimes led to over-etching into the silicon substrate (figure 1a left). A new recipe eliminated the problem (figure 1a right). The graph compares the oxide-to-polysilicon sensitivity of several of Applied’s proposed recipe changes with the customer’s original recipe (figure 1b).

(1a) (1b)

Manufacturers must continually refine andimprove their operations in order to meetincreasingly difficult device performance andyield goals. This article describes a fab-wide engagement in which Applied Materials’ FabVantage consulting group helped onecustomer solve a variety of yield challenges across a fleet of tools. The result has been a significant and sustainable increase in the fab’s overall yield.

byliMing Zhang anDhelen arMer


faB-WiDeeffoRt inCReases yielD

a cAsestuDy

NaNochipNaNochip4 5

implemented a patch to contain the problem, it was costly.

These hillocks were caused by Al film stress, which can be modulated by the temperature of the hot Al deposition step. However, a lower Al de-gas temperature can lead todefects in subsequent steps; therefore a number of related processes need tobe tuned in accordance with changes in Al deposition.

A series of changes to the stack recipe were recommended and implemented, from de-gas to Al reflow, which reduced the number of hillocks by more than half. The results were validated by electrical parametric tests (see figure 5).

tOOl AvAilABility imPrOvement

Other results of the work performed during the fab-wide consulting engagement include:

■■ Greater Availability. The uptime and stability of one PVD tool used to fabricate copper barrier/seed (CuBS) layers was increased by the addition of a new bell jar component. DC bias deterioration was eliminated and RF matching for load and tune positions was stabilized.

■■ Backside Etch Defect Reduction. One Applied Centura tool was experiencing intermittent yield

loss from defects during backside etch. FabVantage consultants identified chamber maintenancepractices as the root cause of the defects. They then recommended and helped implement new procedures for electrostatic chuck (ESC) cleaning and inline defect detection.

■■ Side-to-Side Chamber Mismatch Eliminated. The parameters of devices produced on different sides of one Applied Producer CVD tool’schamber were mismatched. The team determined the tool’sshowerhead was one factor; the second factor was differences in the level of radio frequency (RF) power from one side to the other. A faceplate change at the next preventive maintenance cycle was recommended, and the levelof RF power applied throughout the chamber was optimized and equalized.

The key to successful semiconductor manufacturing is toachieve and maintain the highest possible yields at the lowest possiblecost. As this project demonstrates, well-qualified and experienced consultants such as those in Applied’s FabVantage group, backed by extensive technology resources, can help manufacturers achieve those goals.

Figure 4. Tool hardware and recipe audits of tools in the CoSi loop uncovered several findings that were contributing to poor transistor performance. After optimizing the Co PVD recipe to eliminate transient steps and increase pressure and power, the standard deviation of within-wafer thickness uniformity decreased by almost half (figure 4a) and the standard deviation of within-wafer resistivity declined about 15% (figure 4b). More importantly, resistivity was controlled in a tighter range.

(4a) (4b)

Acknowledgements:Key participants in this project included Laura Bertarelli, Massimo Casella, Marco Crivellari, Francesco Fattibene, Patrick Fernandez, Robert Grimwood, Valeria Lanza and Tony Persico

For additional information, contact [email protected]

Figure 5. The Al hillocks seen at left were caused by Al film stress and were impacting yields from a PVD tool (figure 5a). Applied’s FabVantage consultants recommended a number of ways to reduce film stress, reducing hillock formation by more than half (figure 5b).

(5a)

(5b)

Figure 2. An RTP tool’s system controller was optimized to eliminate temperature overshoots during ramp-up (figure 2a). These can cause oxide growth and dopant out-diffusion, and lead to variations in transistor performance across wafers. Also, the beneficial effects of a recipe change to accommodate higher chamber pressures are shown in figure 2b. The FabVantage team discovered that chamber pressures were causing peak temperature control issues. The new recipe led to more uniform temperatures across heater zones.

(2a)

(2b)



cause of peak temperature control issues, and the recipe was modified to accommodate higher pressures (see figure 2b). Finally, hardware/maintenance practice audits revealed that the tool’s process kit was marginal, and also that preventive maintenance procedures needed to be optimized. The hardware issues were addressed and BKM cleaning procedures were implemented.

deFect reductiOn leAds tO Better cmP

A chemical-mechanical planarization (CMP) tool was unable to achieve targeted yields because of scratches generated during a polishing step. These scratches were being generated at more than three times the number that could be tolerated by the customer’s technology.

The FabVantage team conducted several tool audits to understand the problem and identify solutions. They determined that upstream processes induced particles at the wafer edge that subsequently scratched the wafer during polishing. A multi-faceted solution was recommended and implemented that focused on optimizing slurry delivery, evaluating specific tool components, and conducting upstream preventive maintenance activities in accordance with Applied’s BKMs. The result was a more than 300% reduction in scratches (see figure 3).

Figure 3. Tool audits conducted by the FabVantage team led to a more than 300% reduction in scratches from one CMP tool. The team recommended changes to upstream preventive maintenance procedures in accordance with Applied’s BKMs, and optimized slurry delivery and evaluation of certain tool components.

imPrOved PrOcess stABility

Production and yields from a PVD tool that was trying to run a new recipe were impacted by the complexity of a cobalt silicide (CoSi) deposition loop, which led to widespread transistor leakage and logic timing failures during wafer probe tests.

The FabVantage consultants determined that failures were dependent on product-type, process integration of the CoSi step was marginal, and within-wafer leakage patterns were related to the thickness of the cobalt film—the thicker the Co, the worse the leakage.

The team recommended improved inline electrical parametric tests and test layouts as a way to detect failure mechanisms early, as well as the implementation of a very soft sputter (VSS) etch process prior to Co deposition to improve film uniformity (see figure 4). Modifications to pressure and power to improve process stability were suggested, and the Co PVD recipe was optimized for better within-wafer and wafer-to-wafer thickness uniformity.

OPtimiZed Aluminum dePOsitiOn reduces HillOcKs

One PVD tool was experiencing yield loss with specific device-types because high aluminum (Al) hillocks were being produced by the baseline process. Although the customer had

Temperature overshoots during ramp-up caused oxide growth and dopant out-diffusion, and these effects led to the variation in device performance. In response, the customer and the FabVantage team modified the tool’s system controller to optimize it for the temperature ramp-up step (see figure 2a).

Meanwhile, the recipe audit identified chamber pressure as a

NaNochipNaNochip4 5

implemented a patch to contain the problem, it was costly.

These hillocks were caused by Al film stress, which can be modulated by the temperature of the hot Al deposition step. However, a lower Al de-gas temperature can lead to defects in subsequent steps; therefore a number of related processes need to be tuned in accordance with changes in Al deposition.

A series of changes to the stack recipe were recommended and implemented, from de-gas to Al reflow, which reduced the number of hillocks by more than half. The results were validated by electrical parametric tests (see figure 5).

tOOl AvAilABility imPrOvement

Other results of the work performed during the fab-wide consulting engagement include:

■■ Greater Availability. The uptime and stability of one PVD tool used to fabricate copper barrier/seed (CuBS) layers was increased by the addition of a new bell jar component. DC bias deterioration was eliminated and RF matching for load and tune positions was stabilized.

■■ Backside Etch Defect Reduction. One Applied Centura tool was experiencing intermittent yield

loss from defects during backside etch. FabVantage consultants identified chamber maintenance practices as the root cause of the defects. They then recommended and helped implement new procedures for electrostatic chuck (ESC) cleaning and inline defect detection.

■■ Side-to-Side Chamber Mismatch Eliminated. The parameters of devices produced on different sides of one Applied Producer CVD tool’s chamber were mismatched. The team determined the tool’s showerhead was one factor; the second factor was differences in the level of radio frequency (RF) power from one side to the other. A faceplate change at the next preventive maintenance cycle was recommended, and the level of RF power applied throughout the chamber was optimized and equalized.

The key to successful semiconductor manufacturing is to achieve and maintain the highest possible yields at the lowest possible cost. As this project demonstrates, well-qualified and experienced consultants such as those in Applied’s FabVantage group, backed by extensive technology resources, can help manufacturers achieve those goals.

Figure 4. Tool hardware and recipe audits of tools in the CoSi loop uncovered several findings that were contributing to poor transistor performance. After optimizing the Co PVD recipe to eliminate transient steps and increase pressure and power, the standard deviation of within-wafer thickness uniformity decreased by almost half (figure 4a) and the standard deviation of within-wafer resistivity declined about 15% (figure 4b). More importantly, resistivity was controlled in a tighter range.

(4a) (4b)

Acknowledgements:Key participants in this project included Laura Bertarelli, Massimo Casella, Marco Crivellari, Francesco Fattibene, Patrick Fernandez, Robert Grimwood, Valeria Lanza and Tony Persico


Figure 5. The Al hillocks seen at left were caused by Al film stress and were impacting yields from a PVD tool (figure 5a). Applied’s FabVantage consultants recommended a number of ways to reduce film stress, reducing hillock formation by more than half (figure 5b).

(5a)

(5b)

Figure 2. An RTP tool’s system controller was optimized toeliminate temperature overshoots during ramp-up (figure 2a). These can cause oxide growth and dopant out-diffusion, and lead to variations in transistor performance across wafers. Also, the beneficial effects of a recipe change toaccommodate higher chamber pressures are shown in figure 2b. The FabVantage team discovered that chamber pressures were causing peak temperature control issues. The new recipe led to more uniform temperatures across heater zones.

(2a)

(2b)



cause of peak temperature control issues, and the recipe was modified to accommodate higher pressures (see figure 2b). Finally, hardware/maintenance practice audits revealed that the tool’s process kit was marginal, and also that preventivemaintenance procedures needed tobe optimized. The hardware issues were addressed and BKM cleaning procedures were implemented.

deFect reductiOn leAds tO Better cmP

A chemical-mechanical planarization (CMP) tool was unableto achieve targeted yields because of scratches generated during a polishing step. These scratches were being generated at more than three times the number that could be tolerated by the customer’stechnology.

The FabVantage team conducted several tool audits to understand the problem and identify solutions. Theydetermined that upstream processes induced particles at the wafer edge that subsequently scratched the wafer during polishing. A multi-faceted solution was recommended and implemented that focused on optimizing slurry delivery, evaluating specific tool components, and conducting upstream preventive maintenance activities in accordance with Applied’s BKMs. The result was a more than 300% reduction in scratches (see figure 3).

Figure 3. Tool audits conducted by the FabVantage team led to a more than 300% reduction in scratches from one CMP tool. The team recommended changes to upstream preventive maintenance procedures in accordance with Applied’s BKMs, and optimized slurry delivery and evaluation of certain tool components.

imPrOved PrOcess stABility

Production and yields from a PVD tool that was trying to run a new recipe were impacted bythe complexity of a cobalt silicide (CoSi) deposition loop, which led towidespread transistor leakage and logic timing failures during wafer probe tests.

The FabVantage consultants determined that failures were dependent on product-type, processintegration of the CoSi step was marginal, and within-wafer leakage patterns were related to the thickness of the cobalt film—the thicker the Co, the worse the leakage.

The team recommended improved inline electrical parametric tests and test layouts as a way to detect failure mechanisms early, as well as the implementation of a very soft sputter (VSS) etch process prior to Co deposition to improve film uniformity (see figure 4). Modifications to pressure and power to improve process stability were suggested, and the Co PVD recipe was optimized for better within-wafer and wafer-to-wafer thickness uniformity.

OPtimiZed Aluminum dePOsitiOn reduces HillOcKs

One PVD tool was experiencing yield loss with specific device-types because high aluminum (Al) hillocks were being produced by the baseline process. Although the customer had

Temperature overshoots during ramp-up caused oxide growth and dopant out-diffusion, and these effects led to the variation in device performance. In response, the customer and the FabVantage team modified the tool’s system controller to optimize it for the temperature ramp-up step (see figure 2a).

Meanwhile, the recipe audit identified chamber pressure as a

NaNochipNaNochip6 7

as MoBile systeMs offeR aDDitional MeMs sensoRs, POwer is A PrimAry cHAllenGe

byDaViD

laMMerS

Rob Lineback, an IC Insights analyst who tracks power ICs as part of the market research firm’sreport on optoelectronics, sensors, and discretes (O-S-D), said much of the attention in the power field has been on mobile systems, principally smartphones. “Battery power management has been talked about for so long. But there is renewed attention on reducing the power consumption of the big computers and switches, partly so we can cut air pollution from the power plants. Power management plays acrossthe whole range of systems, and there is a lot of money there for the semiconductor companies.”

The consolidation in the chip industry, so Darwinian for makers of memory and digital ICs, has not impacted the power IC market as severely. Lineback noted that while

Japan-based companies have cut back on investments in system-on-chip production, “they keep investing in the power area. No one is selling off or consolidating in this area.”

Market research firm Yole Développement predicts 19.5% growthfor the power electronics market—including power ICs, power modules, and discretes such as rectifiers—withtotal revenues for the sector approaching $14 billion. Revenues for power ICs bythemselves will increase from $3 billion in 2013 to about $3.55 billion in 2014. By 2018 power electronics will be a $16 billion sector, the market researcher predicts, with power ICs accounting for $4.23 billion of the total.

In a 2013 study of the super junction (SJ) power IC market, Yole noted that several new players entered the SJ MOSFET market over the last 36 months, including some smaller

Jeremie Bouchaud, senior principal analyst for MEMS and sensors at market research firm IHS, said environmental sensors on the horizon will turn smartphones into “micro gas chromatographs” able to monitor pollen in the air or alcohol on one’s breath. STMicroelectronics foresees each phone having a micro display capability. Apple’s decision to provide a fingerprint MEMS sensor in its latest iPhone will soon be emulated by the Android smartphone camp.

To be sure, we can all look forward to an array of exciting new capabilities built into everything you can imagine−from cars and smartphones to intelligent appliances and wearable technology−based on a range of new sensors and ICs (see figure 1). The behind-the-scenes challenge, however, is to deliver power to those components without exceeding the system’s power budget. That is spurring power IC vendors to develop new device architectures and advanced 200mm manufacturing techniques.

Power Struggle:

Figure 1. Today’s advanced power switching applications are driven mostly by the fast-growing consumer market. While higher frequency and ever higher power-handling capabilities are sought, portability is also a key factor because there is increasing pressure to make these devices smaller and more efficient. In doing so, the device density increases and so does the complexity of manufacturing for this class of semiconductor power device. (Courtesy of Yole Développement.)

As more sensors are added, consumers are keeping one eye on the battery’s charge level. Partly to keep power under control, the iPhone5 includes a dedicated coprocessor to handle the fingerprint processing and other data streams coming from MEMS devices. And with Intel Corporation squarely behind the trend, smartphone and mobile computer users soon may be able to take advantage of wireless charging; for example, drivers may be

able to lay a smartphone down on the car’s center console to charge the battery.

Other developing−and potentially huge−markets for power semiconductors include solar-powered buildings and battery-powered electric vehicles, which depend on efficient high-voltage power-switching ICs. Home appliances and HVAC systems are fertile markets for smarter power electronics (see figure 2).

foundries in China, raising the number of competitors to about 15. “We have seen new business models emerge, and unexpected players entering,”Yole concluded.

For a variety of technical reasons, SJ power ICs are gaining acceptance compared with conventional power MOSFETs, particularly in consumer applications such as phones and tablets. With their high aspect ratio (HAR) trenches, SJ MOSFETs can be much smaller than lateral or planar power MOSFETs, with faster switching speeds due to a lower ON resistance. Though SJ MOSFETs can also be used in relatively high-power applications, the architecture excels in the small power supplies used in mobile systems that must stay within a relatively low operating temperature range. Vendors are reducing the die sizes of SJ offerings, and smaller packages also are coming to the market.

NaNochipNaNochip6 7

as MoBile systeMs offeR aDDitional MeMs sensoRs, POwer is A PrimAry cHAllenGe

byDaViD

laMMerS

Rob Lineback, an IC Insights analyst who tracks power ICs as part of the market research firm’s report on optoelectronics, sensors, and discretes (O-S-D), said much of the attention in the power field has been on mobile systems, principally smartphones. “Battery power management has been talked about for so long. But there is renewed attention on reducing the power consumption of the big computers and switches, partly so we can cut air pollution from the power plants. Power management plays across the whole range of systems, and there is a lot of money there for the semiconductor companies.”

The consolidation in the chip industry, so Darwinian for makers of memory and digital ICs, has not impacted the power IC market as severely. Lineback noted that while

Japan-based companies have cut back on investments in system-on-chip production, “they keep investing in the power area. No one is selling off or consolidating in this area.”

Market research firm Yole Développement predicts 19.5% growth for the power electronics market—including power ICs, power modules, and discretes such as rectifiers—with total revenues for the sector approaching $14 billion. Revenues for power ICs by themselves will increase from $3 billion in 2013 to about $3.55 billion in 2014. By 2018 power electronics will be a $16 billion sector, the market researcher predicts, with power ICs accounting for $4.23 billion of the total.

In a 2013 study of the super junction (SJ) power IC market, Yole noted that several new players entered the SJ MOSFET market over the last 36 months, including some smaller

Jeremie Bouchaud, senior principal analyst for MEMS and sensors at market research firm IHS, said environmental sensors on thehorizon will turn smartphones into“micro gas chromatographs” able tomonitor pollen in the air or alcohol on one’s breath. STMicroelectronics foresees each phone having a micro display capability. Apple’s decision toprovide a fingerprint MEMS sensor in its latest iPhone will soon be emulated by the Android smartphone camp.

To be sure, we can all look forward to an array of exciting new capabilities built into everything you can imagine−from cars and smartphones to intelligent appliances and wearable technology−based on a range of new sensors and ICs (see figure 1). The behind-the-scenes challenge, however, is to deliver power to those components without exceeding the system’s power budget. That is spurring power IC vendors todevelop new device architectures and advanced 200mm manufacturing techniques.

PowerStruggle:

Figure 1. Today’s advanced power switching applications are driven mostly by the fast-growing consumer market. While higher frequency and ever higher power-handling capabilities are sought, portability is also a key factor because there is increasing pressure to make these devices smaller and more efficient. In doing so, the device density increases and so does the complexity of manufacturing for this class of semiconductor power device. (Courtesy of Yole Développement.)

As more sensors are added, consumers are keeping one eye on the battery’s charge level. Partly to keep power under control, the iPhone5 includes a dedicated coprocessor to handle the fingerprint processing and other data streams coming from MEMS devices. And with Intel Corporation squarelybehind the trend, smartphone and mobile computer users soon may be able to take advantage of wireless charging; for example, drivers may be

able to lay a smartphone down on the car’s center console to charge the battery.

Other developing−andpotentially huge−markets for power semiconductors include solar-powered buildings and battery-powered electric vehicles, which depend on efficient high-voltage power-switching ICs. Home appliances and HVAC systems are fertile markets for smarter power electronics (see figure 2).

foundries in China, raising the number of competitors to about 15. “We have seen new business models emerge, and unexpected players entering,” Yole concluded.

For a variety of technical reasons, SJ power ICs are gaining acceptance compared with conventional power MOSFETs, particularly in consumer applications such as phones and tablets. With their high aspect ratio (HAR) trenches, SJ MOSFETs can be much smaller than lateral or planar power MOSFETs, with faster switching speeds due to a lower ON resistance. Though SJ MOSFETs can also be used in relatively high-power applications, the architecture excels in the small power supplies used in mobile systems that must stay within a relatively low operating temperature range. Vendors are reducing the die sizes of SJ offerings, and smaller packages also are coming to the market.

NaNochipNaNochip8 9

Insulated gate bipolar transistors (IGBTs), the higher power switching chips used in industrial electronics, electric vehicles (EVs) and electric utilities, are also undergoing manufacturing developments. IGBTs can gain switching performance by thinning the wafer, and market leader Infineon is moving to thinner 300mm wafers for its high-volume bipolar products. Lineback said “using vertical trench structures and wafer thinning improves the switching speed of the IGBTs. But the problem has been that thinning the wafers creates some other problems, and Infineon is always working on improving its trench stop technology.”

ePitAxiAl GrOwtH And deeP rie

In all types of power devices, current flows from top to bottom

Mike Rosa, 200mm strategic marketing manager for emerging markets at Applied Global Services, said “for the epi steps, everyone wants high throughput; 40 to 100 microns of epi at greater than 4 microns per minute. Once grown, customers need to etch trenches in the blanket film with a DRIE process. The DRIE process must have a high etch rate, as well as the ability to handle slightly tapered structures.”

Subsequent processes include areduced pressure epi to then fill these structures in a void-free, uniformly doped manner. “With Applied’sDRIE etch tool we can do etch rates of 15 microns per minute, with excellent uniformity across the wafer. That leaves us well positioned to apply it topower chips,” Rosa said.

The critical dimension (CD) of the trench opening is also challenging. Rosa said today’s state of the art is approximately 1 to 2 microns and 40 microns deep. “We can shrink it. Using our DRIE tool, we can shrink the trench CD in a gyroscope to .2 microns or 200 nanometers. The fingers become fivetimes more sensitive as compared tothe 1-micron CD structures. With the capabilities of this new etch product, customers can either make the gap smaller and have the same number of fingers, or make the fingers smaller and keep the gap the same, or use fewer fingers,” said Rosa, who earned his doctorate in MEMS technology.

deeP trencH etcHer

Jon Farr, senior etch product manager, said Applied’s deep trench etch product is targeted primarily at power ICs and MEMS. It features decoupled inductive and capacitive reactor sources. Applied’s DPS source is a two-part chamber, with a lower loading chamber and an upper process chamber. The system offers good uniformity, repeatableperformance, low aspect ratio dependence, and long time between cleans (LTBC), Farr said.

Figure 2. The push for more functionality in portable electronics has resulted in more MEMS technology with each generation of consumer device. Some MEMS devices, such as the Inkjet, are mature; others, such as the inertial measurement unit (IMU) combo sensor, are in a high-growth phase. Devices such as pico projectors are still emerging. All these devices compete for mobility power resources. (Source: Applied Materials)

relatively time-consuming, requiring multiple thick-epi growth steps followed by dopant implantation and annealing to activate the dopants. Accurately placing the dopants is challenging.

The deep trench approach, by contrast, involves etching a trench and then backfilling it with highly doped epi films. DRIE, however, requires excellent sidewall profile control, at a high etch rate, with uniformity across the wafer. Deep trench MEMS, such as gyroscopes, can require etching of trenches as deep as 40–50 microns with high precision. Figure 3 shows an example of DRIE for MEMS using Applied’s 200mm etch tool. Deep trench SJ MOSFETs can involve, for example, 60-micron trenches with slightly tapered sidewalls so the trench can be filled without voids (see figure 4).

through epitaxial doped regions. For the increasingly popular SJ devices, the thickness of the doped regions impacts the ON resistance (Ron), which controls the switching speed, but making them too thin affects the necessary Roff. Bringing the heavily doped columns closer together can improve the performance of power ICs.

Applied Materials has efforts underway to improve the epitaxial, deep reactive ion etching (DRIE), and dense aluminum interconnect deposition steps. For SJ MOSFETs created with the deep trench method instead of the multi-step epitaxial deposition and doping approach, DRIE is the critical difference.

Deep trench SJ MOSFETs have certain advantages. The conventional, and still-mainstream approach, which builds up the epitaxial layers one by one, is

“This etch system is aimed at a broad swathe of applications, including power and MEMS. There is interest in making devices with very high aspect ratio (VHAR) submicron trenches from companies makingmany kinds of products−opticaldevices, inkjet heads, even things likeblood filters,” Farr said.

SJ power MOSFETs are challenging, partly because the trenches have a high open area due tothe pitch, often with a 50% open area and a 10:1 aspect ratio. CDs range from 1 to 5 microns. While the aspect ratio of trenches in memory ICs rarely goes beyond 10:1, deep silicon etch steps are at ratios of 10:1 to 100:1.

Customer applications are divided between single-step etch methods and the Bosch process, each having its specific advantages. The single-step process works well for creating the smooth sidewalls required for miniaturized SJ devices, he said.

While another emerging market, through-silicon vias (TSVs) also requires deep trenches, Farr saidTSV trenches are not particularly demanding, and only require low-cost, high-throughput systems. “What we are doing is more difficult. With gyroscopes (MEMS), such a level of precision is required that each device has to be electrically tested. With SJs, there are challenges with the large open area, loading, and CD uniformity.”

Applied’s etcher is a cluster-type tool, capable of plugging in up to four etch chambers. The RF configuration was modernized to improve the across-wafer CD uniformity and provide for higher open areas andimproved across-wafer depth uniformity.

“We changed the way the reactor works, with more digital controls requiring more computing power. Customers can configure the system with metal etch, deep trench reactors, strippers, and so on—all on one platform,” Farr said.

Waiting in the wings of the power IC market are twodeveloping processes, one based on gallium nitride (GaN) and one using silicon carbide (SiC), each bearing the challenges associated with compound substrates and the promise associated with wide band-gap materials. With revenues growing and multiple companies investing in new manufacturing techniques and materials, the power electronics market will be well worth paying close attention to.


Figure 3. Next-generation devices will require a unique combination of fine CD or sub-micron capability and deep trench etch to produce tightly packed devices with aspect ratios approaching or in excess of 100:1. (Source: Applied Materials)

Figure 4. Advanced DRIE solutions for SJ power devices call for exacting control over the sidewall profile, undercut, and selectivity to the oxide and photoresist masks used. (Source: Applied Materials)

Power Struggle

NaNochipNaNochip8 9

Insulated gate bipolar transistors (IGBTs), the higher power switching chips used in industrial electronics, electric vehicles (EVs) and electric utilities, are also undergoing manufacturing developments. IGBTs can gain switching performanceby thinning the wafer, and market leader Infineon is moving to thinner 300mm wafers for its high-volume bipolar products. Lineback said “using vertical trench structures and wafer thinning improves the switching speed of the IGBTs. But the problem has been that thinning the wafers creates some other problems, and Infineon is always working on improving its trench stop technology.”

ePitAxiAl GrOwtH And deeP rie

In all types of power devices, current flows from top to bottom

Mike Rosa, 200mm strategic marketing manager for emerging markets at Applied Global Services, said “for the epi steps, everyone wants high throughput; 40 to 100 microns of epi at greater than 4 microns per minute. Once grown, customers need to etch trenches in the blanket film with a DRIE process. The DRIE process must have a high etch rate, as well as the ability to handle slightly tapered structures.”

Subsequent processes include a reduced pressure epi to then fill these structures in a void-free, uniformly doped manner. “With Applied’s DRIE etch tool we can do etch rates of 15 microns per minute, with excellent uniformity across the wafer. That leaves us well positioned to apply it to power chips,” Rosa said.

The critical dimension (CD) of the trench opening is also challenging. Rosa said today’s state of the art is approximately 1 to 2 microns and 40 microns deep. “We can shrink it. Using our DRIE tool, we can shrink the trench CD in a gyroscope to .2 microns or 200 nanometers. The fingers become five times more sensitive as compared to the 1-micron CD structures. With the capabilities of this new etch product, customers can either make the gap smaller and have the same number of fingers, or make the fingers smaller and keep the gap the same, or use fewer fingers,” said Rosa, who earned his doctorate in MEMS technology.

deeP trencH etcHer

Jon Farr, senior etch product manager, said Applied’s deep trench etch product is targeted primarily at power ICs and MEMS. It features decoupled inductive and capacitive reactor sources. Applied’s DPS source is a two-part chamber, with a lower loading chamber and an upper process chamber. The system offers good uniformity, repeatable performance, low aspect ratio dependence, and long time between cleans (LTBC), Farr said.

Figure 2. The push for more functionality in portable electronics has resulted in more MEMS technology with each generation of consumer device. Some MEMS devices, such as the Inkjet, are mature; others, such as the inertial measurement unit (IMU) combo sensor, are in a high-growth phase. Devices such as pico projectors are still emerging. All these devices compete for mobility power resources. (Source: Applied Materials)

relatively time-consuming, requiringmultiple thick-epi growth steps followed by dopant implantation and annealing to activate the dopants. Accurately placing the dopants is challenging.

The deep trench approach, bycontrast, involves etching a trench and then backfilling it with highly doped epi films. DRIE, however, requires excellent sidewall profile control, at a high etch rate, with uniformity across the wafer. Deep trench MEMS, such as gyroscopes, can require etching of trenches as deep as 40–50 microns with high precision. Figure 3 shows an example of DRIE for MEMS using Applied’s200mm etch tool. Deep trench SJ MOSFETs can involve, for example, 60-micron trenches with slightlytapered sidewalls so the trench can be filled without voids (see figure 4).

through epitaxial doped regions. For the increasingly popular SJ devices, the thickness of the doped regions impacts the ON resistance (Ron), which controls the switching speed, but making them too thin affects the necessary Roff. Bringing the heavily doped columns closer together can improve the performance of power ICs.

Applied Materials has efforts underway to improve the epitaxial, deep reactive ion etching (DRIE), and dense aluminum interconnect deposition steps. For SJ MOSFETscreated with the deep trench method instead of the multi-step epitaxial deposition and doping approach, DRIE is the critical difference.

Deep trench SJ MOSFETshave certain advantages. The conventional, and still-mainstream approach, which builds up the epitaxial layers one by one, is

“This etch system is aimed at a broad swathe of applications, including power and MEMS. There is interest in making devices with very high aspect ratio (VHAR) submicron trenches from companies making many kinds of products−optical devices, inkjet heads, even things like blood filters,” Farr said.

SJ power MOSFETs are challenging, partly because the trenches have a high open area due to the pitch, often with a 50% open area and a 10:1 aspect ratio. CDs range from 1 to 5 microns. While the aspect ratio of trenches in memory ICs rarely goes beyond 10:1, deep silicon etch steps are at ratios of 10:1 to 100:1.

Customer applications are divided between single-step etch methods and the Bosch process, each having its specific advantages. The single-step process works well for creating the smooth sidewalls required for miniaturized SJ devices, he said.

While another emerging market, through-silicon vias (TSVs) also requires deep trenches, Farr said TSV trenches are not particularly demanding, and only require low-cost, high-throughput systems. “What we are doing is more difficult. With gyroscopes (MEMS), such a level of precision is required that each device has to be electrically tested. With SJs, there are challenges with the large open area, loading, and CD uniformity.”

Applied’s etcher is a cluster-type tool, capable of plugging in up to four etch chambers. The RF configuration was modernized to improve the across-wafer CD uniformity and provide for higher open areas and improved across-wafer depth uniformity.

“We changed the way the reactor works, with more digital controls requiring more computing power. Customers can configure the system with metal etch, deep trench reactors, strippers, and so on—all on one platform,” Farr said.

Waiting in the wings of the power IC market are two developing processes, one based on gallium nitride (GaN) and one using silicon carbide (SiC), each bearing the challenges associated with compound substrates and the promise associated with wide band-gap materials. With revenues growing and multiple companies investing in new manufacturing techniques and materials, the power electronics market will be well worth paying close attention to.


Figure 3. Next-generation devices will require a unique combination of fine CD or sub-micron capability and deep trench etch to produce tightly packed devices with aspect ratios approaching or in excess of 100:1. (Source: Applied Materials)

Figure 4. Advanced DRIE solutions for SJ power devices call for exacting control over the sidewall profile, undercut, and selectivity to the oxide and photoresist masks used. (Source: Applied Materials)

Power Struggle

NaNochipNaNochip10 11

byaDele harS

STMicroelectronics: on ToP ofKey mArKets

How do you stay on top when times are tough? For Europe’s biggest chipmaker, STMicroelectronics, it takes a renewed focus on the five markets where the company has the products, technology and ambition to lead.

ST already holds top-3 positions in some of those key markets—and plans to win more. Orio Bellezza, executive vice president and general manager of Front-End Manufacturing& Technology R&D for ST’s Sense & Power and Automotive Product (SP&A) segment (and member of ST’s Strategic Committee) explains how. “You need scale,” he said. “You need to be on top of large, growing markets, with leading customers, and driving innovativeapplications. The name of the game is to be fast and first.” A key component in the strategy, he says, is “relentless commitment to process technology.”

ST already has the leading customers: Apple, Bosch, Cisco, Continental, HP, Samsung, Sony and Western Digital, among others. But the company also sells more and more to diversified markets and smaller customers, especially through its distribution channel.

The company has six front-end manufacturing sites serving two main product blocks: Sense & Power and Automotive (SP&A), located primarily in Italy (around Milan and Catania) and Singapore, and Embedded ProcessingSolutions (EPS), located mainly in and around Grenoble and Rousset. ST also manages its own back end and packaging, primarily at sites in China, Malaysia, Malta, Morocco, the Philippines and Singapore.

The main technologies ST will focus on are: MEMS and sensors; smart power; set-top box/home gateway and ASICs; microcontrollers; and automotive.

clusters OF cOmPetencies

The manufacturing sites are organized into “clusters of competencies” comprising design, technology and manufacturing, explained Bellezza. Each fab has a

technical mission, but there is also flexibility across sites and with foundry partners to ensure appropriate support for customers as needed.

Because ST offers thousands of products, each fab runs anywhere from one- to three-dozen processes, each with multiple variations and each variation requiring multiple mask sets. Price pressure on high-volume applications requires optimal scheduling across the manufacturing sites.

While this kind of scheduling is complex to manage, “ST has a very efficient planning system at a central level to optimize asset utilization and deliver the service and responsivenessexpected by our customers,” said Bellezza. “At a local level, of course the MES and automation systems playimportant roles in fab managementand we work on their continuous evolution and adaptation in the fab. In 150 and 200mm our focus is not so much on the transportation [AMHS] but more on WIP manage-ment, advanced process control anddata analysis.”

Manufacturing is tightly coupled with R&D; together they account for almost a quarter of the company’sworkforce. “It’s very important for us tohave manufacturing and R&D peopleworking side-by-side, developing technology and translating it tovolume,” explained Bellezza. “We often have R&D and manufacturing in the same fab, which speeds development.”

In fact, Bellezza attributes ST’sleadership in MEMS today to the strong contribution and ability of the teams around Milan (and in Malta’sback end) to manage a very efficient coordination among design, technology and manufacturing, enabling fast time to market and volume. It’s an excellent example of how the flow of information toward manufacturing, the learning

Orio Bellezza, executive vice president and general manager of Front-EndManufacturing & Technology R&D for ST’s Sense & Power and AutomotiveProducts segment and member of ST’s Strategic Committee

STMicrosystems operations in Agrate, Italy.


byaDele harS

STMicroelectronics:on ToP ofKey mArKets

How do you stay on top when times are tough? For Europe’s biggest chipmaker, STMicroelectronics, it takes a renewed focus on the five markets where the company has the products, technology and ambition to lead.

ST already holds top-3 positions in some of those key markets—and plans to win more. Orio Bellezza, executive vice president and general manager of Front-End Manufacturing & Technology R&D for ST’s Sense & Power and Automotive Product (SP&A) segment (and member of ST’s Strategic Committee) explains how. “You need scale,” he said. “You need to be on top of large, growing markets, with leading customers, and driving innovative applications. The name of the game is to be fast and first.” A key component in the strategy, he says, is “relentless commitment to process technology.”

ST already has the leading customers: Apple, Bosch, Cisco, Continental, HP, Samsung, Sony and Western Digital, among others. But the company also sells more and more to diversified markets and smaller customers, especially through its distribution channel.

The company has six front-end manufacturing sites serving two main product blocks: Sense & Power and Automotive (SP&A), located primarily in Italy (around Milan and Catania) and Singapore, and Embedded Processing Solutions (EPS), located mainly in and around Grenoble and Rousset. ST also manages its own back end and packaging, primarily at sites in China, Malaysia, Malta, Morocco, the Philippines and Singapore.

The main technologies ST will focus on are: MEMS and sensors; smart power; set-top box/home gateway and ASICs; microcontrollers; and automotive.

clusters OF cOmPetencies

The manufacturing sites are organized into “clusters of competencies” comprising design, technology and manufacturing, explained Bellezza. Each fab has a

technical mission, but there is also flexibility across sites and with foundry partners to ensure appropriate support for customers as needed.

Because ST offers thousands of products, each fab runs anywhere from one- to three-dozen processes, each with multiple variations and each variation requiring multiple mask sets. Price pressure on high-volume applications requires optimal scheduling across the manufacturing sites.

While this kind of scheduling is complex to manage, “ST has a very efficient planning system at a central level to optimize asset utilization and deliver the service and responsiveness expected by our customers,” said Bellezza. “At a local level, of course the MES and automation systems play important roles in fab management and we work on their continuous evolution and adaptation in the fab. In 150 and 200mm our focus is not so much on the transportation [AMHS] but more on WIP manage-ment, advanced process control and data analysis.”

Manufacturing is tightly coupled with R&D; together they account for almost a quarter of the company’s workforce. “It’s very important for us to have manufacturing and R&D people working side-by-side, developing technology and translating it to volume,” explained Bellezza. “We often have R&D and manufacturing in the same fab, which speeds development.”

In fact, Bellezza attributes ST’s leadership in MEMS today to the strong contribution and ability of the teams around Milan (and in Malta’s back end) to manage a very efficient coordination among design, technology and manufacturing, enabling fast time to market and volume. It’s an excellent example of how the flow of information toward manufacturing, the learning

Orio Bellezza, executive vice president and general manager of Front-End Manufacturing & Technology R&D for ST’s Sense & Power and Automotive Products segment and member of ST’s Strategic Committee

STMicrosystems operations in Agrate, Italy.


and the anticipation of problems in the development phase are naturally addressed with time-to-volume in mind. And with good R&D and coordination comes higher yields.

“There is a lot of innovation here,” said Bellezza. Teamwork and meetings are part of the daily job. Process control, stored program control, equipment management—all are well mastered when ownership is transferred from the R&D team to the manufacturing engineers.

ST also insists on strong cooperation with the equipment suppliers, he noted, not just for 300mm work but for analog, MEMS and even discrete products. Things like wafer thinning and doping, and specialized interconnection schemes, as well as new materials integration, require specific tools and strong support from suppliers.

The tight coupling of R&D with manufacturing is another reason that a major move to outsourcing is not envisioned for the SP&A segment. “We have a broad portfolio, we’re building on it, and we need to be very fast,” said Bellezza. Take MEMS for example, where ST is the world leader. ST was the first company to move to 200mm MEMS R&D and production. The company’s MEMS sales exceeded $1 billion, according to research firm Yole Développement, while its market share grew from 43% in 2011 to 48% today. While there

might be some outsourcing of very high volume motion sensors, there are a lot of other flavors of MEMS and sensors in the pipeline.

With the “humanization” of user interfaces, ST is anticipating a radical expansion in smarter technologies for capturing gesture, voice and touch for markets such as health and wellness, wearable electronics, and applications related to the Internet of Things. Targeting strong growth for MEMS, the company is looking beyond its successful lines of accelerometers and gyroscopes to actuation (for example, mirrors for micro-projectors), acoustics and environmental sensors.

However, the company does take different approaches to R&D for CMOS logic vs. the analog and MEMS side of things. For advanced CMOS, ST has pioneered FD-SOI, which is in production now at 28nm, with 14nm

to follow next year. As the investments required are immense, “competencies clustering” is shared across alliances with IBM and GlobalFoundries. Under the Nano2017 public/private investment initiative, enhanced R&D efforts will support customer demand by increasing the capacity of ST’s 300mm fab. It’s expected to grow from 3,500 wafers per week to 5,700 wafers per week by 2017, and ultimately reach 7,000 wafers per week.

The €3.5 billion Nano2017 initiative is so important that the French government has announced it will contribute €600 million to it. The French government contends that Nano2017 will make ST Grenoble one of the three pillars (along with GlobalFoundries Dresden and NXP Eindhoven) of the European Horizon2020 program, which begins in January 2014.

On the analog side (“south of the Alps”), ST is also investing in the next technology nodes for its fabs in Catania, which do volume production of smart power and other BCD-based products and development for advanced discrete products; and Agrate, which does advanced BCD, and smart power devices and MEMS R&D along with volume manufacturing.

reducinG cOsts

ST operates 150mm, 200mm and 300mm fabs, and like everyone else in the industry, is working to

reduce costs. Is moving to larger wafer sizes the solution? Bellezza believes there are essentially three approaches to reducing costs: design and innovation, wafer diameter and optical shrink.

Optical shrink is slowing in CMOS, and while going to larger wafer diameters can be helpful, especially on the digital side, it is not a panacea. Bellezza cited issues in moving to 450mm with step-and-scan lithography tools. Basically, the bigger the wafer, the more step-and-scan steps you need to do. “Those machines have not yet made the leap—in fact, to expose a 450mm wafer takes two to three times longer [you have to stay on the wafer longer to get all dice exposed], so there’s no gain in those expensiveprocess steps. The economics don’tyet make sense,” he said.

On the analog side, ST is moving two of its 150mm lines to200mm, but Bellezza does not see MEMS products in his SP&A segment moving from 200mm to300mm anytime soon. “There’sstill a huge market for 200mm,” he said. “Of course you always need to continuously reduce process complexity and look for savings in material costs and energy consumption.”

But in a business driven bythe steady reduction of price-per-function, where do you focus your cost reduction efforts? “You have to bet on innovation,” said Bellezza. “Collaboration and support of keysuppliers is very important. For example, if you’re moving to cheaper materials, you need to address the processes and equipment, find new recipes, and improve equipmentproductivity and efficiency.”

diFFerentiAtiOn

As an IDM, “ST’s objective is to offer something differentiating,”noted Bellezza. As for analog, “our

ability to compete is strongly related to our technology capabilities. So we keep developing internally those manufacturing technologies that enable us to differentiate our portfolio. Of course, we don’t sell technology; we sell products.”

In recent months, ST has announced a host of new technologies that are enabling new products. But if there’s one thing that gets Bellezza excited, it’sclearly the prospects for automotiveapplications. Historically northernItaly, including greater Milan and Turin, which are among Europe’swealthiest cities, is an important area for the automotive industry. It is home to Fiat, Pirelli and Alfa Romeo, the prestigious Milan and Turin Polytechnic Universities, and the famous Monza racetrack.

ST is in the top three of the world’s biggest suppliers to the automotive market. It is first in smart power (with 25% market share), ASICs, active safety and audio power amps, and second in infotainment. “Our relentless efforts to improve safety, reduce fuel consumption, expand entertainmentand infotainment options, and enable more efficient hybrid and electric vehicles, make the car our most exciting lab for electronics,” he said.

As is often noted, the percentage of electronics in automotive BOMs is increasing rapidly. “ST has a unique portfolio of technologies and products that cover the full spectrum of opportunities, in most cases with a leadership position,” he continued. Bellezza cited advanced BCD smart power for power train control, fuel consumption control, car radioand several other applications; embedded non-volatile memory (NVM) for microcontrollers; advanced CMOS for image sensing and processing; and MEMS motion and environmental sensors for active safety and comfort. ST’s new

FD-SOI technology will be in a broad range of applications for higher performance with lower power consumption. “All of this is before you even start talking about electric vehicles!” he exclaimed.

“I think ST definitely has all the ingredients to enhance our leadership in this continuouslygrowing and evolving sector, including full ownership and ongoing investments in process technology—especially at ourCrolles and Agrate technology centers—and full control of the supply chain through internal manufacturing,“ said Bellezza.

With new technologies coming to the fore, opportunities abound. While typically ST works interactively with customers toprovide options, performance andenabling products, sometimes in areas like analog and MEMS “we find we can offer things our customers couldn’t even have imagined!” concluded Bellezza.

Adele Hars is a writer and director of High Tech International, based in Paris, France.

Special thanks to Laura Bertarelli for her support of this article.

STMicroelectronics:

on ToP of Key MarKetS

Power and other BDC products are produced at ST’s Catania facility.


and the anticipation of problems in the development phase are naturally addressed with time-to-volumein mind. And with good R&D and coordination comes higher yields.

“There is a lot of innovation here,” said Bellezza. Teamwork and meetings are part of the daily job. Process control, stored programcontrol, equipment management—all are well mastered when ownership is transferred from the R&D team to the manufacturing engineers.

ST also insists on strong cooperation with the equipmentsuppliers, he noted, not just for 300mm work but for analog, MEMS and even discrete products. Things like wafer thinning and doping, and specialized interconnection schemes, as well as new materials integration, require specific tools and strong support from suppliers.

The tight coupling of R&D with manufacturing is another reason that a major move to outsourcing is not envisioned for the SP&A segment. “We have a broad portfolio, we’re building on it, and we need to be very fast,” said Bellezza. Take MEMS for example, where ST is the world leader. ST was the first company to move to 200mm MEMS R&D and production. The company’s MEMSsales exceeded $1 billion, according toresearch firm Yole Développement, while its market share grew from 43% in 2011 to 48% today. While there

might be some outsourcing of very high volume motion sensors, there are a lot of other flavors of MEMS and sensors in the pipeline.

With the “humanization” of user interfaces, ST is anticipating a radical expansion in smarter technologies for capturing gesture, voice and touch for markets such as health and wellness, wearable electronics, and applications related to the Internet of Things. Targeting strong growth for MEMS, the company is looking beyond its successful lines of accelerometers and gyroscopes to actuation (for example, mirrors for micro-projectors), acoustics and environmental sensors.

However, the company does take different approaches to R&D for CMOS logic vs. the analog and MEMS side of things. For advanced CMOS, ST has pioneered FD-SOI, which is in production now at 28nm, with 14nm

to follow next year. As the investments required are immense, “competencies clustering” is shared across alliances with IBM and GlobalFoundries. Under the Nano2017 public/privateinvestment initiative, enhanced R&D efforts will support customer demand by increasing the capacity of ST’s300mm fab. It’s expected to grow from 3,500 wafers per week to 5,700 wafers per week by 2017, and ultimately reach 7,000 wafers per week.

The €3.5 billion Nano2017 initiative is so important that the French government has announced it will contribute €600 million to it. The French government contends that Nano2017 will make ST Grenoble one of the three pillars (along with GlobalFoundries Dresden and NXP Eindhoven) of the European Horizon2020 program, which begins in January 2014.

On the analog side (“south of the Alps”), ST is also investing in the next technology nodes for its fabs in Catania, which do volume production of smart power and other BCD-based products and developmentfor advanced discrete products; andAgrate, which does advanced BCD, and smart power devices and MEMS R&D along with volume manufacturing.

reducinG cOsts

ST operates 150mm, 200mm and 300mm fabs, and like everyone else in the industry, is working to

reduce costs. Is moving to larger wafer sizes the solution? Bellezza believes there are essentially three approaches to reducing costs: design and innovation, wafer diameter and optical shrink.

Optical shrink is slowing in CMOS, and while going to larger wafer diameters can be helpful, especially on the digital side, it is not a panacea. Bellezza cited issues in moving to 450mm with step-and-scan lithography tools. Basically, the bigger the wafer, the more step-and-scan steps you need to do. “Those machines have not yet made the leap—in fact, to expose a 450mm wafer takes two to three times longer [you have to stay on the wafer longer to get all dice exposed], so there’s no gain in those expensive process steps. The economics don’t yet make sense,” he said.

On the analog side, ST is moving two of its 150mm lines to 200mm, but Bellezza does not see MEMS products in his SP&A segment moving from 200mm to 300mm anytime soon. “There’s still a huge market for 200mm,” he said. “Of course you always need to continuously reduce process complexity and look for savings in material costs and energy consumption.”

But in a business driven by the steady reduction of price-per-function, where do you focus your cost reduction efforts? “You have to bet on innovation,” said Bellezza. “Collaboration and support of key suppliers is very important. For example, if you’re moving to cheaper materials, you need to address the processes and equipment, find new recipes, and improve equipment productivity and efficiency.”

diFFerentiAtiOn

As an IDM, “ST’s objective is to offer something differentiating,” noted Bellezza. As for analog, “our

ability to compete is strongly related to our technology capabilities. So we keep developing internally those manufacturing technologies that enable us to differentiate our portfolio. Of course, we don’t sell technology; we sell products.”

In recent months, ST has announced a host of new technologies that are enabling new products. But if there’s one thing that gets Bellezza excited, it’s clearly the prospects for automotive applications. Historically northern Italy, including greater Milan and Turin, which are among Europe’s wealthiest cities, is an important area for the automotive industry. It is home to Fiat, Pirelli and Alfa Romeo, the prestigious Milan and Turin Polytechnic Universities, and the famous Monza racetrack.

ST is in the top three of the world’s biggest suppliers to the automotive market. It is first in smart power (with 25% market share), ASICs, active safety and audio power amps, and second in infotainment. “Our relentless efforts to improve safety, reduce fuel consumption, expand entertainment and infotainment options, and enable more efficient hybrid and electric vehicles, make the car our most exciting lab for electronics,” he said.

As is often noted, the percentage of electronics in automotive BOMs is increasing rapidly. “ST has a unique portfolio of technologies and products that cover the full spectrum of opportunities, in most cases with a leadership position,” he continued. Bellezza cited advanced BCD smart power for power train control, fuel consumption control, car radio and several other applications; embedded non-volatile memory (NVM) for microcontrollers; advanced CMOS for image sensing and processing; and MEMS motion and environmental sensors for active safety and comfort. ST’s new

FD-SOI technology will be in a broad range of applications for higher performance with lower power consumption. “All of this is before you even start talking about electric vehicles!” he exclaimed.

“I think ST definitely has all the ingredients to enhance our leadership in this continuously growing and evolving sector, including full ownership and ongoing investments in process technology—especially at our Crolles and Agrate technology centers—and full control of the supply chain through internal manufacturing,“ said Bellezza.

With new technologies coming to the fore, opportunities abound. While typically ST works interactively with customers to provide options, performance and enabling products, sometimes in areas like analog and MEMS “we find we can offer things our customers couldn’t even have imagined!” concluded Bellezza.

Adele Hars is a writer and director of High Tech International, based in Paris, France.

Special thanks to Laura Bertarelli for her support of this article.

STMicroelectronics:

on ToP of Key MarKetS

Power and other BDC products are produced at ST’s Catania facility.


byJeFFrey

DietZ anD Cheryl

KnePFler

Legacy 200mm tools are workhorses. Their reliability, economy andperformance make them attractive to manufacturers who produce analog, image sensor, MEMS and power products and for whom scaling andmigration to larger wafer sizes are not currently high priorities.

Figure 1. Applied’s new controller for legacy 200mm tools makes it possible for customers to develop new materials and processes. It provides fast data-collection capabilities for advanced FDC, high connectivity for remote monitoring/control and scalability, and uses a modern operating system and components to ensure easy parts replacement.

However, there are concerns with these older tools regarding continuing productivity, availability and uptime—critical requirements for cost-effective fabrication.

Among these concerns are questions about the continued availability of parts and whether the tools can accommodate modern advanced process control (APC) to enable fault detection and classification (FDC), as well as run-to-run and statistical process control technologies. Applied Materials’ new system controller upgrade for its 200mm tools addresses these concerns by replacing the performance-limiting electronics in the original system controller, which is fast becoming obsolete, with a new version (see figure 1). The upgraded controller offers:

■■ Easy connectivity of legacy tools with modern APC software for higher yields and lower cost production

■■ Much faster and more robust data collection, enabling the use of FDC analysis tools to help optimize device performance and yield

■■ Greatly improved system data management, storage and protection

■■ Full backward compatibility with each tool’s existing application software version

■■ Process- and recipe transparency with the same look and feel for operators and technicians

■■ Readily available component supplies for future repairs and upgrades

Applied’s new controller includes an advanced single-boardcomputer (SBC) with a 2.6 GHz Intel Core CPU and Windows 7 operating system. It is fully and easily compatible with contemporary data communications architectures and technologies, making remotemonitoring/control and high-speed host communications possible. New features not available in the legacy design include 4 Ethernet ports for advanced HSMS, with additional data access from 6 USB 2.0 connections, and 16 additional serial ports.

minimiZed reQuAliFicAtiOns

Significant hardware changes within a fab’s qualified production flow can increase manufacturing risk and change control costs by

requiring process or product requalification. Applied’s new controller is specifically designed to help semiconductor manufacturers minimize the need for tool and process requalification.

The new SBC is designed to be fully backward-compatible with the existing version of software on any tool, as well as process-transparent with existing recipes. Using a proprietary Applied software interpreter layer, the SBC links a user’s specific version of legacy application software to the modern electronic architecture, enabling the upgraded system to provide consistent control functionality. Recipes are executed in exactly the same way as before. Operators have a familiar user experience with the same system interface (see figure 1).

To achieve this, Applied conducted extensive in-house testing of the controller upgrade and followed that by collaborating with chip manufacturers for production-validation tests.

PerFOrmAnce vAlidAted in PrOductiOn tests

Maintaining the viability of 200mm fabs cost-effectively for another 10-15 years is critical to many customers who believe that supporting an aging installed base requires close cooperation with their equipment manufacturers.

Working together at one customer’s fab, the Applied/customer team needed only a single day to swap the controller hardware and restart one of the customer’s Applied Endura tools. This work included a complete hard drive backup, which captured tool settings and performance set points. No recalibration was required to achieve the same performance in the tool’s material-handling functions, a result similar to a standard tool recovery or restart procedure.

The process transparency of the upgraded Endura tool was evaluated and verified in production during more than three months and over 30,000 wafers. Regular film properties tests of the up-graded tool and, ultimately, end-of-line output were compared with other systems on the line. The electrical tests evaluated four metal layers on five different tools comparing contact resistance, intermetal leakage, sheet resistance and via resistance. The execution of recipes on the tool equipped with the new controller matched that of like tools that still use the original controller, with no need to alter any recipes.

eXTenDS LIfe of 200mm TooLS

new ConTroLLer


byJeFFrey

DietZ anD Cheryl

KnePFler

Legacy 200mm tools are workhorses. Their reliability, economy and performance make them attractive to manufacturers who produce analog, image sensor, MEMS and power products and for whom scaling and migration to larger wafer sizes are not currently high priorities.

Figure 1. Applied’s new controller for legacy 200mm tools makes it possible for customers to develop new materials and processes. It provides fast data-collection capabilities for advanced FDC, high connectivity for remote monitoring/control and scalability, and uses a modern operating system and components to ensure easy parts replacement.

However, there are concerns with these older tools regarding continuing productivity, availability and uptime—critical requirements for cost-effective fabrication.

Among these concerns are questions about the continued availability of parts and whether the tools can accommodate modern advanced process control (APC) to enable fault detection and classification (FDC), as well as run-to-run and statistical process control technologies. Applied Materials’ new system controller upgrade for its 200mm tools addresses these concerns by replacing the performance-limiting electronics in the original system controller, which is fast becoming obsolete, with a new version (see figure 1). The upgraded controller offers:

■■ Easy connectivity of legacy tools with modern APC software for higher yields and lower cost production

■■ Much faster and more robust data collection, enabling the use of FDC analysis tools to help optimize device performance and yield

■■ Greatly improved system data management, storage and protection

■■ Full backward compatibility with each tool’s existing application software version

■■ Process- and recipe transparency with the same look and feel for operators and technicians

■■ Readily available component supplies for future repairs and upgrades

Applied’s new controller includes an advanced single-board computer (SBC) with a 2.6 GHz Intel Core CPU and Windows 7 operating system. It is fully and easily compatible with contemporary data communications architectures and technologies, making remote monitoring/control and high-speed host communications possible. New features not available in the legacy design include 4 Ethernet ports for advanced HSMS, with additional data access from 6 USB 2.0 connections, and 16 additional serial ports.

minimiZed reQuAliFicAtiOns

Significant hardware changes within a fab’s qualified production flow can increase manufacturing risk and change control costs by

requiring process or product requalification. Applied’s new controller is specifically designed to help semiconductor manufacturers minimize the need for tool and process requalification.

The new SBC is designed to be fully backward-compatible with the existing version of software on any tool, as well as process-transparent with existing recipes. Using a proprietary Applied software interpreter layer, the SBC links a user’s specific version of legacy application software to the modern electronic architecture, enabling the upgraded system to provide consistent control functionality. Recipes are executed in exactly the same way as before. Operators have a familiar user experience with the same system interface (see figure 1).

To achieve this, Applied conducted extensive in-house testing of the controller upgrade and followed that by collaborating with chip manufacturers for production-validation tests.

PerFOrmAnce vAlidAted in PrOductiOn tests

Maintaining the viability of 200mm fabs cost-effectively for another 10-15 years is critical to many customers who believe that supporting an aging installed base requires close cooperation with their equipment manufacturers.

Working together at one customer’s fab, the Applied/customer team needed only a single day to swap the controller hardware and restart one of the customer’s Applied Endura tools. This work included a complete hard drive backup, which captured tool settings and performance set points. No recalibration was required to achieve the same performance in the tool’s material-handling functions, a result similar to a standard tool recovery or restart procedure.

The process transparency of the upgraded Endura tool was evaluated and verified in production during more than three months and over 30,000 wafers. Regular film properties tests of the up-graded tool and, ultimately, end-of-line output were compared with other systems on the line. The electrical tests evaluated four metal layers on five different tools comparing contact resistance, intermetal leakage, sheet resistance and via resistance. The execution of recipes on the tool equipped with the new controller matched that of like tools that still use the original controller, with no need to alter any recipes.

eXTenDS LIfeof 200mm TooLS

new ConTroLLer



new cOntrOller

As file load on the legacy HDD increases, throughput drops. With the new controller this performance loss does not occur; throughput is optimized to full system entitlement. The increase in system throughput depends on many variables, including product line, configuration, recipe time, and system maintenance practices. The tests at the customer site showed increases between 1.0% and 2.3%, depending on the application.

Stable high-quality data and higher data transfer rates also enable customers to build viable FDC models that more effectively identify yield excursions, to initiate root cause analyses, and to provide feedback to APC systems to improve yield.

To be most effective in capturing short-duration events of interest, these FDC models require data sampling rates of 10Hz or greater and at least 100 SVIDs (status variable identifier data).

Until now FDC has had limited efficacy with legacy 200mm tools because the data sampling rate was too low. The priority had been placed on the stability of the controller interface with factory automation software, rather than on data collection.

Now, however, the controller upgrade supports up to 10Hz data sampling and for the first time enables the use of viable FDC models with these tools. It also allows the use of sophisticated factory automation software such as Applied’s E3 environment.

PusHBAcK On OBsOlescence

The original design of the SBC used in Applied’s Endura and Centura tools is more than 20 years old and is based on the 30 MHz Motorola 68000-type processor. As time marches on for legacy tools, about 3% of parts become obsolete each year. Most of those are electrical parts. Manufacturers began discontinuing production of the SBC’s key components in 2007; the remaining stock will soon be depleted. Virtually all of the SBC’s building blocks are impacted, including the CPU, memory/memory controllers, PLDs, FGPAs, and I/O controllers.

In addition to the obsolescence problem, many of the critical components of the legacy controller for Applied’s Endura and Centura tools have design limitations. These present a major barrier to the use of modern monitoring and control techniques that are proven to increase yields and reduce costs.

Extending the life of mature equipment is a very attractive way to minimize capital expenditures. Applied’s new controller for 200mm tools offers customers the opportunity to do just that.

The new controller greatly improves Centura and Endura performance and uses new, readily available components. It offers a low risk, plug-and-play, process-transparent system enhancement on a modern platform with the processing power to add new applications or modules, and to enable effective fault detection and fab automation. By upgrading to the new controller, customers can bring their tried-and-true 200mm production tools into the modern age.


design already includes Ethernet HSMS, eliminating the need for this additional hardware.

Figure 4 shows the results of fab-host communications tests where the new controller matched the performance of the HSMS-upgraded communication system on the customer tool. Implementation was accomplished by simply connecting to the fab host to one of the four standard Ethernet ports, with no other modification or optimization required.

Better dAtA, Better results

The new controller manages interaction within the system much faster and more efficiently than the original controller, eliminatingbottlenecks that negatively impact throughput. Internal testing demonstrated an Endura throughput increase of as much as 6% from the optimized interaction between the hard disk drive (HDD) and the CPU (see figure 5).

Figure 3. Electrical performance of the new controller (in blue) was in line with five tools running the original hardware. Contact resistance, sheet resistance, via resistance and leakage were comparable for all metal levels of the device.

Figure 4. Communications rate matched performance of HSMS-enabled original controller.

Figure 5. Internal test data demonstrating the impact file volume has on the performance of legacy systems. With the original controller, as file load on the HDD increases throughput drops. With the new controller, this performance loss does not occur; throughput is optimized to full system entitlement.

Figure 2 provides film control-chart comparison data demonstrat-ing recipe transparency, with excellent repeatability of performance on the test tool before and after the installation of the new controller.

The process transparency was assessed by processing thou-sands of production wafers and measuring more than 15 electrical structures covering all metal layers, and sampling the contact, via and sheet resistance as well as wire and intermetal leakage. Figure 3

Figure 2. Thickness and resistance performance results for three film types and four chambers demonstrate transparency between the original and new controllers.

shows a subset of the electrical results, with excellent agreement between the tool running with the new controller and five additional tools running concurrent production on the same device.

The serial communications rate for the original controller is up to 19.2 kHz. A small subset of the installed base, including our beta site, has been upgraded with additional hardware to enable HSMS, which delivers up to 100MHz. The new controller upgrade



new cOntrOller

As file load on the legacy HDD increases, throughput drops. With the new controller this performance loss does not occur; throughput is optimized to full system entitlement. The increase in system throughput depends on many variables, including product line, configuration, recipe time, and system maintenance practices. The tests at the customer site showed increases between 1.0% and 2.3%, depending on the application.

Stable high-quality data and higher data transfer rates also enable customers to build viable FDC models that more effectively identify yield excursions, to initiate root cause analyses, and to provide feedback to APC systems to improve yield.

To be most effective in capturing short-duration events of interest, these FDC models require data sampling rates of 10Hz or greater and at least 100 SVIDs (status variable identifier data).

Until now FDC has had limited efficacy with legacy 200mm tools because the data sampling rate was too low. The priority had been placed on the stability of the controller interface with factory automation software, rather than on data collection.

Now, however, the controller upgrade supports up to 10Hz data sampling and for the first time enables the use of viable FDC models with these tools. It also allows the use of sophisticated factory automation software such as Applied’s E3 environment.

PusHBAcK On OBsOlescence

The original design of the SBC used in Applied’s Endura and Centura tools is more than 20 years old and is based on the 30 MHz Motorola 68000-type processor. As time marches on for legacy tools, about 3% of parts become obsolete each year. Most of those are electrical parts. Manufacturers began discontinuing production of the SBC’s key components in 2007; the remaining stock will soon be depleted. Virtually all of the SBC’s building blocks are impacted, including the CPU, memory/memory controllers, PLDs, FGPAs, and I/O controllers.

In addition to the obsolescence problem, many of the critical components of the legacy controller for Applied’s Endura and Centura tools have design limitations. These present a major barrier to the use of modern monitoring and control techniques that are proven to increase yields and reduce costs.

Extending the life of mature equipment is a very attractive way to minimize capital expenditures. Applied’s new controller for 200mm tools offers customers the opportunity to do just that.

The new controller greatly improves Centura and Endura performance and uses new, readily available components. It offers a low risk, plug-and-play, process-transparent system enhancement on a modern platform with the processing power to add new applications or modules, and to enable effective fault detection and fab automation. By upgrading to the new controller, customers can bring their tried-and-true 200mm production tools into the modern age.


design already includes Ethernet HSMS, eliminating the need for this additional hardware.

Figure 4 shows the results of fab-host communications tests where the new controller matched the performance of the HSMS-upgraded communication system on the customer tool. Implementation was accomplished by simply connecting to the fab host to one of the four standard Ethernet ports, with no other modification or optimization required.

Better dAtA, Better results

The new controller manages interaction within the system much faster and more efficiently than the original controller, eliminating bottlenecks that negatively impact throughput. Internal testing demonstrated an Endura throughput increase of as much as 6% from the optimized interaction between the hard disk drive (HDD) and the CPU (see figure 5).

Figure 3. Electrical performance of the new controller (in blue) was in line with five tools running the original hardware. Contact resistance, sheet resistance, via resistance and leakage were comparable for all metal levels of the device.

Figure 4. Communications rate matched performance of HSMS-enabled original controller.

Figure 5. Internal test data demonstrating the impact file volume has on the performance of legacy systems. With the original controller, as file load on the HDD increases throughput drops. With the new controller, this performance loss does not occur; throughput is optimized to full system entitlement.

Figure 2 provides film control-chart comparison data demonstrat-ing recipe transparency, with excellent repeatability of performance on the test tool before and after the installation of the new controller.

The process transparency was assessed by processing thou-sands of production wafers and measuring more than 15 electrical structures covering all metal layers, and sampling the contact, via and sheet resistance as well as wire and intermetal leakage. Figure 3

Figure 2. Thickness and resistance performance results for three film types and four chambers demonstrate transparency between the original and new controllers.

shows a subset of the electrical results, with excellent agreement between the tool running with the new controller and five additional tools running concurrent production on the same device.

The serial communications rate for the original controller is up to 19.2 kHz. A small subset of the installed base, including our beta site, has been upgraded with additional hardware to enable HSMS, which delivers up to 100MHz. The new controller upgrade


Applied Materials offers a suite of parts repair and refurbishment services that is one of the broadest in the industry. We handle repair and refurbishment for more than 2,000 different parts, including chillers, robots, MFCs, RF generators and matches, and pumps. Our repair services deliver comprehensive assembly solutions and the results are parts that operate “as new.” Serving customers from our network of repair centers and suppliers around the globe, Applied will repair more than 10,000 customer parts in 2013, saving customers nearly $75 million over new-part prices. Currently we have repair centers in Korea, Singapore, Europe, North America and Taiwan with plans to expand local capability. In addition toApplied’s own repair centers we have many prequalified regional repair suppliers that can bring focused expertise to provide a high-quality, timely repair solution.

FlexiBle rePAir PrOGrAms

Applied’s parts repair services address the varied needs of customers, from straightforward transactional repairs to quick turnaround services for both standard and process-critical parts.

■■ Recondition Parts Service (RPS): Applied RPS is a perfect solution for customers looking for a simple wayto repair broken parts and save the most money. With RPS, your broken parts are repaired and returned toyou within an agreed time frame. The closed-loop RPS covers both process-critical and non-process critical parts so you can monitor the part’s history and past process exposure. You get your own parts back, fully reconditioned to perform to new-part quality standards.

For example, one customer wanted to upgrade a key part on all their Applied tools in order to improve wafer performance. Replacing all of the existing parts with new ones would have been extremely costly. However, it was determined that the legacy parts could be refurbished into the new design and a spec was jointly developed with the customer. As the refurbishment got underway, Applied was able to make some additional change recommendations to further improve the part.

Figure 1. Customers have realized significant savings byhaving parts repaired instead of buying new ones, whether they need one part or many hundreds of parts.

Upon completion of the project, this customer was able to upgrade their existing installed base, refreshthe lifetime of these critical parts, and improve wafer performance—all at a savings of more than 50% over the much higher cost of buying new parts.

■■ Parts Exchange Services: When time-to-repair iscritical, parts exchange programs such as Applied Materials Express Exchange (ExE) and Express Repair (ExR) eliminate wait time by providing a fast exchange service for repaired parts. These programs are usually paired with our Total Parts Management (TPM) program, which consigns your inventory and manages your repair exchanges.

Applied ExE offers an exchange solution from a pool of Applied’s previously repaired parts. This is an excellent option for obtaining parts that are not considered process critical. For process critical parts the ExR program ensures that broken parts are quickly replaced with repaired ones drawn only from your own pool of repaired parts held in inventory at our repair center.

Applied’s RPS, ExE and ExR programs are proven parts repair solutions. By delivering potential savings of 30% to60%, they offer you the opportunity to lower CoO through price, wait time, and reliability. And they offer one thing more: peace of mind that your repair will be handled right by a supplier you can trust.


When GOOd PArts GO BAd: RepaiR oR ReplaCe?

Unfortunately, all the CoO reduction efforts in the world can’t overcome wear and tear on parts. Like the engine in your car or the motor in your dishwasher, sooner or later, parts will break or wear out. When they do, what are your choices?

The decision to repair or replace a part often comes down to just a few factors: the age and overall condition of the part, replacement part availability, and of course, cost. If it’s a low-cost or consumable part it’s an easy decision to pull one from inventory and replace it. But some parts, such as robots, pumps, and chillers, carry high price tags and may be too costly to have sitting in inventory until needed. In many cases, repair or refurbishment of these expensive parts is a good alternative to buying a new one if you can count on a trusted, reliable source to do the work. A repaired part can provide a savings of as much as 30–60% over the cost of a new part, and with the right supplier, immediate replacement or parts exchange programs can result in very limited wait time and lower inventory-carrying costs.

Once you’ve decided to repair rather than replace a part, it’s obviously important to select a repair service provider who is experienced and delivers consistently high-quality service at a competitive price. You want the part to perform to new-part standards with a price that represents a good savings over new-part pricing.

You may also want a comprehensive assembly repair solution that returns your part in “like new” condition rather than simply replacing a failed component within the part itself. Component repair, while cheap, may not be an optimal solution. It’s like replacing a single failed robot bearing without replacing the other bearings and seals in the assembly. You’ve temporarily fixed your problem but you’re risking another failure in the near future. That next breakdown will become another period of tool downtime with more negative impact on your costs, so a seemingly cheap repair becomes multiple repairs. Comprehensive assembly repair will return to you a part that will perform as new: one incident, one refurbished part versus multiple incidents, more wait time, and increased CoO.

In today’s fab environment, many device makers run production around the clock, 365 days a year, so tools are pushed hard to keep cranking out high-yield wafers at the lowest possible cost. Reducing cost of ownership (CoO) is always a high priority for fab managers, especially as competitive market pressures increase.

byDenny

huebner

NaNochip 19

Applied Materials offers a suite of parts repair and refurbishment services that is one of the broadest in the industry. We handle repair and refurbishment for more than 2,000 different parts, including chillers, robots, MFCs, RF generators and matches, and pumps. Our repair services deliver comprehensive assembly solutions and the results are parts that operate “as new.” Serving customers from our network of repair centers and suppliers around the globe, Applied will repair more than 10,000 customer parts in 2013, saving customers nearly $75 million over new-part prices. Currently we have repair centers in Korea, Singapore, Europe, North America and Taiwan with plans to expand local capability. In addition to Applied’s own repair centers we have many prequalified regional repair suppliers that can bring focused expertise to provide a high-quality, timely repair solution.

Flexible RepaiR pRogRams

Applied’s parts repair services address the varied needs of customers, from straightforward transactional repairs to quick turnaround services for both standard and process-critical parts.

■■ Recondition Parts Service (RPS): Applied RPS is a perfect solution for customers looking for a simple way to repair broken parts and save the most money. With RPS, your broken parts are repaired and returned to you within an agreed time frame. The closed-loop RPS covers both process-critical and non-process critical parts so you can monitor the part’s history and past process exposure. You get your own parts back, fully reconditioned to perform to new-part quality standards.

For example, one customer wanted to upgrade a key part on all their Applied tools in order to improve wafer performance. Replacing all of the existing parts with new ones would have been extremely costly. However, it was determined that the legacy parts could be refurbished into the new design and a spec was jointly developed with the customer. As the refurbishment got underway, Applied was able to make some additional change recommendations to further improve the part.

Customer AChillers,

Heat Exchangers

Customer BRF Products

Customer CChillers,

Heat Exchangers, Pumps

Ann

ual S

avin

gs R

ealiz

ed ($

thou

sand

s)

1,500

1,000

500

0

Figure 1. Customers have realized significant savings by having parts repaired instead of buying new ones, whether they need one part or many hundreds of parts.

Upon completion of the project, this customer was able to upgrade their existing installed base, refresh the lifetime of these critical parts, and improve wafer performance—all at a savings of more than 50% over the much higher cost of buying new parts.

■■ Parts Exchange Services: When time-to-repair is critical, parts exchange programs such as Applied Materials Express Exchange (ExE) and Express Repair (ExR) eliminate wait time by providing a fast exchange service for repaired parts. These programs are usually paired with our Total Parts Management (TPM) program, which consigns your inventory and manages your repair exchanges.

Applied ExE offers an exchange solution from a pool of Applied’s previously repaired parts. This is an excellent option for obtaining parts that are not considered process critical. For process critical parts the ExR program ensures that broken parts are quickly replaced with repaired ones drawn only from your own pool of repaired parts held in inventory at our repair center.

Applied’s RPS, ExE and ExR programs are proven parts repair solutions. By delivering potential savings of 30% to 60%, they offer you the opportunity to lower CoO through price, wait time, and reliability. And they offer one thing more: peace of mind that your repair will be handled right by a supplier you can trust.



As PCs start to showrevenue declines, the Internet of Things (IoT) is seen as the semiconductor industry’s next bigwave, following PCs, networking, and mobile systems. With its cloud-dependent, “everything is connected” promise, the IoT has a game-changing, futuristic aspect. While analysts agree security concerns and the productivemanagement of data beinggenerated need to be worked out before the IoT can develop fully, there is little doubt the long-range impact will be substantial.

Jeremie Bouchaud, principal MEMS and sensors analyst at market research firm IHS, estimates it will take about seven years before smart sensors and wireless networks begin to fully transform society into the connected cities and smart homes that hold so much promise.

Mario Morales, director of semiconductor research at IDC, describes a class of “intelligent systems”—defined as Internet-connected devices that analyzeinformation collected in real time—and estimates there will be some 25 billion units out there in

the next decade, larger than the combined number of PCs, phones and tablets.

Many of these intelligent systems will be in factories, “ac-curately monitoring conditionsin real time,” said Gareth Noyes, chief strategy and technology officer at Wind River. Noyes, speaking at an IDC seminar, said intelligent monitoring will support two overarching capabilities: predictive maintenance, and the “adaptive analysis of historical data, providing nuanced under-standing” of what is going on inside factories.

Bill Morelli, an IHS analyst who tracks the IoT trend, said while some MEMS/sensors will be connected to the Internet, led by the obvious example of smart-phones, others won’t. A high-end car, for example, has hundreds of sensors monitoring its inner workings, but to avoid danger-ous mischief from hackers, few of them will be connected to the Internet.

Morelli cautioned against irrational exuberance, noting thatsmart cities will require multiple businesses to agree on sharing data, some of which may be

proprietary. “When we talk of smart cities, we have to get an awful lot of disparate organiza-tions working together to makethat happen. There are numerous security and business reasons why you might not want to do that. Getting people to buy into it is pretty challenging.”

Individual companies arecreating sophisticated networks inside and among their factories, but granting access beyond a firm’s boundaries is a different story. “We are seeing a lot more automation in the factories, an increased use of sensors and machine vision. Machine-to- machine connections are a lot more prevalent, but many of those are not necessarily IP- connected sensors. The factory itself is the main outpoint of connectivity, and corporationsdon’t want access to those exter-nally” lest competitors engage in snooping, Morelli said.

Siegfried Dais, deputy chair-man of the board at Stuttgart, Germany-based engineeringand electronics company Robert Bosch GmbH, predicts that “apiece of metal or raw mate-rial will say, ‘I am the block that

will be made into product X for customer Y.’ This unfinished material already knows for which customer it is intended and carries with it all the information about where and when it will be processed.”

In the macro view, there is debate over how quickly the worldwide IoT will mature, but the impact is almost certain to be huge. Dean Freeman, semicon-ductor manufacturing analyst atGartner, Inc., noted the various predictions that—perhaps by the end of this decade—the world may be home to a trillion sensors. Eventually, a trillion sensors a year could be consumed. Freeman notes that about two-hundred ninety 200mm fabs would be required to process the 1.7 million wafers necessary to meet that trillion unit sensors figure. “It may not reach the full 290 fabs, but the main point to keep in mind is that there is very healthygrowth ahead for legacy silicon,”Freeman said.

For chipmakers, producing all those wafers, while adding speed and functionality to devices and keeping a tight rein on costs, is a significant challenge. As sensors,

by DaViD

laMMerS

faBsinternet OF tHinGs erA

As the wider society enters the Internet of Things era, semiconductor fabs are also benefiting from the analysis of data streaming from sensor-laden equipment. But the management of “big data,” and the attendant security concerns, are among the biggest challenges facing chip makers and vendors as they seek to reap the benefits of a connected fab.

in tHe


As PCs start to show revenue declines, the Internet of Things (IoT) is seen as the semiconductor industry’s next big wave, following PCs, networking, and mobile systems. With its cloud-dependent, “everything is connected” promise, the IoT has a game-changing, futuristic aspect. While analysts agree security concerns and the productive management of data being generated need to be worked out before the IoT can develop fully, there is little doubt the long-range impact will be substantial.

Jeremie Bouchaud, principal MEMS and sensors analyst at market research firm IHS, estimates it will take about seven years before smart sensors and wireless networks begin to fully transform society into the connected cities and smart homes that hold so much promise.

Mario Morales, director of semiconductor research at IDC, describes a class of “intelligent systems”—defined as Internet-connected devices that analyze information collected in real time—and estimates there will be some 25 billion units out there in

the next decade, larger than the combined number of PCs, phones and tablets.

Many of these intelligent systems will be in factories, “ac-curately monitoring conditions in real time,” said Gareth Noyes, chief strategy and technology officer at Wind River. Noyes, speaking at an IDC seminar, said intelligent monitoring will support two overarching capabilities: predictive maintenance, and the “adaptive analysis of historical data, providing nuanced under-standing” of what is going on inside factories.

Bill Morelli, an IHS analyst who tracks the IoT trend, said while some MEMS/sensors will be connected to the Internet, led by the obvious example of smart-phones, others won’t. A high-end car, for example, has hundreds of sensors monitoring its inner workings, but to avoid danger-ous mischief from hackers, few of them will be connected to the Internet.

Morelli cautioned against irrational exuberance, noting that smart cities will require multiple businesses to agree on sharing data, some of which may be

proprietary. “When we talk of smart cities, we have to get an awful lot of disparate organiza-tions working together to make that happen. There are numerous security and business reasons why you might not want to do that. Getting people to buy into it is pretty challenging.”

Individual companies are creating sophisticated networks inside and among their factories, but granting access beyond a firm’s boundaries is a different story. “We are seeing a lot more automation in the factories, an increased use of sensors and machine vision. Machine-to- machine connections are a lot more prevalent, but many of those are not necessarily IP- connected sensors. The factory itself is the main outpoint of connectivity, and corporations don’t want access to those exter-nally” lest competitors engage in snooping, Morelli said.

Siegfried Dais, deputy chair-man of the board at Stuttgart, Germany-based engineering and electronics company Robert Bosch GmbH, predicts that “a piece of metal or raw mate-rial will say, ‘I am the block that

will be made into product X for customer Y.’ This unfinished material already knows for which customer it is intended and carries with it all the information about where and when it will be processed.”

In the macro view, there is debate over how quickly the worldwide IoT will mature, but the impact is almost certain to be huge. Dean Freeman, semicon-ductor manufacturing analyst at Gartner, Inc., noted the various predictions that—perhaps by the end of this decade—the world may be home to a trillion sensors. Eventually, a trillion sensors a year could be consumed. Freeman notes that about two-hundred ninety 200mm fabs would be required to process the 1.7 million wafers necessary to meet that trillion unit sensors figure. “It may not reach the full 290 fabs, but the main point to keep in mind is that there is very healthy growth ahead for legacy silicon,” Freeman said.

For chipmakers, producing all those wafers, while adding speed and functionality to devices and keeping a tight rein on costs, is a significant challenge. As sensors,

by DaViD

laMMerS

faBsinternet OF tHinGs erA

As the wider society enters the Internet of Things era, semiconductor fabs are also benefiting from the analysisof data streaming from sensor-laden equipment. But themanagement of “big data,” and the attendant security concerns, are among the biggest challenges facing chip makers and vendors as they seek to reap the benefits of a connected fab.

in tHe

NaNochip22

processors, and wireless links become faster and less costly, the connected fab will transform fab productivity. Increasingly connected tools will help the chip industry reduce variability by monitoring each tool’s “health.” Semiconductor companies will be able to optimize a fab line for chip performance, yields or high throughput, said Alex Schwarm, senior product manager in the Applied Global Services (AGS) group.

BIG DATA, BIG CHALLENGE

Consultant Tom Sonderman, who pioneered the adoption of advanced process control (APC) techniques while at AMD, said the IoT in the semiconductor industry brings both challenges and opportunities. Key among them is dealing with the big data that sensors and other automa-tion technologies gather (see www.appliedmaterials.com/intelligence-connected-fab).

“All of this information is like a sunken treasure,” Sonderman said. “You have to figure out how to get it into the boat.”

A leading-edge fab might contain >1,000 tools, with several dozen key sensors on each tool, and each wafer may see as many as ~1,400 process steps. Huge streams of information are com-ing from fab tools, wafers, GDS (design) files, and facility systems such as chillers.

A fab will generate 140 TB per year at 20nm design rules, three times as much as at the 45nm node, according to John Scoville, senior director of ap-plication engineering at AGS.

WHAT DOES THE DATA MEAN?

“There will be a lot more data coming in as we instrument our tools to much greater levels and take subcomponent tracking much further. The challenge is: what does the data mean?” said Jeremy Read, vice president of automation products at Applied Materials.

Data analysis is moving beyond fault detection and classification (FDC) and other techniques aimed at figuring out what might have gone awry. “Now companies are pushing data analysis down to the manu-facturing technician level,” Read said. Data analysis techniques previously used by test and yield engineering groups are now be-ing employed by the technicians engaged in daily manufacturing. “A module manufacturing group may not have had access to analysis systems before; it wasn’t

necessarily part of their daily work flow. Now they need access to the data so they can more quickly ramp and manufacture the process,” he said.

Read noted that sensors and other data-gathering tools are propelling the industry to move toward a more efficient, predict-able manufacturing model. “Big data is allowing customers to get beyond reactive, beyond even proactive, to predictive. We can take a more holistic view of the tool and its behavior,” he said.

“We will see a lot more equipment monitors providing data that give a general indication of the health of the tool: parts that are beginning to wear, erratic performance indicators, and so forth. We will be able to catch the vast majority of general efficien-cies as the tool is in use, and will know, ‘Will the tool be working at its best?’ And if it not, we’ll know that now we have to fix something.”

The industry also will move to tackle chamber matching on a broad scale. Read said this has always been a topic of interest,

but so far, solid automated tech-niques to achieve and maintain it have been lacking. “Now, as tools move and are repurposed from product to product and factory to factory, chamber matching is more important than ever. It’s the quickest way to ramp production. A tool may be working perfectly well in this factory or on this device design, but how can I get it working in the next fab or the next production batch? This isn’t a new concept, but the data will help us achieve that,” he said.

PARTNER, OR GO IT ALONE

For leading-edge companies, the need to move faster to the 20nm node and beyond coincides with the new emphasis on the predictive analysis techniques that rely on production tool data. Read was asked if the largest semiconductor companies prefer to develop data analysis and predictive techniques in-house.

“There certainly is no barrier to the customer doing it them-selves,” Read said. “However, if

INTERNET OF THINGS, WORLD, 2011–2025

Source: IHS 2013

2025

60,000

50,000

40,000

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20,000

10,000

0

16,000

14,000

12,000

10,000

8,000

6,000

4,000

2,000

0202220192016201320122011

Automotive

Computers

Medical

Fixed Communications

Consumer

Military & Aerospace

Mobile Communications

Industrial

New Device Shipments

FabsIN THE INTERNET Of THINGS ERA


Applied already has the models and algorithms, and is prepared to engage with the customer in a performance-level contract based on our capabilities, then the customer has to ask, ‘Why am I reinventing the wheel? Is that truly core to my value?’”

Given the time pressures involved in getting to advanced nodes, device makers are increasingly likely to depend on suppliers for modeling, sensor prioritization, predictive maintenance algorithms, and other analytics. That being the case, “if Applied Materials has a solution, why spend six months or more trying to do it on my own, at a risk of not getting there in time?” Read said. Applied also has sought to understand “the broader context” of the data coming from individual tools, he added. “We work with the customer to address process challenges on tools and we also look at data holistically, from the viewpoint of the entire fab.”

Schwarm said Applied’s technology-enabled services go beyond the maintenance-driven relationships Applied has with chipmakers. Most large manufacturers, he said, are

already collaborating with the company on data-driven analysis projects, drawing upon Applied’s E3 performance-tracking and data-mining software, as well as libraries and models.

Applied engineers record vibration data, wafer placement images, optical emissions, and other sets of information to help enrich analysis models. For instance, the company has done some very high speed analysis, collecting data at 1000 Hz, to detect potentially damaging arcs in a plasma system. “We want to take the data we have now, along with the new sources of data, and combine them to create specialized analysis techniques,” Schwarm said. “These tech-nology service relationships are much more interactive and integrated than a typical maintenance service relationship. You are now an extension of the customer’s team for these device- and film-oriented problems.”

HAndle witH cAre

While the benefits of cooperative data analysis can provide a competitive edge, overcoming security

concerns in the hypersensitive semiconductor industry is a major challenge. “Without a doubt, security and IP-related issues are the biggest obstacles to effective collaboration between vendors and manu-facturers,” Schwarm noted.

One approach Applied takes is using servers within the fab’s firewall that are connected to the process tools only and with tightly controlled access to data.

“Applied has many layers of security, and we have to adapt to varying customer needs,” Schwarm said. “Some customers use our remote service access via secure VPN to allow Applied Materials engineers anywhere in the world to help diagnose issues. Others are more conservative and invest in having us install a server behind their firewall with access that they define.”

Schwarm noted that Applied’s analysis systems and procedures are designed with the protection of the customer’s IP in mind. “Our customers are investing to develop the most advanced processes, and we understand and respect that,” he added.

Sonderman said the connected fab, including big data analysis, is a fast-moving field. Fabs must become more efficient to supply the world with low-cost processors and sensors, and foundries must be able to protect the IP of multiple customers, who guard their design- and yield data closely.

Data analysis is bringing huge returns to forward-thinking companies with the resources to embark on the journey. Schwarm said some are already figuring out how to “dial in their factory” to align it with production goals such as optimized device performance, higher yields, faster throughputs and lower costs.

“Now that we have less expensive compute power and storage, there are systems that allow you to do this kind of analysis. For example, we can take a process tool data set and extract from it an understanding of what is driving variation. Some companies are doing that, but many are not,” Schwarm said, citing a lack of resources as a major reason.

To achieve that heightened level of “nuanced understanding” that Wind Rivers’ Noyes predicts, chipmakers will need to deal with security concerns and lack of in-house resources, which may hinder progress toward the connected fab. Read summed up the challenge as tools begin to provide more data: “We need to get better at providing the context to the information coming off of the tool. What’s needed are more personnel resources and analysis systems to be able to figure out ‘what is that data telling me?’”

For information contact alexander_schwarm @amat.com

processors, and wireless links become faster and less costly, the connected fab will transform fab productivity. Increasingly connected tools will help the chip industry reduce variability by monitoring each tool’s “health.”Semiconductor companies will be able to optimize a fab line for chip performance, yields or high throughput, said Alex Schwarm, senior product manager in the Applied Global Services (AGS)group.

BiG dAtA, BiG cHAllenGe

Consultant Tom Sonderman, who pioneered the adoption of advanced process control (APC)techniques while at AMD, said the IoT in the semiconductor industry brings both challenges and opportunities. Key amongthem is dealing with the big data that sensors and other automa-tion technologies gather (see www.appliedmaterials.com/intelligence-connected-fab).

“All of this information is likea sunken treasure,” Sondermansaid. “You have to figure out howto get it into the boat.”

A leading-edge fab might contain >1,000 tools, with several dozen key sensors on each tool, and each wafer may see as manyas ~1,400 process steps. Huge streams of information are com-ing from fab tools, wafers, GDS (design) files, and facility systems such as chillers.

A fab will generate 140 TB per year at 20nm design rules, three times as much as at the 45nm node, according to John Scoville, senior director of ap-plication engineering at AGS.

wHAt dOes tHe dAtA meAn?

“There will be a lot more data coming in as we instrument our tools to much greater levels and take subcomponent tracking much further. The challenge is: what does the data mean?” said Jeremy Read, vice president of automation products at Applied Materials.

Data analysis is moving beyond fault detection and classification (FDC) and other techniques aimed at figuring out what might have gone awry. “Now companies are pushing data analysis down to the manu-facturing technician level,” Read said. Data analysis techniques previously used by test and yield engineering groups are now be-ing employed by the technicians engaged in daily manufacturing. “A module manufacturing group may not have had access toanalysis systems before; it wasn’t

necessarily part of their daily work flow. Now they need access to the data so they can more quickly ramp and manufacture the process,” he said.

Read noted that sensors and other data-gathering tools arepropelling the industry to move toward a more efficient, predict-able manufacturing model. “Bigdata is allowing customers to get beyond reactive, beyond even proactive, to predictive. We can take a more holistic view of the tool and its behavior,” he said.

“We will see a lot more equipment monitors providing data that give a general indication of the health of the tool: parts that are beginning to wear, erratic performance indicators, and so forth. We will be able to catch the vast majority of general efficien-cies as the tool is in use, and will know, ‘Will the tool be working at its best?’ And if it not, we’ll know that now we have to fix something.”

The industry also will move to tackle chamber matching on a broad scale. Read said this has always been a topic of interest,

but so far, solid automated tech-niques to achieve and maintain it have been lacking. “Now, as tools move and are repurposed from product to product and factory to factory, chamber matching is more important than ever. It’s the quickest way to ramp production. A tool may be working perfectly well in this factory or on this device design, but how can I get it working in the next fab or the next production batch? This isn’t a new concept, but the data will help us achieve that,” he said.

PArtner, Or GO it AlOne

For leading-edge companies, the need to move faster to the 20nm node and beyond coincides with the new emphasis on the predictiveanalysis techniques that rely on production tool data. Read was asked if the largest semiconductor companies prefer to develop data analysis and predictive techniques in-house.

“There certainly is no barrier to the customer doing it them-selves,” Read said. “However, if

faBsin tHe internet OF tHinGs erA


“matched outputs” as measured by post-process metrology. Using this definition, chamber matching can be achieved bysetting the E3 run-to-run (R2R) control targets (e.g., thickness and uniformity)to be equal across the fleet. Using this approach (which we do with E3 today) the chamber outputs can be “matched”; however the chambers can be operating very differently (e.g., high temperature with

Figure 2. Chamber variance reporting with E3.

Variance Correction Systems….” [1]

Fortunately, the same software tool used for chamber variance investigation, E3, is being enhanced by Applied engineers to provide these automatic correction capabilities. The challenge is determining an algorithmicapproach to chamber variance correction.

As Applied experts looked into this problem, we first noted that a common definition applied to chamber matching is

iMpRoving yielD with Fleet ChaMber MatChing

Matching tools running identical processes is particularly critical for users migrating to more advanced nodes (<28nm). Sustaining a fleet of tools to a matched state can reduce yield losses and yield variability, allow for greater routing flexibility in the fab, identify and control process inefficiencies, and reduce time for root cause analysis of yield issues. Applied Materials understands the criticality and complexity of chamber matching, and is leveraging its algorithmic, equipment- and process expertise to develop a comprehensive solution that enables matching across many dimensions.

by ManJunath yeDatore,

JaMeS Moyne, JiMMy iSKanDar

anD ParriS hawKinS

Figure 1. Chamber-matching dimensions.

The top graph summarizes chamber variance per chamber across the fleet and indicates an unmatched chamber. Root cause investigation: On the lower left a data mining score indicates which parameters are important to the chamber mismatch; in the middle graph summary data on theseimportant variables can be compared over thecourse of many runs; on the bottom graph the sensor raw data can be analyzed and compared.

DAtA MininG SCORE

StAtiStiCAllySiGnifiCAnt

RESult

Run StAtiStiCS vS. tiME

SAMPlED SEnSORS vS. tiME

1. Hardware Configuration

2. Software Configuration

3. tool Sensors

4. Process

5. Metrology

6. Maintenance

7. End-of-line Electrical

• Mainframe, Chamber Variant• Upgrades• Facilities

• Software Revision• System Constants

• FDC Traces for P1 Sensors• Sampling Frequency

• Recipes• Process Window

• Target• Uniformity• Defect

• PM/CM Practice, Calibration• Parts & Cleans• Maintenance History

• Parametric• Yield

CHAMBER MATCHING REQUIRES MULTI-DIMENSIONAL SOLUTIONS

Ideally, the matching process would extend to every available dimension, from configuration through process setup and execution, and yield analysis, as shown in figure 1. The first step in the matching process is to perform a hardware and software audit. In many cases a “golden tool” is identified as part of a collaborative effort between the customer and Applied experts. Baselines for the hardware and software parameters are established using Applied’s tool- and process expertise. For example, we can help determine what parameters are important to the matching process and what level of matching needs to be obtained.

After the hardware and software con-figurations are matched, tool sensors and data collection come next. Applied E3 data

tAKinG tHe next steP: cHAmBer vAriAnce cOrrectiOn durinG PrOductiOn

The capabilities identified above are critical to the chamber-matching process and yield a number of benefits. However they are generally applied offline and don’t address chamber matching duringproduction (see the dark blue steps in figure 1). In examining how to improve this technology and provide chamber variancecorrection during production, we realized that current approaches do not provide the control recommendations or actionsrequired to bring operating chambers closer to a matched state; rather they provide insight into what is “wrong” and leave it to experts to determine what should be modified. While this approach is appropriate for certain dimensions of the chamber-matching problem, such as hardware, software and sensor matching, it does not work as well during production where matching decisions are often made lot-by-lot or even wafer-by-wafer. As is noted in the ITRS, what is needed is “migration of Chamber Variance Reporting to Chamber

collection and analysis configurations are matched and E3 analysis capabilities such as “chamber variance reporting” are used to determine the level of chamber match-ing and to investigate sources of mismatch, as shown in figure 2. Often the remedies involve identifying underperforming cham-bers and then matching input and output parameters to “golden” chambers. For example, in a poly etch matching process, drive current (Ion) matching was improved from a difference of 7% to 0%. Ion standard deviation within wafer was reduced by 30%. This was achieved by matching gas flows, equipment constants, RF parameters, and recipe optimization. As a result, chambers that were previously performing poorly were returned to production.


“matched outputs” as measured by post-process metrology. Using this definition, chamber matching can be achieved by setting the E3 run-to-run (R2R) control targets (e.g., thickness and uniformity) to be equal across the fleet. Using this approach (which we do with E3 today) the chamber outputs can be “matched”; however the chambers can be operating very differently (e.g., high temperature with

Figure 2. Chamber variance reporting with E3.

Variance Correction Systems….” [1]

Fortunately, the same software tool used for chamber variance investigation, E3, is being enhanced by Applied engineers to provide these automatic correction capabilities. The challenge is determining an algorithmic approach to chamber variance correction.

As Applied experts looked into this problem, we first noted that a common definition applied to chamber matching is

iMpRoving yielDwith Fleet ChaMber MatChing

Matching tools running identical processes is particularly critical for users migrating to more advanced nodes (<28nm). Sustaining a fleet of tools to a matched state can reduce yield losses and yieldvariability, allow for greater routing flexibility in the fab, identify and control process inefficiencies, and reduce time for root cause analysis of yield issues. Applied Materials understands the criticality and complexity of chamber matching, and is leveraging its algorithmic, equipment- and process expertiseto develop a comprehensive solution that enables matching across many dimensions.

by ManJunath yeDatore,

JaMeS Moyne, JiMMy iSKanDar

anD ParriS hawKinS

Figure 1. Chamber-matching dimensions.

The top graph summarizes chamber variance per chamber across the fleet and indicates an unmatched chamber. Root cause investigation: On the lower left a data mining score indicates which parameters are important to the chamber mismatch; in the middle graph summary data on these important variables can be compared over the course of many runs; on the bottom graph the sensor raw data can be analyzed and compared.

DAtA MininG SCORE

StAtiStiCAlly SiGnifiCAnt

RESult

Run StAtiStiCS vS. tiME

SAMPlED SEnSORS vS. tiME

1. Hardware Configuration

2. Software Configuration

3. tool Sensors

4. Process

5. Metrology

6. Maintenance

7. End-of-line Electrical

• Mainframe, Chamber Variant• Upgrades• Facilities

• Software Revision• System Constants

• FDC Traces for P1 Sensors• Sampling Frequency

• Recipes• Process Window

• Target• Uniformity• Defect

• PM/CM Practice, Calibration• Parts & Cleans• Maintenance History

• Parametric• Yield

CHAMBER MATCHING REQUIRES MULTI-DIMENSIONAL SOLUTIONS

Ideally, the matching process would extend to every available dimension, from configuration through process setup and execution, and yield analysis, as shown in figure 1. The first step in the matching process is to perform a hardware and software audit. In many cases a “golden tool” is identified as part of a collaborative effort between the customer and Applied experts. Baselines for the hardware and software parameters are established using Applied’stool- and process expertise. For example, we can help determine what parameters are important to the matching process and what level of matching needs to be obtained.

After the hardware and software con-figurations are matched, tool sensors and data collection come next. Applied E3 data

tAKinG tHe next steP: cHAmBer vAriAnce cOrrectiOn durinG PrOductiOn

The capabilities identified above are critical to the chamber-matching process and yield a number of benefits. However they are generally applied offline and don’t address chamber matching during production (see the dark blue steps in figure 1). In examining how to improve this technology and provide chamber variance correction during production, we realized that current approaches do not provide the control recommendations or actions required to bring operating chambers closer to a matched state; rather they provide insight into what is “wrong” and leave it to experts to determine what should be modified. While this approach is appropriate for certain dimensions of the chamber-matching problem, such as hardware, software and sensor matching, it does not work as well during production where matching decisions are often made lot-by-lot or even wafer-by-wafer. As is noted in the ITRS, what is needed is “migration of Chamber Variance Reporting to Chamber

collection and analysis configurations arematched and E3 analysis capabilities such as “chamber variance reporting” are used to determine the level of chamber match-ing and to investigate sources of mismatch, as shown in figure 2. Often the remedies involve identifying underperforming cham-bers and then matching input and output parameters to “golden” chambers. For example, in a poly etch matching process, drive current (Ion) matching was improved from a difference of 7% to 0%. Ion standarddeviation within wafer was reduced by 30%. This was achieved by matching gas flows, equipment constants, RF parameters, and recipe optimization. As a result, chambers that were previously performing poorly were returned to production.


Figure 4. Utilizing Applied E3 capabilities for improved matching through the maintenance cycle.

The collective use of these tools toprovide maintenance cycle benefits is best illustrated through an example. In a thermal process, the lamp maintenance effort can be costly and time-consuming. In a typical system lamps can fail unexpectedly causing unscheduled downtime and scrap. The maintenance recovery can be time-consuming because there are usually multiple post-maintenance (i.e., after lamp kit replacement) iterationsof lamp parameter “tuning” that include running a number of test wafers with specific characterization recipes, analyzing metrology data, and making hardwareand software adjustments. Four to ten iterations of this type are not uncommon, leading to MTTR on the order of two days or more. In addition to all of these cost-of-ownership issues, there generally is noclear methodology for matching chambers through the maintenance process.

Applied engineers are enhancing E3 and E3 services so that these issues can be addressed to reduce unscheduled downtime and scrap, improve MTBI, reduce MTTR, and match chambers throughout the entire maintenance cycle. First E3 EHM will be used during production tomonitor equipment health and point to anyunforeseen lamp (or other) issues as theyappear. As the lamp begins to degrade, E3 R2R control can be used to keep the process tuned so Cpk remains high. The R2R matching mechanism described above will be employed to keep chambers matched as much as possible during this lamp-degradation phase. E3 PdM models will predict a time horizon for lamp failure, allowing for the conversion of unscheduled

maintenance to scheduled maintenance. A confidence factor provided with the prediction can help determine the “best” future stateat which to bring the chamber down, based on an evaluation of the customer’s relativecosts for scheduled and unscheduled downtime. This “best” state will be matched across chambers. During the maintenanceprocedure, models relating the lamp-tunable settings to metrology data associated with the post-maintenance characterization runs will utilize multivariate R2R control and reverse virtual metrology to determine necessary lamp adjustments. This reduces the number of post-maintenance tuning iterations from 4–10 down to 2 or 3. Note that R2R controller matching can be employed here as well tobetter match the chambers as they return toproduction. Finally EHM can be used to verify a “fingerprint” of a healthy and matched tool that is ready for production.

mAKinG it wOrK: A PArtnerinG OF exPertise

Effective chamber matching requires the leveraging of equipment, process, sensor and statistical knowledge. This can only be achieved if Applied works closely with customers to design, develop, implement andmaintain chamber-matching solutions that are customized to be most effective for each unique situation. This advanced services-oriented approach to delivering solutionsrepresents the new paradigm in APC. Indeed, the upcoming 2013 ITRS Roadmap, Factory Integration (FI) Chapter states:

Development and maintenanceof emerging capabilities such as PdM, VM, waste management, and

utilities management incorporation into fab objectives, requires intimateknowledge of the fab objectives, process, equipment and the capabili-ties themselves. Thus it has become clear that cost-effective developmentand maintenance of these capabilities will require increased and continuouscooperation of users, OEMs and 3rdparty FI capability suppliers.[5]

Applied Materials recognizes this need and, through its Applied Global Services business, is developing advanced services for multi-dimensional chamber matching. Wewill work closely with customers to deliver fleet chamber-matching solutions that (1)address all aspects of the chamber-matching problem and (2) are tailored to customer-specific needs.


[1] 2012 International Technology Roadmap for Semiconductors (ITRS): Factory Integration Chapter, 2012 (available at www.itrs.net).

[2] J. Moyne, J. Iskandar, “Matching process controllers for improved matching of processes,” United States patent pending

[3] J. Moyne, J. Iskandar, P. Hawkins, T. Walker, A. Furest and B. Pollard, D. Stark and G. Crispieri, “Deploying an Equipment Health Monitoring Dashboard and Assessing Predictive Maintenance,”Proceedings of the 24th Annual Advanced Semiconductor Manufacturing Conference (ASMC 2013), Saratoga Springs, New York, May 2013.

[4] J. Moyne, J. Iskandar, B. Schulze, “Portable adaptable equipment health user interface,”United States patent pending

[5] 2013 International Technology Roadmap for Semiconductors (ITRS): Factory IntegrationChapter DRAFT, 2013 (final version to be available at www.itrs.net in early 2014).

lower time settings for chamber 1 and lower temperature with higher timer settings for chamber 2 producing the same thickness output). This can cause yield variability and ultimately yield loss.

An improved definition is: “chambers are matched if their states of operation are matched.” This requires that, in addition to matching process outputs, we should also try to match process conditions such as process inputs and process variables. Thus, in the above example, temperature and time setting inputs should be matched in addition to thickness output.

In order to provide improved matching during production with this amended matching definition, we are working to develop a fleet-wide matched R2R control approach.[2] The approach leverages Applied’s E3 capability for fleet-wide monitoring and coordinated control. It

matching process toward variables that are determined to be more important to yield matching. With this approach R2R control is used to match process-tunable inputs in addition to process outputs. Thus the states of the chambers are kept closer together, leading to a better matched fleet.

We are also developing a method for extending the improved matching through the maintenance cycle, again using the extensive powers of E3. A number of E3 advanced process control (APC) tools are leveraged throughout the entire maintenance cycle as shown in figure 4. Equipment health monitoring (EHM) is used during production to monitor tool health and during the maintenance recovery process to assess “fingerprints” indicating successful maintenance procedures.[3,4] Predictive maintenance (PdM) is used to predict a consistent downtime state.[3]

Virtual metrology (VM) and R2R control can be used to determine settings during maintenance recovery. Collectively these capabilities result in improved mean time between interrupt (MTBI) and mean time to repair (MTTR), and an opportunity to provide improved chamber matching through the maintenance process.

also leverages the fact that, in many R2R control solutions, the control problem is “underdetermined”; that is, there are more tunable inputs (e.g., time and temperature) than outputs to control (e.g., thickness) and so there are technically an infinite number of control solutions. With this approach, a fleet target R2R control recipe (i.e., a recipe consisting of R2R control adjustable parameters) is determined utilizing R2R control information across the fleet of tools to be matched. Depending on the matching goals, this target R2R control recipe can take many forms, including (1) a baseline recipe for a golden tool, (2) the latest R2R control recipe for that golden tool, and (3) a weighted “average” control recipe across the fleet of tools. The latter can be determined from an averaging of R2R recipe advices or an inversion of an average model across the fleet of chambers. When recipe advice is requested from a particular chamber, the E3 R2R controller picks a recipe that is closer to the target R2R control recipe (among an infinite set of choices), as shown in figure 3. The target R2R control recipe is updated as necessary. Relative weighting of variables (among inputs, and between inputs and outputs) can be used to skew the

Figure 3. Illustration of fleet-coordinated R2R control.


In this example we are controlling a single output, e.g., thickness, by tuning two input variables: power and pressure. We have a simple linear model of the chamber and a current operating point (left graph, red line and dot). With traditional R2R control, after a run, the R2R controller identifies a difference between the predicted output and actual output, adjusts the model accordingly, and selects a new operating point that is closest to the previous one (orange line and dot). In chamber-matched control with a fleet of two chambers (right graph), we are aware of the model and operating point for chamber 2 (blue line and dot). In this case, after updating the model for chamber 1, we choose an operation point (among an infinite set of choices on the line) that is closer to the operating point of chamber 2 (orange line and green dot).


Figure 4. Utilizing Applied E3 capabilities for improved matching through the maintenance cycle.

The collective use of these tools to provide maintenance cycle benefits is best illustrated through an example. In a thermal process, the lamp maintenance effort can be costly and time-consuming. In a typical system lamps can fail unexpectedly causing unscheduled downtime and scrap. The maintenance recovery can be time-consuming because there are usually multiple post-maintenance (i.e., after lamp kit replacement) iterations of lamp parameter “tuning” that include running a number of test wafers with specific characterization recipes, analyzing metrology data, and making hardware and software adjustments. Four to ten iterations of this type are not uncommon, leading to MTTR on the order of two days or more. In addition to all of these cost-of-ownership issues, there generally is no clear methodology for matching chambers through the maintenance process.

Applied engineers are enhancing E3 and E3 services so that these issues can be addressed to reduce unscheduled downtime and scrap, improve MTBI, reduce MTTR, and match chambers throughout the entire maintenance cycle. First E3 EHM will be used during production to monitor equipment health and point to any unforeseen lamp (or other) issues as they appear. As the lamp begins to degrade, E3 R2R control can be used to keep the process tuned so Cpk remains high. The R2R matching mechanism described above will be employed to keep chambers matched as much as possible during this lamp-degradation phase. E3 PdM models will predict a time horizon for lamp failure, allowing for the conversion of unscheduled

maintenance to scheduled maintenance. A confidence factor provided with the prediction can help determine the “best” future state at which to bring the chamber down, based on an evaluation of the customer’s relative costs for scheduled and unscheduled downtime. This “best” state will be matched across chambers. During the maintenance procedure, models relating the lamp-tunable settings to metrology data associated with the post-maintenance characterization runs will utilize multivariate R2R control and reverse virtual metrology to determine necessary lamp adjustments. This reduces the number of post-maintenance tuning iterations from 4–10 down to 2 or 3. Note that R2R controller matching can be employed here as well to better match the chambers as they return to production. Finally EHM can be used to verify a “fingerprint” of a healthy and matched tool that is ready for production.

mAKinG it wOrK: A PArtnerinG OF exPertise

Effective chamber matching requires the leveraging of equipment, process, sensor and statistical knowledge. This can only be achieved if Applied works closely with customers to design, develop, implement and maintain chamber-matching solutions that are customized to be most effective for each unique situation. This advanced services-oriented approach to delivering solutions represents the new paradigm in APC. Indeed, the upcoming 2013 ITRS Roadmap, Factory Integration (FI) Chapter states:

Development and maintenance of emerging capabilities such as PdM, VM, waste management, and

utilities management incorporation into fab objectives, requires intimate knowledge of the fab objectives, process, equipment and the capabili-ties themselves. Thus it has become clear that cost-effective development and maintenance of these capabilities will require increased and continuous cooperation of users, OEMs and 3rd party FI capability suppliers.[5]

Applied Materials recognizes this need and, through its Applied Global Services business, is developing advanced services for multi-dimensional chamber matching. We will work closely with customers to deliver fleet chamber-matching solutions that (1) address all aspects of the chamber-matching problem and (2) are tailored to customer-specific needs.


[1] 2012 International Technology Roadmap for Semiconductors (ITRS): Factory Integration Chapter, 2012 (available at www.itrs.net).

[2] J. Moyne, J. Iskandar, “Matching process controllers for improved matching of processes,” United States patent pending

[3] J. Moyne, J. Iskandar, P. Hawkins, T. Walker, A. Furest and B. Pollard, D. Stark and G. Crispieri, “Deploying an Equipment Health Monitoring Dashboard and Assessing Predictive Maintenance,” Proceedings of the 24th Annual Advanced Semiconductor Manufacturing Conference (ASMC 2013), Saratoga Springs, New York, May 2013.

[4] J. Moyne, J. Iskandar, B. Schulze, “Portable adaptable equipment health user interface,” United States patent pending

[5] 2013 International Technology Roadmap for Semiconductors (ITRS): Factory Integration Chapter DRAFT, 2013 (final version to be available at www.itrs.net in early 2014).

lower time settings for chamber 1 and lower temperature with higher timer settings for chamber 2 producing the same thickness output). This can cause yield variability and ultimately yield loss.

An improved definition is: “chambers are matched if their states of operation are matched.” This requires that, in addition tomatching process outputs, we should also try to match process conditions such as process inputs and process variables. Thus, in the above example, temperature and time setting inputs should be matched in addition to thickness output.

In order to provide improved matching during production with this amended matching definition, we are working todevelop a fleet-wide matched R2R control approach.[2] The approach leverages Applied’s E3 capability for fleet-wide monitoring and coordinated control. It

matching process toward variables that are determined to be more important to yield matching. With this approach R2R control is used to match process-tunable inputs in addition to process outputs. Thus the states of the chambers are kept closer together, leading to a better matched fleet.

We are also developing a method for extending the improved matching through the maintenance cycle, again using the extensive powers of E3. A number of E3 advanced process control (APC)tools are leveraged throughout the entire maintenance cycle as shown in figure 4. Equipment health monitoring (EHM) is used during production to monitor tool health and during the maintenance recovery process to assess “fingerprints” indicating successful maintenance procedures.[3,4]

Predictive maintenance (PdM) is used topredict a consistent downtime state.[3]

Virtual metrology (VM) and R2R control can be used to determine settings during maintenance recovery. Collectively these capabilities result in improved mean time between interrupt (MTBI) and mean time to repair (MTTR), and an opportunity to provide improved chamber matching through the maintenance process.

also leverages the fact that, in many R2R control solutions, the control problem is “underdetermined”; that is, there are more tunable inputs (e.g., time and temperature)than outputs to control (e.g., thickness) and so there are technically an infinite number of control solutions. With this approach, a fleet target R2R control recipe (i.e., a recipe consisting of R2R control adjustable parameters) is determined utilizing R2R control information across the fleet of tools to be matched. Depending on the matching goals, this target R2R control recipe can take many forms, including (1) a baseline recipe for a golden tool, (2) the latest R2R control recipe for that golden tool, and (3) aweighted “average” control recipe across the fleet of tools. The latter can be determined from an averaging of R2R recipe advices or an inversion of an average model across the fleet of chambers. When recipe advice is requested from a particular chamber, the E3 R2R controller picks a recipe that is closer to the target R2R control recipe (among an infinite set of choices), as shown in figure 3. The target R2R control recipe is updated as necessary. Relative weighting of variables (among inputs, and between inputs and outputs) can be used to skew the

Figure 3. Illustration of fleet-coordinated R2R control.


In this example we are controlling a single output, e.g., thickness, by tuning two input variables: power and pressure. We have a simple linear model of the chamber and a current operating point (left graph, red line and dot). With traditional R2R control, after a run, the R2R controller identifies a difference between the predicted output and actual output, adjusts the model accordingly, and selects a new operating point that is closest to the previous one (orange line and dot). In chamber-matched control with a fleet of two chambers (right graph), we are aware of the model and operating point for chamber 2 (blue line and dot). In this case, after updating the model for chamber 1, we choose an operation point (among an infinite set of choices on the line) that is closer to the operating point of chamber 2 (orange line and green dot).


Finally, what really drives our responsiveness when it comes to difficult problems such as defects and particles is AGS’s3000-strong customer engineering (CE) team. Today’s fabs generate a flood of process- and equipment-related data that can be used to optimize processes and increase yields. Our CEs are receiving extensive training in IT functionality and data manipulation so they can effectively interpret the trove of data coming from software-based monitoring and control systems, sensors, and other computer-driven equipment.

nfS: Can you give us an example of how better data analysis is paying off for customers?

Pappis: Data analysis and the use of appropriate sensors and control systems are key to helping customers understand the health of the tool and provide clues that make it possible to predict and prevent problems. One example that comes to mind has to do with an etch chamber. One of the things we typically look at is backside helium pressure. But what does that really tell us?Often when there’s a spike in pressure it is in fact a backside helium fault, so before we were able to characterize these chambers the way we can now, we always assumed that was the problem and we would routinely vent the chamber and start maintenance.

However, at one customer site, when we tied these chambers into Applied’s E3 factory automation software environment, we found that not all backside helium pressure events are created equal! Some of them can be handled without actually having to vent the chamber. Others just amount to the normal wear pattern of the e-chuck. Sometimes they mean there’sa backside particle or a placement error we can handle just by calibrating the robot. This is a case where we can help the customer manage a tool in production much more efficiently bycharacterizing things better and putting FDC models in place.

With 30,000 machines installed, we are learning faster than anyone how important accurate data analysis is, and we’re taking this capability across the installed base. For example, when our FabVantage consultants begin a customer engagement, they do a deep discovery to determine the critical issues holding the customer back in terms of cycle time, productivity, yield, and so forth. No two customers have the same needs, and even the same customer may have very different needs and priorities at different times and locations. Therefore, what we do is never ‘one-size-fits-all.’ What wereally consider business as usual is to customize cost- and quality-competitive solutions to meet the exact needs of a particular fab at a given time.

nfS: What does that mean for your organization on a practical, day-to-day level?

Pappis: Cost savings extend beyond parts, of course. Our new iSYScontroller for the subfab is designed to give customers a very fast payback via electricity and fuel savings for abatement. In manycases the payback period is two years, and for those located in areas of the world where electricity is incredibly expensive, payback is one year or even less.

There are also things we can do to help customers improve their technical performance—in process capability, in defect perfor-mance, which can also improve uptime and lower cost. Our Lava Coat II technology is a good example. We developed it for our PVD chambers to reduce the frequency of service intervals and lower the defect densities in the chamber, which can have a sig-nificant impact on yield. This coating can reduce defect levels by25% and boost mean time between cleans by up to 1.5x. While that may not sound like much, consider that whenever you take aPVD chamber out of production, you have to vent it to do any kind of a clean or a kit change. Then you have to recover it to the same performance levels, so it becomes a 24- to 72-hour service event. If you can increase the time you’re running product by 1.5x before you have to do a clean, and if you can also reduce the overall defect level during that run by 25%, there’s a huge productivity gain. These are the kinds of services that are true value adds for our customers, and they keep asking for more of them.

Our goal is to have customers always be willing to give us a “first look and a last chance.” That’s really critical for us, and what’skey to making it happen is our willingness to listen openly to what a customer is saying, and then provide the relevant technologies, tools, people and whatever other resources are required—on whatever basis makes the most sense—given a customer’sspecific situation.

nfS: But what gives you the ability to handle customers’ highest-level problems? How are you different from other service providers?

Pappis: We’re different in almost every way that counts! First of all we have unparalleled tool knowledge across a broad portfolio of process technologies. Second, AGS is at work every day in production environments in the semiconductor, solar and displayareas supporting an installed base of about 30,000 Applied Materials tools. Customers typically run these machines for 20 to 25 years, and so every time Applied has shipped a tool, for the following two decades we have had recurring opportunities tohelp the customer get the best possible result out of their capital asset, and to learn a great deal from that experience.

nfS: you’ve said that a changing semiconductor industry requires service providers to provide different types of support than before. Can you elaborate?

Pappis: The service business used to be driven by the need to keep systems up and running: identifying mechanical problems, adjusting hardware, replacing parts and so forth. Equipment reliability isn’t our customers’ main service need anymore—the reliability of electromechanical systems is much greater than it used to be. What’s driving everything now is vastly increasing process complexity and the high costs that come with not getting it done right or not doing it fast enough. Service today is about fine-tuning processes for optimum performance and managing on-board technology so customers can predict and prevent problems before they impact device performance and yield. And that takes a much more advanced service model that integrates state-of-the-art technologies, expanded service staff expertise, and an unprecedented level of collaboration between the customer and the OEM.

There will be more radical technological change in our industry in the next five years than over the past 15, because scaling alone can no longer keep us on pace with Moore’s Law. You can see it starting to happen already—new architectures like Fin-FETS and 3D structures, an explosion of new materials into what were relatively stable gate and interconnect stacks—all of this requires more process steps, much narrower process windows, many more interacting variables, and higher capital costs.

Charlie PaPPiS:

seRving up a BetteR outCoMe

Now, it certainly isn’t easy to address these issues, so what that means for service providers like AGS is that we must be able to support customers as a high-level, trusted partner. We need to be able to help them solve their highest-value problems—the ones with the greatest impact on the performance and yield of the de-vices they make—so that, for example, they can successfully ramp a megafab to run the most aggressive nodes at the right yield, the right cost, the right quality and with the right cycle times. It’s criti-cal for the customer’s success to be able to do that, and when you come down to it, that’s really what a modern service organization like AGS has to focus on: enabling the customer’s success, helping them achieve dramatically better results with our equipment. So we’re evolving in order to do that more effectively.

nfS: that’s a huge challenge. How are you going about it?Pappis: It’s really a three-part strategy. Trust is bedrock. It underpins all

our relationships with customers. The complexity and sensitivity of issues impacting device performance and yield mean we have to stay more closely connected to the customer than ever. You can’t do that without a solid foundation of trust. It’s something we always work to build on, because while it’s one thing to say we are willing to collaborate with customers to solve their highest-stakes problems, it’s another to actually deliver on the promise.

Trust gets us an invitation to the table. Once we’re there, being competitive on cost and quality are absolute prerequisites. Our customers have choices, so we need to define competitiveness the same way they do. In a way, it’s like running a race where there’s no finish line. The job is never done because we’re always trying to make further improvements in what we offer.

If we’ve proven we can be trusted to deliver on the basics of cost and quality, the door opens for us to work at higher levels to meet a customer’s most important device-performance and yield challenges. It’s there that I think AGS can demonstrate real innovation and leadership to help customers reach their goals.

Success in today’s semiconductor industry goes beyond just keeping the fab running—it takes faster ramps and higher yields at lower costs. Charlie Pappis, group vice president and general manager of Applied Global Services (AGS), contends that the service model has evolved as well, from providing traditional maintenance, parts and repair services to an expanded role as a strategic customer partner.

In a recent interview with Nanochip Fab Solutions (NFS), Pappis, a 27-year veteran of Applied Materials and head of AGS for the last four years, discussed customers’ increasingly sophisticated support needs and what that means for his large service organization.

“While it’s one thing to say we are willing to collaborate with customers to solve their highest-stakes problems, it’s another to

actually deliver on the promise."


Finally, what really drives our responsiveness when it comes to difficult problems such as defects and particles is AGS’s 3000-strong customer engineering (CE) team. Today’s fabs generate a flood of process- and equipment-related data that can be used to optimize processes and increase yields. Our CEs are receiving extensive training in IT functionality and data manipulation so they can effectively interpret the trove of data coming from software-based monitoring and control systems, sensors, and other computer-driven equipment.

nfS: Can you give us an example of how better data analysis is paying off for customers?

Pappis: Data analysis and the use of appropriate sensors and control systems are key to helping customers understand the health of the tool and provide clues that make it possible to predict and prevent problems. One example that comes to mind has to do with an etch chamber. One of the things we typically look at is backside helium pressure. But what does that really tell us? Often when there’s a spike in pressure it is in fact a backside helium fault, so before we were able to characterize these chambers the way we can now, we always assumed that was the problem and we would routinely vent the chamber and start maintenance.

However, at one customer site, when we tied these chambers into Applied’s E3 factory automation software environment, we found that not all backside helium pressure events are created equal! Some of them can be handled without actually having to vent the chamber. Others just amount to the normal wear pattern of the e-chuck. Sometimes they mean there’s a backside particle or a placement error we can handle just by calibrating the robot. This is a case where we can help the customer manage a tool in production much more efficiently by characterizing things better and putting FDC models in place.

With 30,000 machines installed, we are learning faster than anyone how important accurate data analysis is, and we’re taking this capability across the installed base. For example, when our FabVantage consultants begin a customer engagement, they do a deep discovery to determine the critical issues holding the customer back in terms of cycle time, productivity, yield, and so forth. No two customers have the same needs, and even the same customer may have very different needs and priorities at different times and locations. Therefore, what we do is never ‘one-size-fits-all.’ What we really consider business as usual is to customize cost- and quality-competitive solutions to meet the exact needs of a particular fab at a given time.

nfS: What does that mean for your organization on a practical, day-to-day level?

Pappis: Cost savings extend beyond parts, of course. Our new iSYS controller for the subfab is designed to give customers a very fast payback via electricity and fuel savings for abatement. In many cases the payback period is two years, and for those located in areas of the world where electricity is incredibly expensive, payback is one year or even less.

There are also things we can do to help customers improve their technical performance—in process capability, in defect perfor-mance, which can also improve uptime and lower cost. Our Lava Coat II technology is a good example. We developed it for our PVD chambers to reduce the frequency of service intervals and lower the defect densities in the chamber, which can have a sig-nificant impact on yield. This coating can reduce defect levels by 25% and boost mean time between cleans by up to 1.5x. While that may not sound like much, consider that whenever you take a PVD chamber out of production, you have to vent it to do any kind of a clean or a kit change. Then you have to recover it to the same performance levels, so it becomes a 24- to 72-hour service event. If you can increase the time you’re running product by 1.5x before you have to do a clean, and if you can also reduce the overall defect level during that run by 25%, there’s a huge productivity gain. These are the kinds of services that are true value adds for our customers, and they keep asking for more of them.

Our goal is to have customers always be willing to give us a “first look and a last chance.” That’s really critical for us, and what’s key to making it happen is our willingness to listen openly to what a customer is saying, and then provide the relevant technologies, tools, people and whatever other resources are required—on whatever basis makes the most sense—given a customer’s specific situation.

nfS: But what gives you the ability to handle customers’ highest-level problems? How are you different from other service providers?

Pappis: We’re different in almost every way that counts! First of all we have unparalleled tool knowledge across a broad portfolio of process technologies. Second, AGS is at work every day in production environments in the semiconductor, solar and display areas supporting an installed base of about 30,000 Applied Materials tools. Customers typically run these machines for 20 to 25 years, and so every time Applied has shipped a tool, for the following two decades we have had recurring opportunities to help the customer get the best possible result out of their capital asset, and to learn a great deal from that experience.

nfS: you’ve said that a changing semiconductor industry requires service providers to provide different types of support than before. Can you elaborate?

Pappis: The service business used to be driven by the need to keep systems up and running: identifying mechanical problems, adjusting hardware, replacing parts and so forth. Equipment reliability isn’t our customers’ main service need anymore—the reliability of electromechanical systems is much greater than it used to be. What’s driving everything now is vastly increasing process complexity and the high costs that come with not getting it done right or not doing it fast enough. Service todayis about fine-tuning processes for optimum performance and managing on-board technology so customers can predict and prevent problems before they impact device performance andyield. And that takes a much more advanced service model that integrates state-of-the-art technologies, expanded servicestaff expertise, and an unprecedented level of collaboration between the customer and the OEM.

There will be more radical technological change in our industry in the next five years than over the past 15, because scaling alone can no longer keep us on pace with Moore’s Law. You can see it starting to happen already—new architectures like Fin-FETS and 3D structures, an explosion of new materials into what were relatively stable gate and interconnect stacks—all of this requires more process steps, much narrower process windows, many more interacting variables, and higher capital costs.

Charlie PaPPiS:

seRvingup aBetteRoutCoMe

Now, it certainly isn’t easy to address these issues, so what that means for service providers like AGS is that we must be able tosupport customers as a high-level, trusted partner. We need to be able to help them solve their highest-value problems—the ones with the greatest impact on the performance and yield of the de-vices they make—so that, for example, they can successfully ramp a megafab to run the most aggressive nodes at the right yield, the right cost, the right quality and with the right cycle times. It’s criti-cal for the customer’s success to be able to do that, and when you come down to it, that’s really what a modern service organization like AGS has to focus on: enabling the customer’s success, helping them achieve dramatically better results with our equipment. So we’re evolving in order to do that more effectively.

nfS: that’s a huge challenge. How are you going about it?Pappis: It’s really a three-part strategy. Trust is bedrock. It underpins all

our relationships with customers. The complexity and sensitivity of issues impacting device performance and yield mean we have to stay more closely connected to the customer than ever. You can’t do that without a solid foundation of trust. It’s something wealways work to build on, because while it’s one thing to say we are willing to collaborate with customers to solve their highest-stakes problems, it’s another to actually deliver on the promise.

Trust gets us an invitation to the table. Once we’re there, being competitive on cost and quality are absolute prerequisites. Our customers have choices, so we need to define competitiveness the same way they do. In a way, it’s like running a race where there’s no finish line. The job is never done because we’re always trying to make further improvements in what we offer.

If we’ve proven we can be trusted to deliver on the basics of cost and quality, the door opens for us to work at higher levels to meet a customer’s most important device-performance and yield challenges. It’s there that I think AGS can demonstrate real innovation and leadership to help customers reach their goals.

Success in today’s semiconductor industry goes beyond just keeping the fab running—it takes faster ramps and higher yields at lower costs. Charlie Pappis, group vice president and general manager of Applied Global Services (AGS),contends that the service model has evolved aswell, from providing traditional maintenance, parts and repair services to an expanded role as a strategic customer partner.

In a recent interview with Nanochip Fab Solutions (NFS), Pappis, a 27-year veteran of Applied Materials and head of AGS for the last four years, discussed customers’ increasingly sophisticated support needs and what that means for his largeservice organization.

“While it’s one thing to say we are willing to collaborate with customers to solve theirhighest-stakes problems, it’s another to

actually deliver on the promise."


applieD MateRials SerViCe PortFolio

Applied Performance ServicestechEdge

■■ Combine traditional support with advanced software control

■■ Provide greater predictability and prevention

■■ Identify productivity loss

fabvantage ■■ Uncover hidden productivity■■ Drive predictability of yield and output ■■ Process optimization■■ Cost containment

Applied Managed Service

Engineer On-Site Service

techEdge Excursion Controltool Output and CostPreventive Maintenance

ServicetechEdge Prizm Data Mining

yield and Predictability

transactional Service future Planned fab Productivity

certiFied servicesChoose from our flexible service solutions to optimize system and factory efficiency.

tecHnOlOGy-enABled servicesMove from reactive to predict/prevent operations. TechEdge services can take your fab operations to the next level.

FAB cOnsultinG servicesAvailable on an as-needed, project basis, FabVantage consultants bring deep expertise and advanced analytical tools to help solve tough production problems that have the greatest impact on your business.

nfS: What do you consider to be among the most difficult things customers are trying to do today?

Pappis: A number of our customers are grappling with the myriad issues involved with ramping these huge fabs: fabs designed for 60,000, 80,000 or even 100,000 wafer starts per month at 28 nanometers or other advanced nodes. Sure, they may have yield on pilot lots, they may have yield when they’re running a couple thousand wafers a month, but now they have to take that production to a level ten times higher! And what we’re finding is, they haven’t solved all of the problems that come with 7x24 operation at 60,000 wafers a month.

We have a number of FabVantage consulting agreements where we’re actually helping customers deal with some of these challenges. Consultants use a disciplined discovery process and tap into the Applied knowledge base, then combine it with the customer’s own data to give a more complete picture of what’s happening with the customer’s tool or line. Our customers certainly have the ability to solve these problems on their own. But with help from the FabVantage team they can identify the problem—and the solution—faster. And in the process, they often uncover opportunities for additional improvements as well.

nfS: you talk about the blend of technology and the know-how of the service team. Where does the technology come in?

Pappis: Events like arcing and process excursions can have a huge detrimental effect on device performance and yields, and so the ability to predict and prevent them before they happen gives customers a major competitive advantage. Our software packages and new TechEdge service offerings combine advanced software and analytics tools with experts who have special training in yield management, data analysis and factory-floor dynamics. The result is a map of what’s happening with the tool that helps pinpoint potential problems. This is a capability all our customers can benefit from, whether they are producing at the latest technology node on 300mm wafers or making analog, power, sensor, MEMS and other products on 200mm wafers.

For example, TechEdge Prizm, for use with Applied CD-SEM tools in 300mm environments, is very helpful in chamber- and fleet matching. We often find customers have tied their critical-dimension data to just one lithography tool, but this enables all the customer’s CD-SEMs to be precisely matched so they can get an entire tool fleet running in such a way that an expensive lithography tool wouldn’t ever become a bottleneck.

Another example is Applied E3 software. It brings high levels of predictability and performance by helping to pose and answer questions like, which is the crucial data to be tracking? Is it one sensor or a combination? Are FDC data rates fast enough to cap-ture subtle but meaningful changes? Are control limits effective? Things may be running well, but could they run even better?

“Our attitude is that AGS exists solely to enable customer success, and as the complexity of fab operations increases, AGS will evolve in lockstep with customers."

“It’s ironic that the products our tools help to create are in turn enabling some of the most exciting service solutions of the last

decade or more. "

nfS: Okay, but don’t customers have concerns about letting an outside organization such as AGS become so deeply immersed in their proprietary data?

Pappis: Sharing of customer data and intellectual property is a huge concern for all of us in this industry, customers and suppliers alike. It’s the lifeblood of our businesses. At a time when there is greater collaboration than ever, protecting the data we exchange is a critical priority. In addition to our stringent IP handling practices and employee certification processes, the simplest way to secure customer data is to ensure that it stays on the customer site.

AGS installs dedicated computers at customer facilities that have no external connections. Only the data the customer defines and allows AGS to access is drawn. We tell the customer beforehand what we need and the customer either allows it or disallows it. At the tool level, we use a parallel port to access the very same data the customer is accessing and nothing else.

Fundamentally, it comes down to forging relationships with customers that are built on mutual trust. It’s in the best interests of both of us to carefully handle the confidential information we share.

nfS: Charlie, any final thoughts?Pappis: It’s ironic that the products our tools help to create are in

turn enabling some of the most exciting service solutions of the last decade or more. Sensors and controllers, combined with software, networks, and modeling and simulation methods, are opening the door to an amazing array of service offerings that go well beyond traditional equipment maintenance practices.

Our attitude is that AGS exists solely to enable customer success, and as the complexity of fab operations increases, AGS will evolve in lockstep with customers. We are, and always will be, a trustworthy and capable partner dedicated to helping customers uncover and solve even their most difficult production challenges.

nfS: thank you for your time.

Charlie PaPPiS:


At Applied Materials, we understand that our success is tied to that of our customers. By listening first, then attacking challenges that are meaningful to customers, we can help them

ImProve equIPmenT anD fab ProDuCTIvITy

The AGS service portfolio offers many flexible options—from basic hourly engineering and maintenance services to more advanced, integrated services.

deliver competitive products with higher yield and output. The service products from Applied Global Services are designed to address critical needs like maintenance efficiency and cost reduction, while also providing advanced service technologies to help customers optimize equipment and factory productivity.

We offer a broad portfolio of customizable solutions for customers in the semiconductor, solar and display industries. Options range from basic hourly

Applied services target key manufacturing challenges to:

• Increase maintenance efficiency• Improve output• Reduce costs

Collaborating with Customers to Predict and Solve Problems

helPing CustoMeRsengineering and preventive maintenance services to advanced consultative services for highly dynamic production environments.

With more than 3,000 field engineers and nearly 33,000 Applied Materials systems installed globally—across many technologies and running thousands of processes—we are uniquely equipped to help identify, resolve, and predict or prevent customer’s most difficult problems, at both the tool- and fab operations levels.


applieD MateRials SerViCe PortFolio

Applied Performance ServicestechEdge

■■ Combine traditional support with advanced software control

■■ Provide greater predictability and prevention

■■ Identify productivity loss

fabvantage ■■ Uncover hidden productivity■■ Drive predictability of yield and output ■■ Process optimization■■ Cost containment

Applied Managed Service

Engineer On-Site Service

techEdge Excursion Controltool Output and CostPreventive Maintenance

ServicetechEdge Prizm Data Mining

yield and Predictability

transactional Service future Planned fab Productivity

certiFied servicesChoose from our flexible service solutions to optimize system and factory efficiency.

tecHnOlOGy-enABled servicesMove from reactive to predict/prevent operations. TechEdge services can take your fab operations to the next level.

FAB cOnsultinG servicesAvailable on an as-needed, project basis, FabVantage consultants bring deep expertise and advanced analytical tools to help solve tough production problems that have the greatest impact on your business.

nfS: What do you consider to be among the most difficult things customers are trying to do today?

Pappis: A number of our customers are grappling with the myriad issues involved with ramping these huge fabs: fabs designed for 60,000, 80,000 or even 100,000 wafer starts per month at 28 nanometers or other advanced nodes. Sure, they may have yield on pilot lots, they may have yield when they’re running a couple thousand wafers a month, but now they have to take that production to a level ten times higher! And what we’re finding is, they haven’t solved all of the problems that come with 7x24 operation at 60,000 wafers a month.

We have a number of FabVantage consulting agreements where we’re actually helping customers deal with some of these challenges. Consultants use a disciplined discovery process and tap into the Applied knowledge base, then combine it with the customer’s own data to give a more complete picture of what’s happening with the customer’s tool or line. Our customers certainly have the ability to solve these problems on their own. But with help from the FabVantage team they can identify the problem—and the solution—faster. And in the process, they often uncover opportunities for additional improvements as well.

nfS: you talk about the blend of technology and the know-how of the service team. Where does the technology come in?

Pappis: Events like arcing and process excursions can have a huge detrimental effect on device performance and yields, and so the ability to predict and prevent them before they happen gives customers a major competitive advantage. Our software packages and new TechEdge service offerings combine advanced software and analytics tools with experts who have special training in yield management, data analysis and factory-floor dynamics. The result is a map of what’s happening with the tool that helps pinpoint potential problems. This is a capability all our customers can benefit from, whether they are producing at the latest technology node on 300mm wafers or making analog, power, sensor, MEMS and other products on 200mm wafers.

For example, TechEdge Prizm, for use with Applied CD-SEM tools in 300mm environments, is very helpful in chamber- and fleet matching. We often find customers have tied their critical-dimension data to just one lithography tool, but this enables all the customer’s CD-SEMs to be precisely matched so they can get an entire tool fleet running in such a way that an expensive lithography tool wouldn’t ever become a bottleneck.

Another example is Applied E3 software. It brings high levels of predictability and performance by helping to pose and answer questions like, which is the crucial data to be tracking? Is it one sensor or a combination? Are FDC data rates fast enough to cap-ture subtle but meaningful changes? Are control limits effective? Things may be running well, but could they run even better?

“Our attitude is that AGS exists solely to enable customer success, and as the complexity of fab operations increases, AGS will evolve in lockstep with customers."

“It’s ironic that the products our tools help to create are in turn enabling some of the most exciting service solutions of the last

decade or more. "

nfS: Okay, but don’t customers have concerns about letting an outside organization such as AGS become so deeply immersed in their proprietary data?

Pappis: Sharing of customer data and intellectual property is a huge concern for all of us in this industry, customers and suppliers alike. It’s the lifeblood of our businesses. At a time when there is greater collaboration than ever, protecting the data we exchange is a critical priority. In addition to our stringent IP handling practices and employee certification processes, the simplest way to secure customer data is to ensure that it stays on the customer site.

AGS installs dedicated computers at customer facilities that have no external connections. Only the data the customer defines and allows AGS to access is drawn. We tell the customer beforehand what we need and the customer either allows it or disallows it. At the tool level, we use a parallel port to access the very same data the customer is accessing and nothing else.

Fundamentally, it comes down to forging relationships with customers that are built on mutual trust. It’s in the best interests of both of us to carefully handle the confidential information we share.

nfS: Charlie, any final thoughts?Pappis: It’s ironic that the products our tools help to create are in

turn enabling some of the most exciting service solutions of the last decade or more. Sensors and controllers, combined with software, networks, and modeling and simulation methods, are opening the door to an amazing array of service offerings that go well beyond traditional equipment maintenance practices.

Our attitude is that AGS exists solely to enable customer success, and as the complexity of fab operations increases, AGS will evolve in lockstep with customers. We are, and always will be, a trustworthy and capable partner dedicated to helping customers uncover and solve even their most difficult production challenges.

nfS: thank you for your time.

Charlie PaPPiS:


At Applied Materials, we understand that our success is tied to that of our customers. By listening first, then attacking challenges that are meaningful to customers, we can help them

ImProve equIPmenT anD fab ProDuCTIvITy

The AGS service portfolio offers many flexible options—from basic hourly engineering and maintenance services to more advanced, integrated services.

deliver competitive products with higher yield and output. The service products from Applied Global Services are designed to address critical needs like maintenance efficiency and cost reduction, while also providing advanced service technologies to help customers optimize equipment and factory productivity.

We offer a broad portfolio of customizable solutions for customers in the semiconductor, solar and display industries. Options range from basic hourly

Applied services target key manufacturing challenges to:

• Increase maintenance efficiency• Improve output• Reduce costs

Collaborating with Customers to Predict and Solve Problems

helPing CustoMeRsengineering and preventive maintenance services to advanced consultative services for highly dynamic production environments.

With more than 3,000 field engineers and nearly 33,000 Applied Materials systems installed globally—across many technologies and running thousands of processes—we are uniquely equipped to help identify, resolve, and predict or prevent customer’s most difficult problems, at both the tool- and fab operations levels.


Figure 2. Numerous factors affect yield in the manufacturing of today’s devices.

Figure 3. Complex process integrations, such as high-k metal gate, increase the potential for a wide array of yield-limiting defects.

cHiPmAKer’s tOP-dOwn deFect resOlutiOn

Chip manufacture at today’s most advanced sub-40nm nodes is significantly more demanding than at previous generations. The challenges stem from the introduction of new materials, new device and integration considerations, tighter process margins, and process interactions, all of which affect yield. Figure 3, illustrating high-k metal gate technology, shows the many factors affecting yield. Process interactions, arising primarily from the greater number of fabrication steps; gap-fill, planarization, and patterning challenges; and film interactions create more stringent

requirements for equipment and process to function precisely. These in turn necessitate intricate FDC sensor excursion control and chamber-performance matching as discussed later.

Conventional yield loss analysis in the fab employs a top-down analysis of defect issues based on Fail Pareto charts of finished wafer lots. Table 1 lists key contributors to yield loss for a typical 28nm logic process flow that could appear in a Pareto chart. Many of these derive from multiple sources. Effective, permanent resolution of each issue requires understanding of all potential causes and holistic remediation. The right side of the table shows that correcting some

issues will require complete inves-tigation of hardware, process, FDC sensors, and integration.

The conventional Fail Pareto approach to yield improvement implements failure analysis and root cause determination for each defect type appearing on the chart through an iterative approach that first examines process integration, then the unit process, and lastly hardware to determine and remedy the source of the defect. This method is effective only if resolution of the defect is permanent and the Pareto remains stable over successive process qualifications. If the analysis has not considered all the factors potentially contributing to the defect issue,

the problem is only partially fixed and is likely to reappear. In addition, successive Paretos will often exhibit variation in rankings or types of defects as the result of day-to-day in-line variation caused by mismatched chambers, process variability or excursions, unanticipated process interactions, or random malfunctions. This instability makes identifying the true root cause of a given defect more difficult and time-consuming.

The Applied Materials FabVantage consulting group implements a unique approach in complementing the chipmaker’s top-down approach with a bottom-up approach to expedite yield ramping through optimal tool baselining and process-specific optimization.

eQuiPment mAnuFActurers’ BOttOm-uP deFect resOlutiOn

The bottom-up approach reverses the sequence of investigation in resolving yield-limiting defects. Once the top issues, and module-level and process-related performance targets are known for a specific new technology introduction, the bottom-up approach first identifies and eliminates fundamental hardware and baseline-process deficiencies to establish a “golden tool.” It progresses from there to unit process optimization, and finally to integration optimization. While these procedures are straightforward when a new product is brought online at the technology node for which it was designed, they can be more challenging when working to enhance operation of repurposed tools.

Shrinking feature dimen-sions; growing complexity of device architectures; interac-tions among new materials; and variabilities among lots, chambers, and tools are among the factors posing significant challenges in ramping advanced ICs to production-volume yield

paRtneRing With CustoMeRs to iMProVe yielD Chip design and fabrication is becoming highly complex; potential sources of yield loss are multiplying and are often obscure. This makes rapid, problem-free production ramping increasingly challenging in a fast-changing market where time is at a premium. Fabs repurposing older systems find it especially difficult to achieve desired yields, because the tools have not been optimized to meet the more stringent specifications of the new technology node. Combining the top-down resolution process typically used in fabs with the equipment manufacturer’s bottom-up optimization can streamline defect resolution and shorten the time to ramp.

Figure 1. Ramping to production is typically an arduous process.

bySuKetu

PariKh anD PatriCK

FernanDeZ

in today’s fabs. Figure 1 illustrates the typical ramp experience as compared to the smooth, efficient progress that fab operators desire. Yet even as it becomes more arduous to ramp, the imperative to accelerate it grows as shorter product lives and narrower market windows compress the time over which a new technology can generate top dollar for the producer.

The pressure to expedite ramping is especially demanding when systems are being repurposed from an earlier technology generation to a more advanced one. Generally, fabs reuse approximately 80% of their older systems. Not only must these tools be optimized to meet the specific requirements of a new process, they must be comprehensively rebaselined to a higher standard of operation.

In addition, matching performance between qualification wafers and product wafers poses a significant challenge given such factors as interactions from previous steps, topography, pattern density, and edge defects.

Expediting the yield ramp takes a partnership between the chipmaker and the equipment manufacturer. This partnership combines the chipmaker’s top-down approach to defect resolution with the manufacturer’s bottom-up method of examining hardware, process, integration, and environment to streamline root cause identification of specific defects. In this way, the full spectrum of factors affecting yield (see figure 2) can be systematically and effectively addressed.


Figure 2. Numerous factors affect yield in the manufacturing of today’s devices.

Figure 3. Complex process integrations, such as high-k metal gate, increase the potential for a wide array of yield-limiting defects.

cHiPmAKer’s tOP-dOwn deFect resOlutiOn

Chip manufacture at today’s most advanced sub-40nm nodes is significantly more demanding than at previous generations. The challenges stem from the introduction of new materials, new device and integration considerations, tighter process margins, and process interactions, all of which affect yield. Figure 3, illustrating high-k metal gate technology, shows the many factors affecting yield. Process interactions, arising primarily from the greater number of fabrication steps; gap-fill, planarization, and patterning challenges; and film interactions create more stringent

requirements for equipment and process to function precisely. These in turn necessitate intricate FDC sensor excursion control and chamber-performance matching as discussed later.

Conventional yield loss analysis in the fab employs a top-down analysis of defect issues based on Fail Pareto charts of finished wafer lots. Table 1 lists key contributors to yield loss for a typical 28nm logic process flow that could appear in a Pareto chart. Many of these derive from multiple sources. Effective, permanent resolution of each issue requires understanding of all potential causes and holistic remediation. The right side of the table shows that correcting some

issues will require complete inves-tigation of hardware, process, FDC sensors, and integration.

The conventional Fail Pareto approach to yield improvement implements failure analysis and root cause determination for each defect type appearing on the chart through an iterative approach that first examines process integration, then the unit process, and lastly hardware to determine and remedy the source of the defect. This method is effective only if resolution of the defect is permanent and the Pareto remains stable over successive process qualifications. If the analysis has not considered all the factors potentially contributing to the defect issue,

the problem is only partially fixed and is likely to reappear. In addition, successive Paretos will often exhibit variation in rankings or types of defects as the result of day-to-day in-line variation caused by mismatched chambers, process variability or excursions, unanticipated process interactions, or random malfunctions. This instability makes identifying the true root cause of a given defect more difficult and time-consuming.

The Applied Materials FabVantage consulting group implements a unique approach in complementing the chipmaker’s top-down approach with a bottom-up approach to expedite yield ramping through optimal tool baselining and process-specific optimization.

eQuiPment mAnuFActurers’ BOttOm-uP deFect resOlutiOn

The bottom-up approach reverses the sequence of investigation in resolving yield-limiting defects. Once the top issues, and module-level and process-related performance targets are known for a specific new technology introduction, the bottom-up approach first identifies and eliminates fundamental hardware and baseline-process deficiencies to establish a “golden tool.” It progresses from there to unit process optimization, and finally to integration optimization. While these procedures are straightforward when a new product is brought online at the technology node for which it was designed, they can be more challenging when working to enhance operation of repurposed tools.

Shrinking feature dimen-sions; growing complexity of device architectures; interac-tions among new materials; and variabilities among lots, chambers, and tools are among the factors posing significant challenges in ramping advanced ICs to production-volume yield

paRtneRing With CustoMeRs to iMProVe yielD Chip design and fabrication is becoming highly complex; potential sources of yield loss are multiplying and are often obscure. This makes rapid, problem-free production ramping increasingly challenging in a fast-changing market where time is at a premium. Fabs repurposing older systems find it especially difficult to achieve desired yields, because the tools have not been optimized to meet the more stringent specifications of the new technology node. Combining the top-down resolution process typically used in fabs with the equipment manufacturer’s bottom-up optimization can streamline defect resolution and shorten the time to ramp.

Figure 1. Ramping to production is typically an arduous process.

bySuKetu

PariKh anD PatriCK

FernanDeZ

in today’s fabs. Figure 1 illustrates the typical ramp experience as compared to the smooth, efficient progress that fab operators desire. Yet even as it becomes more arduous to ramp, the imperative to accelerate it grows as shorter product lives and narrower market windows compress the time over which a new technology can generate top dollar for the producer.

The pressure to expedite ramping is especially demanding when systems are being repurposed from an earlier technology generation to a more advanced one. Generally, fabs reuse approximately 80% of their older systems. Not only must these tools be optimized to meet the specific requirements of a new process, they must be comprehensively rebaselined to a higher standard of operation.

In addition, matching performance between qualification wafers and product wafers poses a significant challenge given such factors as interactions from previous steps, topography, pattern density, and edge defects.

Expediting the yield ramp takes a partnership between the chipmaker and the equipment manufacturer. This partnership combines the chipmaker’s top-down approach to defect resolution with the manufacturer’s bottom-up method of examining hardware, process, integration, and environment to streamline root cause identification of specific defects. In this way, the full spectrum of factors affecting yield (see figure 2) can be systematically and effectively addressed.


causes of yield-limiting defects. This knowledge complements the chipmaker’s expertise in the unique aspects of his process and can am-plify top-down yield improvement.

Second and more importantly, the combination of customer data on yield Pareto and equipment

maker data on tool performance provides a critically more comprehensive data set that enables efficient root cause analysis and correction of the true root cause.

The clearer picture obtained through the combined top-down

and bottom-up approach (see table 2) minimizes repeated “fire drills” that can cause significant delay in ramping when root causes of defects are obscured by higher baseline defect levels and excursions that can vary ran-domly from run to run. Instead,

yield improvement becomes an efficient, systematic process.

Once golden tools have been set up, ensuring consistent performance across the fab when fanning out the process or module can present a further challenge. Process results may match on blanket wafers but vary on product wafers. Here again, FabVantage team knowledge can facilitate a resolution. Compre-hensive understanding of system constants, calibration targets, system sensors, and which of them can modulate process drift and excursion or specific on-wafer parameters can effectively complement the chipmaker’s familiarity with process behavior to pinpoint the most appropriate path of investigation.

FabVantage consulting engagements have achieved suc-cessful results at several major advanced technology custom-ers, expediting yield improve-ment by reducing variation in process performance and defect excursions through systematic hardware, process, and integra-tion audits and remediation. These successes are founded on yield-improvement collabora-tions by FabVantage consultants

Table 2. Comparison of conventional top-down and FabVantage team approaches to yield improvement.

Figure 4. Defectivity in successive layers, accumulated through the processes sequence, can obscure the true root cause of a defective top layer.

paRtneRing With CustoMeRsto iMProVe yielD

iMPROvEMEntS • Identify top Pareto of yield losses, variations, zone-based losses.• Develop hypothesis on each top loss type and action plan to address.

• Define KPI at process level by top issues.• Incrementally tighten the specification as necessary.

• HW audit – Parts, chamber/tool conditions, facilities, system constants, PM procedure.• Implement essential and high priority findings during PM/tool down.

• Identify golden/backup tool for each critical step.• Identify trace gallery analysis.• Monitor FDC and model excursions.

• Partition/repeat cycling tests to identify issues and address.• Systematic analysis to identify and address issues, excursions.

• Develop fishbone and address issues to create robust module-level solution.

COnvEntiOnAl fABvAntAGE-CHiPMAkER tOP-DOWn APPROACH PARtnERSHiP

Top Issue Pareto Top Pareto of Yield Issues Defect Analysis Defect Analysis

Module-Level Priority Tool List Improvements Based On Each Loss

Unit Process Process Hardware Optimization Assessment/Improvements

Hardware Solution Golden/Backup Tool Set (If Issue Not Resolved By (Defects, In-line Targets) Module And Process) E3/FDC Excursion/Unif Models

Process/Cleans/Consumables/ Interaction Optimization

Module (Integration Improvements)

Partial Reduction in Complete Reduction in Overall Defectivity, Overall Defectivity, High variability Reduced variability

Table 1. Type and potential origin(s) of top yield losses in high-k metal gate fabrication.

models are developed based on individual tool performance and overall in-line defects; these are then used for ongoing monitoring of the optimized tool/process and detection of subsequent excursions.

This detailed bottom-up analysis optimizes the “health” foundation of the tool, eliminating hardware and basic process-related factors as potential root causes of defects. In other words, it reduces the “noise” level, making it easier to identify the “signal” that is the real culprit in a given situation. Once the golden tool is established, the same improvements are fanned out to the rest of the fab for yield ramp.

In the case of process modules, stabilizing yield distribution and narrowing variations from process excursions involves more than

examination of each unit system and process. Capabilities of the integrated tool set must be verified and results from blanket wafers must be seen to translate correctly to product wafers on which pattern densities and other topographical challenges might alter performance. Also, electrical parameters of the completed module must meet criteria across individual wafers, between wafers, and between chambers.

PArtnersHiP BeneFits

The FabVantage team’s approach of partnering with chip-makers in improving ramp yield offers two major benefits.

First, detailed knowledge of the hardware and its behavior across multiple systems and chemistry variations equips FabVantage consultants with les-sons learned and insights related to possible sources and root

defect count and tighten process performance.

A key step in the bottom-up approach is to establish stable, optimal baseline process perfor-mance. This is done through a process audit that investigates key process steps, gas flow, plasma terminations, plasma treatments, chamber cleaning, chamber conditioning, and interactions between a given process step and those immediately preceding and following. In addition, process signatures that cause within-wafer variation (e.g., center/edge or asymmetric) are examined and remedied as are wafer-to-wafer variations caused by differences in the service lives of the chamber, other hardware, or consumables. E3/FDC sensor trace analysis follows for priority sensors and critical steps to verify that tools replicate a predefined golden trace. Finally, sensor excursion

Establishing the golden tool involves detailed audits of the hardware, process, facility, and procedures used in periodic maintenance. Hardware audits include chamber inspections and system health checks to identify issues, such as mainframe particles, resulting from inadequate cleaning, back-side scratching, wafer slippage, heater pad wearout, and MFC bursts that create particle excursions. With the equipment manufacturer’s perspective, the FabVantage team is also sensitive to defect-generating mechanisms that can arise over time (e.g., wear and tear on moving parts and process side effects on chamber surfaces), and to the condition of moving parts over successive maintenance sessions. Further, the team can initiate tool upgrades to reduce

tOP lOSS tyPES P1 tOOlS/PROCESS HW PROCESS fDC fDC-in-linE intEGRAtED PARAMEtRiC StABility CAPABility ExCuRSiOn MEtROlOGy DEfECtS PERfORMAnCE

M2–M4 Damascene (Opens, Etch Flakes) ULK, BLOk, TiN, Litho, Etch X X X X

Extreme Edge Yield Loss (Planarity, EBR, DOF) ULK, Etch, ECP, CMP, Litho X X X X

M2–M4 Wiring (Residue, Missing Cu, Scratches, Cu Voids) Etch, B/S, ECP, CMP X X X X

Gate Pattern Defect (Over STI) HARP, CMP, Litho X X X

Replacement Gate Polish Defects (Scratches, Pits, Dishing) HDP, CMP X X X

FEOL Device Parametric Loss (Vt, I Drive) Gate, High-k, SiGe, Junction X X X

M1 Contact W Plug (Missing Cu, Opens, Post-polish Residue) W CMP, Etch Open, ECP X X X X

High-k Metal Gate Polish (Residue, Scratches) HK CMP, MG Fill, RG Module X X X X X

STI Pattern Defect Litho, Etch X

Implant Particles (Blocked Implant) Implant, Litho, Cleans X X

Gate Replacement (Stringers, Pitting) CMP, Etch X X

High-k EOT Control, Chem Oxide Cleans, RTA, ALD X X X

Contact Mask/Etch (Missing Contact, Alignment, Block Etch) Litho, Etch, Wafer Warp

Gate Pattern Etch (Incomplete Pattern, Residue, Stringers) Litho, Etch, Planarization X X

STI CMP (Scratches, Residue) Polish, Cleans X X X

BEOL (Rs, Leakage) ECP, CMP, Etch, ULK X X X X

NiSI (Rs, Leakage, Agglomeration, Missing) PVD, RTA, Cleans X X X

Metal Gate Work Function, Diffusion Barrier X X X

Contact R, Opens (Missing Plug, Poor Contact/Liner Interface) PVD, Etch Clean, W Dep X X X

SiGe Particles, Selectivity Residue Wet Etch, Cleans, EPI X X X X


causes of yield-limiting defects. This knowledge complements the chipmaker’s expertise in the unique aspects of his process and can am-plify top-down yield improvement.

Second and more importantly, the combination of customer data on yield Pareto and equipment

maker data on tool performance provides a critically more comprehensive data set that enables efficient root cause analysis and correction of the true root cause.

The clearer picture obtained through the combined top-down

and bottom-up approach (see table 2) minimizes repeated “fire drills” that can cause significant delay in ramping when root causes of defects are obscured by higher baseline defect levels and excursions that can vary ran-domly from run to run. Instead,

yield improvement becomes an efficient, systematic process.

Once golden tools have been set up, ensuring consistent performance across the fab when fanning out the process or module can present a further challenge. Process results may match on blanket wafers but vary on product wafers. Here again, FabVantage team knowledge can facilitate a resolution. Compre-hensive understanding of system constants, calibration targets, system sensors, and which of them can modulate process drift and excursion or specific on-wafer parameters can effectively complement the chipmaker’s familiarity with process behavior to pinpoint the most appropriate path of investigation.

FabVantage consulting engagements have achieved suc-cessful results at several major advanced technology custom-ers, expediting yield improve-ment by reducing variation in process performance and defect excursions through systematic hardware, process, and integra-tion audits and remediation. These successes are founded on yield-improvement collabora-tions by FabVantage consultants

Table 2. Comparison of conventional top-down and FabVantage team approaches to yield improvement.

Figure 4. Defectivity in successive layers, accumulated through the processes sequence, can obscure the true root cause of a defective top layer.


iMPROvEMEntS • Identify top Pareto of yield losses, variations, zone-based losses.• Develop hypothesis on each top loss type and action plan to address.

• Define KPI at process level by top issues.• Incrementally tighten the specification as necessary.

• HW audit – Parts, chamber/tool conditions, facilities, system constants, PM procedure.• Implement essential and high priority findings during PM/tool down.

• Identify golden/backup tool for each critical step.• Identify trace gallery analysis.• Monitor FDC and model excursions.

• Partition/repeat cycling tests to identify issues and address.• Systematic analysis to identify and address issues, excursions.

• Develop fishbone and address issues to create robust module-level solution.

COnvEntiOnAl fABvAntAGE-CHiPMAkER tOP-DOWn APPROACH PARtnERSHiP

Top Issue Pareto Top Pareto of Yield Issues Defect Analysis Defect Analysis

Module-Level Priority Tool List Improvements Based On Each Loss

Unit Process Process Hardware Optimization Assessment/Improvements

Hardware Solution Golden/Backup Tool Set (If Issue Not Resolved By (Defects, In-line Targets) Module And Process) E3/FDC Excursion/Unif Models

Process/Cleans/Consumables/ Interaction Optimization

Module (Integration Improvements)

Partial Reduction in Complete Reduction in Overall Defectivity, Overall Defectivity, High variability Reduced variability

Table 1. Type and potential origin(s) of top yield losses in high-k metal gate fabrication.

models are developed based on individual tool performance and overall in-line defects; these are then used for ongoing monitoring of the optimized tool/process and detection of subsequent excursions.

This detailed bottom-up analysis optimizes the “health” foundation of the tool, eliminating hardware and basic process-related factors as potential root causes of defects. In other words, it reduces the “noise” level, making it easier to identify the “signal” that is the real culprit in a given situation. Once the golden tool is established, the same improvements are fanned out to the rest of the fab for yield ramp.

In the case of process modules, stabilizing yield distribution and narrowing variations from process excursions involves more than

examination of each unit system and process. Capabilities of the integrated tool set must be verified and results from blanket wafers must be seen to translate correctly to product wafers on which pattern densities and other topographical challenges might alter performance. Also, electrical parameters of the completed module must meet criteria across individual wafers, between wafers, and between chambers.

PArtnersHiP BeneFits

The FabVantage team’s approach of partnering with chip-makers in improving ramp yield offers two major benefits.

First, detailed knowledge of the hardware and its behavior across multiple systems and chemistry variations equips FabVantage consultants with les-sons learned and insights related to possible sources and root

defect count and tighten process performance.

A key step in the bottom-up approach is to establish stable, optimal baseline process perfor-mance. This is done through a process audit that investigates key process steps, gas flow, plasma terminations, plasma treatments, chamber cleaning, chamber conditioning, and interactions between a given process step and those immediately preceding and following. In addition, process signatures that cause within-wafer variation (e.g., center/edge or asymmetric) are examined and remedied as are wafer-to-wafer variations caused by differences in the service lives of the chamber, other hardware, or consumables. E3/FDC sensor trace analysis follows for priority sensors and critical steps to verify that tools replicate a predefined golden trace. Finally, sensor excursion

Establishing the golden tool involves detailed audits of the hardware, process, facility, and procedures used in periodic maintenance. Hardware audits include chamber inspections and system health checks to identify issues, such as mainframe particles, resulting from inadequate cleaning, back-side scratching, wafer slippage, heater pad wearout, and MFC bursts that create particle excursions. With the equipment manufacturer’s perspective, the FabVantage team is also sensitive to defect-generating mechanisms that can arise over time (e.g., wear and tear on moving parts and process side effects on chamber surfaces), and to the condition of moving parts over successive maintenance sessions. Further, the team can initiate tool upgrades to reduce

tOP lOSS tyPES P1 tOOlS/PROCESS HW PROCESS fDC fDC-in-linE intEGRAtED PARAMEtRiC StABility CAPABility ExCuRSiOn MEtROlOGy DEfECtS PERfORMAnCE

M2–M4 Damascene (Opens, Etch Flakes) ULK, BLOk, TiN, Litho, Etch X X X X

Extreme Edge Yield Loss (Planarity, EBR, DOF) ULK, Etch, ECP, CMP, Litho X X X X

M2–M4 Wiring (Residue, Missing Cu, Scratches, Cu Voids) Etch, B/S, ECP, CMP X X X X

Gate Pattern Defect (Over STI) HARP, CMP, Litho X X X

Replacement Gate Polish Defects (Scratches, Pits, Dishing) HDP, CMP X X X

FEOL Device Parametric Loss (Vt, I Drive) Gate, High-k, SiGe, Junction X X X

M1 Contact W Plug (Missing Cu, Opens, Post-polish Residue) W CMP, Etch Open, ECP X X X X

High-k Metal Gate Polish (Residue, Scratches) HK CMP, MG Fill, RG Module X X X X X

STI Pattern Defect Litho, Etch X

Implant Particles (Blocked Implant) Implant, Litho, Cleans X X

Gate Replacement (Stringers, Pitting) CMP, Etch X X

High-k EOT Control, Chem Oxide Cleans, RTA, ALD X X X

Contact Mask/Etch (Missing Contact, Alignment, Block Etch) Litho, Etch, Wafer Warp

Gate Pattern Etch (Incomplete Pattern, Residue, Stringers) Litho, Etch, Planarization X X

STI CMP (Scratches, Residue) Polish, Cleans X X X

BEOL (Rs, Leakage) ECP, CMP, Etch, ULK X X X X

NiSI (Rs, Leakage, Agglomeration, Missing) PVD, RTA, Cleans X X X

Metal Gate Work Function, Diffusion Barrier X X X

Contact R, Opens (Missing Plug, Poor Contact/Liner Interface) PVD, Etch Clean, W Dep X X X

SiGe Particles, Selectivity Residue Wet Etch, Cleans, EPI X X X X



Business should be good next year, but 2014 may be best remembered for the manufacturing challenges facing logic and memory vendors. On the financial side, the semiconductor market for 2014 looks better than in recent years, fueled largely by an expected shortage of DRAM and NAND. Shortages equal stable or rising ASPs, and increases in capex budgets.

Objective Insights memory analyst Jim Handy said he expects 2014 to be “a shortage year all year for both NAND and DRAM. That should fuel some pretty solid growth—more than 10%—for semiconductors overall.” Although no one is on allocation just yet, Handy characterizes the current situation as a “budding shortage,” the natural outcome of 2011, when capital investments in memory “just totally shut off.”

Joanne Itow, an industry analyst at Semico Research, said strong prices for memory chips this year and next year are supporting overall growth by the chip industry. After 6–7% growth in revenues this year, Itow said that in 2014 Semico predicts even stronger growth of approximately 10%.

Gartner analyst Dean Freeman said next year is when the major logic foundries will prove their sub-20nm processes with FinFETs as the major differentiator. “Intel never missed a beat. But for the foundries, a slowdown took place at 20nm from a true Moore’s Law perspective,” Freeman said. “The transition from 28nm to a true 20nm device was delayed, and it is taking the foundries an extra year. They should have introduced a FinFET at 20nm, but they stuck with planar, not quite realizing the impact on power and performance.”

Freeman was in Taiwan when I caught up with him by phone. He said the transition to FinFETs at TSMC “is moving forward pretty well, with some decent yields, and shuttle runs for customers with good results. But introducing FinFETs in 2014 is still a manufacturing challenge, so we expect to see the real launch of FinFETs by the foundries in 2015, with significant capital spending in that year.”

Handy said the NAND memory makers face important technology choices next year. Some, including Samsung, are expected to push a fast ramp of vertical 3D NAND, while others have signaled that they will stick for the next year or two with a planar NAND architecture, but with a high-k dielectric. Either approach—3D or planar high-k—presents manufacturing challenges. Handy believes sub-20nm NAND production volumes ramps could be impacted, prolonging the memory shortage. “Companies are adopting NAND flash technology that they don’t yet know how to build.”

Handy recalled two previous transitions in DRAM technology when companies struggled to ramp volume production. “They were not able to immediately bring up a technology, so an existing shortage became a longer shortage.” But once 3D NAND production gets underway, Handy believes it will carry the industry further than some have predicted. Gartner’s Freeman noted that Samsung will employ a strategy similar to an earlier era, when IBM put its own DRAMs in IBM computers. Samsung will get a fast start on 3D NAND volumes by using them in its Samsung-branded tablets, solid-state drives (SSDs) and PCs.

While individual differences in technology roadmaps are interesting, all manufacturers need to get a good handle on these transitions. Going from planar to FinFET transistors entails daunting lithography and etch challenges, and moving from a planar NAND to stacking 24 or more vertical bit cells appears to be an equally large technology shift.

Itow said the consolidation of the leading-edge chip industry into just a few players means that they cannot afford to fail, and must invest the resources needed to succeed in any important technology transition. She noted that 6–7% revenue growth this year means the industry has about $19 billion more coming in, and 10% growth next year will boost that to more than $30 billion in new revenues.

“Our model would show a higher growth rate, but for the tentativeness of the overall world economy. Ultrabook PCs haven’t gotten a lot of traction, which also has dampened our forecast,” Itow said.

Remember those red brick walls that used to festoon the International Technology Roadmap for Semiconductors (ITRS)? Next year may be notable for companies blasting through the physical limits presented by planar transistors and moving on to volume manufacturing of vertical structures. It won’t be easy, but once accomplished it should position the chip industry well for the rest of the decade.

David Lammers is an Austin-based technology journalist.

the

last

WoR

D

DaViD laMMerS

tecHnOlOGy trAnsitiOns ShaPe 2014 outlooK

Jim Handy, Memory Analyst at Objective Insights

Joanne Itow, Industry Analyst at Semico Research

Dean Freeman, Industry Analyst at Gartner

and technologists at the Applied Materials Maydan Technology Center (MTC).

The following example of this collaboration is characteristic of the FabVantage team’s approach at customer sites. Figure 4 illus-trates issues related to BEOL defectivity. In this case, post-CMP patterning defectivity was causing yield loss. The FabVantage/MTC team suspected that the defectiv-ity resulted not only from CMP, but from multiple preceding pro-cesses and the relative stability of each process (i.e., low-k dielectric stack deposition, damascene patterning [lithography and etch]) interacting with incoming topog-raphy and defects. Besides overall planarity, the cumulative effect of defects from the most recent layer and copper wiring defects from previous layers (i.e., miss-ing metal, scratches, and slurry residue) could have a significant impact on patterning defects in the next layer to be processed.

The team’s failure analysis proceeded as follows:

1. Defect classified as metal line lithography open (having multiple potential causes and exhibiting high variability from wafer to wafer).

2. Cause identified as resist scumming.

3. Root cause identified as topographical variation (possibly local defects).

4. Solution path determined: identify critical hardware and processes; identify base defectivity/excursion rate and reduce systematically by detailed hardware inspection; corrective action/maintenance; and resolution of apparent process issues.

5. Identify short-loop tests for undesirable process interactions and address variability in defectivity of dielectric stack, patterning, and copper wiring.

6. Systematically reduce excursions in defect count by eliminating unit process excursions and setting up sensor models to establish process control limits for monitoring and reducing future excursions (see figure 5).

7. Improve scumming, identify multiple causes of stack defects.

By comparison, the conven-tional top-down approach would have started with the yield and lithography teams collaborating to improve planarization and the depth-of-field window. The variability of the incoming dama-scene stack and its underlayer would further complicate overall improvement as planarization process adjustments would impact the patterning window without eliminating the root cause of the defects.

Using the same kind of analytical sequence as detailed above, the FabVantage team has helped numerous customers systematically address hardware and process issues at the root of defects in copper wiring layers and the CVD stack. They have also extended the lithography depth of focus window by improving within-wafer planarization uniformity. This methodical approach has resulted in systematic reduction in each defect type observed by these customers, producing overall improvement in multi-layer BEOL yield, such as that illustrated in figure 6 from the collaboration with MTC.

cOnclusiOn

Ramping to production-volume yield in the shortest time possible is challenging for today’s fabs, particularly when older tools are being repurposed for a more advanced technology node. Fabs can save significant time and cost by implementing a ramp yield-improvement partnership with their equipment manufac-turer. The chipmaker brings to the partnership its top-down analysis approach and in-depth expertise in its processes. The FabVantage team brings systematic bottom-up auditing of potential sources of yield-limiting defects; broad problem-resolution expertise; and proven methodologies for yield loss analysis and remediation, en-

hancing baseline tool performance, and minimizing process variability and excursions. Working together, they eliminate the “fire drills” and delays commonly experienced, replacing them with a smooth progression from one golden tool to fab-wide fan out and achieving sustained production-volume yield with fewer preproduction runs.

Acknowledgements: The author thanks Patrick Fernandez, head of FabVantage Yield Practice, for his guidance, and Jeannette Hoffman for editorial assistance; also Mehul Naik (BEOL Integration MTC), Helen Armer, and the FabVantage yield practice team for their support.

For information contact [email protected]

Figure 5. Representative sensor model for monitoring defect excursion.

Figure 6. Systematic reduction in BEOL module defectivity achieved on in-house wafers.



Business should be good next year, but 2014 may be best remembered for the manufacturing challenges facing logic and memory vendors. On the financial side, the semiconductor market for 2014 looks better than in recent years, fueled largely by an expected shortage of DRAM and NAND. Shortages equal stable or rising ASPs, and increases in capex budgets.

Objective Insights memory analyst Jim Handy said he expects 2014 to be “a shortage year all year for both NAND and DRAM. That should fuel some pretty solid growth—more than 10%—for semiconductors overall.” Although no one is on allocation just yet, Handy characterizes the current situation as a “budding shortage,” the natural outcome of 2011, when capital investments in memory “just totally shut off.”

Joanne Itow, an industry analyst at Semico Research, said strong prices for memory chips this year and next year are supporting overall growth by the chip industry. After 6–7% growth in revenues this year, Itow said that in 2014 Semico predicts even stronger growth of approximately 10%.

Gartner analyst Dean Freeman said next year is when the major logic foundries will prove their sub-20nm processes with FinFETs as the major differentiator. “Intel never missed a beat. But for the foundries, a slowdown took place at 20nm from a true Moore’s Law perspective,” Freeman said. “The transition from 28nm to a true 20nm device was delayed, and it is taking the foundries an extra year. They should have introduced a FinFET at 20nm, but they stuck with planar, not quite realizing the impact on power and performance.”

Freeman was in Taiwan when I caught up with him by phone. He said the transition to FinFETs at TSMC “is moving forward pretty well, with some decent yields, and shuttle runs for customers with good results. But introducing FinFETs in 2014 is still a manufacturing challenge, so we expect to see the real launch of FinFETs by the foundries in 2015, with significant capital spending in that year.”

Handy said the NAND memory makers face important technology choices next year. Some, including Samsung, are expected to push a fast ramp of vertical 3D NAND, while others have signaled that they will stick for the next year or two with a planar NAND architecture, but with a high-k dielectric. Either approach—3D or planar high-k—presents manufacturing challenges. Handy believes sub-20nm NAND production volumes ramps could be impacted, prolonging the memory shortage. “Companies are adopting NAND flash technology that they don’t yet know how to build.”

Handy recalled two previous transitions in DRAM technology when companies struggled to ramp volume production. “They were not able to immediately bring up a technology, so an existing shortage became a longer shortage.” But once 3D NAND production gets underway, Handy believes it will carry the industry further than some have predicted. Gartner’s Freeman noted that Samsung will employ a strategy similar to an earlier era, when IBM put its own DRAMs in IBM computers. Samsung will get a fast start on 3D NAND volumes by using them in its Samsung-branded tablets, solid-state drives (SSDs) and PCs.

While individual differences in technology roadmaps are interesting, all manufacturers need to get a good handle on these transitions. Going from planar to FinFET transistors entails daunting lithography and etch challenges, and moving from a planar NAND to stacking 24 or more vertical bit cells appears to be an equally large technology shift.

Itow said the consolidation of the leading-edge chip industry into just a few players means that they cannot afford to fail, and must invest the resources needed to succeed in any important technology transition. She noted that 6–7% revenue growth this year means the industry has about $19 billion more coming in, and 10% growth next year will boost that to more than $30 billion in new revenues.

“Our model would show a higher growth rate, but for the tentativeness of the overall world economy. Ultrabook PCs haven’t gotten a lot of traction, which also has dampened our forecast,” Itow said.

Remember those red brick walls that used to festoon the International Technology Roadmap for Semiconductors (ITRS)? Next year may be notable for companies blasting through the physical limits presented by planar transistors and moving on to volume manufacturing of vertical structures. It won’t be easy, but once accomplished it should position the chip industry well for the rest of the decade.

David Lammers is an Austin-based technology journalist.

the

last

WoR

D

DaViD laMMerS

tecHnOlOGy trAnsitiOns ShaPe 2014 outlooK

Jim Handy, Memory Analyst at Objective Insights

Joanne Itow, Industry Analyst at Semico Research

Dean Freeman, Industry Analyst at Gartner

and technologists at the Applied Materials Maydan Technology Center (MTC).

The following example of this collaboration is characteristic of the FabVantage team’s approach at customer sites. Figure 4 illus-trates issues related to BEOL defectivity. In this case, post-CMP patterning defectivity was causing yield loss. The FabVantage/MTC team suspected that the defectiv-ity resulted not only from CMP, but from multiple preceding pro-cesses and the relative stability of each process (i.e., low-k dielectric stack deposition, damascene patterning [lithography and etch]) interacting with incoming topog-raphy and defects. Besides overall planarity, the cumulative effect of defects from the most recent layer and copper wiring defects from previous layers (i.e., miss-ing metal, scratches, and slurry residue) could have a significant impact on patterning defects in the next layer to be processed.

The team’s failure analysis proceeded as follows:

1. Defect classified as metal line lithography open (having multiple potential causes and exhibiting high variability from wafer to wafer).

2. Cause identified as resist scumming.

3. Root cause identified as topographical variation (possibly local defects).

4. Solution path determined: identify critical hardware and processes; identify base defectivity/excursion rate and reduce systematically by detailed hardware inspection; corrective action/maintenance; and resolution of apparent process issues.

5. Identify short-loop tests for undesirable process interactions and address variability in defectivity of dielectric stack, patterning, and copper wiring.

6. Systematically reduce excursions in defect count by eliminating unit process excursions and setting up sensor models to establish process control limits for monitoring and reducing future excursions (see figure 5).

7. Improve scumming, identify multiple causes of stack defects.

By comparison, the conven-tional top-down approach would have started with the yield and lithography teams collaborating to improve planarization and the depth-of-field window. The variability of the incoming dama-scene stack and its underlayer would further complicate overall improvement as planarization process adjustments would impact the patterning window without eliminating the root cause of the defects.

Using the same kind of analytical sequence as detailed above, the FabVantage team has helped numerous customers systematically address hardware and process issues at the root of defects in copper wiring layers and the CVD stack. They have also extended the lithography depth of focus window by improving within-wafer planarization uniformity. This methodical approach has resulted in systematic reduction in each defect type observed by these customers, producing overall improvement in multi-layer BEOL yield, such as that illustrated in figure 6 from the collaboration with MTC.

cOnclusiOn

Ramping to production-volume yield in the shortest time possible is challenging for today’s fabs, particularly when older tools are being repurposed for a more advanced technology node. Fabs can save significant time and cost by implementing a ramp yield-improvement partnership with their equipment manufac-turer. The chipmaker brings to the partnership its top-down analysis approach and in-depth expertise in its processes. The FabVantage team brings systematic bottom-up auditing of potential sources of yield-limiting defects; broad problem-resolution expertise; and proven methodologies for yield loss analysis and remediation, en-

hancing baseline tool performance, and minimizing process variability and excursions. Working together, they eliminate the “fire drills” and delays commonly experienced, replacing them with a smooth progression from one golden tool to fab-wide fan out and achieving sustained production-volume yield with fewer preproduction runs.

Acknowledgements: The author thanks Patrick Fernandez, head of FabVantage Yield Practice, for his guidance, and Jeannette Hoffman for editorial assistance; also Mehul Naik (BEOL Integration MTC), Helen Armer, and the FabVantage yield practice team for their support.

For information contact [email protected]

Figure 5. Representative sensor model for monitoring defect excursion.

Figure 6. Systematic reduction in BEOL module defectivity achieved on in-house wafers.


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V8/Issue 2/2013 2 6 32 - Applied Materials