Verilog Basic Programs

12/01/2015

DATAFLOW & STRUCTURAL MODELING

1. Full Adder

module ha (input a, b, output sum, carry);

xor g1 (sum, a, b);

and g2 (carry, a, b);

endmodule

a. Using only Half Adders (Position / Ordered Association)

module fa_ha (input a, b, cin, output sum, carry);

wire w1,w2,w3;

ha HA1 (a, b, w1, w3),

HA2(cin, w1, sum, w2),

HA3(w2, w3, carry,);

endmodule

b. Using only Half Adders (Named Association)

module fa_ha (input a, b, cin, output sum, carry);

wire w1,w2,w3;

ha HA1 (.a(a), .b(b), .sum(w1), .carry(w3)),

HA2 (.a(cin), .b(w1), .sum(sum), .carry(w2)),

HA3 (.a(w2), .b(w3), .sum(carry), .carry());

endmodule

Test Bench

module fa_tb;

reg a,b,cin;

wire sum,carry;

fa f1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));

initial

begin

a=0;b=0;cin=0;

$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);

#5 cin = 1;

#5 b = 1;

#5 cin = 0;

#5 a = 1;

#5 cin = 1;

#5 b = 0;

#5 cin = 0;

end

endmodule

2. Full Subtractor

module hs (input a,b, output d, bo);

wire w1;

not g1 (w1, a);

xor g2 (d, a ,b);

and g3 (bo, w1 ,b);

endmodule

a. Using only Half Subtractor (Position / Ordered Association)

module fs_hs (input a, b, c, output diff, borrow);

wire w1,w2,w3;

hs HS1(a, b, w1, w3),

HS2(w1, c, diff, w2),

HS3(w2, w3, borrow, );

endmodule

b. Using only Half Subtractor (Named Association)

module fs_hs (input a, b, c, output diff, borrow);

wire w1,w2,w3;

hs HS1(.a(a), .b(b), .d(w1), .bo(w3)),

HS2(.a(w1), .b(c), .d(diff), .bo(w2)),

HS3(.a(w2),.b(w3),.d(borrow),.bo());

endmodule

3. 8 : 1 Multiplexer using only 2 : 1 Multiplexers

a. Using only vectors

module mux_2_1(input [1:0]i, input s, output y);

assign y = s ? i[1] : i[0];

endmodule

module mux_8_1 (input [7:0]i, input [2:0]s, output y);

wire [5:0]w;

mux_2_1 m1 (.i(i[1:0]), .s(s[0]), .y(w[0])),

m2 (.i(i[3:2]), .s(s[0]), .y(w[1])),

m3 (.i(i[5:4]), .s(s[0]), .y(w[2])),

m4 (.i(i[7:6]), .s(s[0]), .y(w[3])),

m5 (.i(w[1:0]), .s(s[1]), .y(w[4])),

m6 (.i(w[3:2]), .s(s[1]), .y(w[5])),

m7 (.i(w[5:4]), .s(s[2]), .y(y));

endmodule

b. Using scalars & Vectors

module mux_2 (input a, b, s, output y);

assign y=s ? b : a;

endmodule

module mux_8 (input[7:0]i, input[2:0]s, output y);

wire y1,y2,y3,y4,y5,y6;

mux_2 m1 (.a(i[0]), .b(i[1]), .s(s[0]), .y(y1)),

m2 (.a(i[2]), .b(i[3]), .s(s[0]), .y(y2)),

m3 (.a(i[4]), .b(i[5]), .s(s[0]), .y(y3)),

m4 (.a(i[6]), .b(i[7]), .s(s[0]), .y(y4)),

m5 (.a(y1), .b(y2), .s(s[1]), .y(y5)),

m6 (.a(y3), .b(y4), .s(s[1]), .y(y6)),

m7 (.a(y5), .b(y6), .s(s[2]), .y(y));

endmodule

Test Bench

4. 4 : 16 Decoder using 3 : 8 Decoder

3 : 8 Decoder

module dec_3_8 (input a, b, c, en, output [7:0]y);

wire w1,w2,w3;

not g9 (w1, a),

g10 (w2, b),

g11 (w3 ,c);

and g1 (y[0], w1, w2, w3, en),

g2 (y[1], w1, w2, c, en),

g3 (y[2], w1, b, w3, en),

g4 (y[3], w1, b, c, en),

g5 (y[4], a, w2, w3, en),

g6 (y[5], a, w2, c, en),

g7 (y[6], a, b, w3, en),

g8 (y[7], a, b, c, en);

endmodule

4 : 16 Decoder

module dec_4_16 (input a, b, c, d, output [15:0]y);

wire w1;

not g1(w1,a);

dec_3_8 d1 (.a(b), .b(c), .c(d), .en(w1), .y(y[7:0])),

d2 (.a(b), .b(c), .c(d), .en(a), .y(y[15:8]));

endmodule

5. BCD ADDER

module bcd_adder(input [3:0]a,b, input cin, output [3:0]s, output co);

wire w0,w1,w2,w3,w4,w5,w6,w7;

assign cin = 0;

fa_4bit fa1 (.a(a), .b(b), .cin(cin), .s({w3,w2,w1,w0}), .co(w4));

and g1(w5, w1, w3),

g2(w6, w2, w3);

or g3(w7, w4, w5, w6);

fa_4bit fa2 (.a({w3,w2,w1,w0}), .b({cin,w7,w7,cin}), .cin(cin), .s(s), .co());

assign co = w7;

endmodule

Test bench

module bcd_adder_tb;

reg [3:0]a,b;

reg cin;

wire [3:0]s;

wire co;

bcd_adder fa1(.a(a),.b(b),.cin(cin),.s(s),.co(co));

initial

begin

a = 4'b0000;b = 4'b0000;cin = 0;

$monitor("a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,s,co);

#5 b = 4'b0001; a = 4'b1001;

#5 b = 4'b0010;

#5 b = 4'b0011;

#5 b = 4'b1001;

#5 b = 4'b0010;

#5 b = 4'b0110;

#5 b = 4'b0011; a = 4'b0111;

#5 a = 4'b0111;

#5 b = 4'b0110;

#5 b = 4'b1000;

#5 b = 4'b0010;

#5 b = 4'b1001;

end

endmodule

6. 4 – bit Parallel Multiplier

module mult4bit (input [3:0]x, y, output [7:0]m);

wire [3:0]p1,p2,p3,p4,s1,s2;

wire c1,c2;

assign p1 = x & {4{y[0]}},

p2 = x & {4{y[1]}};

fa_4bit fa1(.a({1'b0,p1[3:1]}), .b(p2), .cin(1'b0), .s(s1), .co(c1));

assign p3 = x & {4{y[2]}};

fa_4bit fa2(.a({c1,s1[3:1]}), .b(p3), .cin(1'b0), .s(s2), .co(c2));

assign p4 = x & {4{y[3]}};

fa_4bit fa3(.a({c2,s2[3:1]}),.b(p4),.cin(1'b0),.s(m[6:3]),.co(m[7]));

assign m[0] = p1[0],

m[1] = s1[0],

m[2] = s2[0];

endmodule

Test bench

module mult4bit_tb;

reg [3:0]x,y;

wire [7:0]m;

mult4bit mul1(.x(x), .y(y), .m(m));

initial

begin

x = 4'b0000;y = 4'b0000;

$monitor("x=%b, y=%b, m=%b",x,y,m);

#5 x = 4'b1001; y = 4'b1001;

#5 x = 4'b0010;

#5 x = 4'b0011;

#5 x = 4'b1001;

#5 x = 4'b0010;

#5 x = 4'b1110;

#5 x = 4'b0011; y = 4'b0111;

#5 x = 4'b0111;

#5 x = 4'b0110;

#5 x = 4'b1011;

#5 x = 4'b0010;

#5 x = 4'b1001;

#5 x = 4'b0011; y = 4'b1111;

#5 x = 4'b0111;

#5 x = 4'b0110;

#5 x = 4'b1011;

#5 x = 4'b1010;

#5 x = 4'b1001;

end

13/01/2015

BEHAVIORAL MODELING

1. Examples to understand the execution of statements in procedural

blocks

a. Test 3

module test3;

initial

begin

#0 $display("Block 1 St 1");



end

initial

begin

$display("Block 2 St 1");



end

endmodule

Output

Block 2 St 1

Block 1 St 1

Block 2 St 2

Block 1 St 2

Block 1 St 3

Block 2 St 3

module test3;

initial

begin




end

initial

begin




end

endmodule

Output

Block 2 St 1

Block 1 St 1

Block 1 St 2

Block 2 St 2

Block 1 St 3

Block 2 St 3

b. Test 4

module test4;

integer a,b,c,d,e,f;

initial

module test4;

integer a,b,c,d,e,f;

initial

begin

a = 20;

$display("%d", a);

#5 b = 50;

$display("%d",b);

end

initial

begin

#10 c = 55;

$display("%d",c);

#15 d = 70;

$display("%d",d);

end

initial

begin

#20 e = 75;

$display("%d",e);

#45 f = 80;

$display("%d",f);

end

endmodule

Output

a = 20

b = 50

c = 55

e = 75

d = 70

f = 80

begin

a = 20;

$display("%d", a);

#5 b = 50;

$display("%d",b);

end

initial

begin

#10 c = 55;

$display("%d",c);

#15 d = 70;

$display("%d",d);

end

initial

begin

e = 75;

$display("%d",e);

#5 f = 80;

$display("%d",f);

end

endmodule

Output

a = 20

e = 75

b = 50

f = 80

c = 55

d = 70

14 / 01 / 2015

2. 2:1 Multiplexer

module mux2to1_bh(input a,b,sel, output reg y);

always@(a,b,sel)

begin

if(sel)

y = b;

else

y = a;

end

endmodule

testbench

module mux_2_tb;

reg a,b,s;

wire y;

mux_2 m1(.a(a),.b(b),.s(s),.y(y));

initial

begin

a=0;b=0;s=0;

$monitor("a=%b,b=%b,s=%b,y=%b",a,b,s,y);

#5 s = 1;

#5 a = 1;

#5 s = 0;

#5 b = 1;

#5 s = 1;

#5 a = 0;

#5 s = 0;

end

endmodule

3. Full Adder

a. Using if else ladder ( Blocking Assignment Statements )

module fa_bh4(input a,b,cin, output reg sum,carry);

always@(a,b,cin)

begin

if(a==0 && b==0 && cin==0)

begin

sum = 0;

carry = 0;

end

else if(a==0 && b==0 && cin==1)

begin

sum = 1;

carry = 0;

end

else if(a==0 && b==1 && cin==0)

begin

sum = 1;

carry = 0;

end

else if(a==0 && b==1 && cin==1)

begin

sum = 0;

carry = 1;

end

else if(a==1 && b==0 && cin==0)

begin

sum = 1;

carry = 0;

end

else if(a==1 && b==0 && cin==1)

begin

sum = 0;

carry = 1;

end

else if(a==1 && b==1 && cin==0)

begin

sum = 0;

carry = 1;

end

else

begin

sum = 1;

carry = 1;

end

end

endmodule

b. Using case statement ( Blocking Assignment Statements )


always@(a,b,cin)

begin

case({a,b,cin})

3'b000:begin

sum = 0; carry = 0;

end

3'b001:begin

sum = 1; carry = 0;

end

3'b010:begin

sum = 1; carry = 0;

end

3'b011:begin

sum = 0; carry = 1;

end

3'b100:begin

sum = 1; carry = 0;

end

3'b101:begin

sum = 0; carry = 1;

end

3'b110:begin

sum = 0; carry = 1;

end

3'b111:begin

sum = 1; carry = 1;

end

endcase

end

endmodule

c. Using if else ladder and operators ( Blocking Assignment Statements )


always@(a,b,cin)

begin

if(!a & !b & !cin)

begin

sum = 0;

carry = 0;

end

else if(!a & !b & cin)

begin

sum = 1;

carry = 0;

end

else if(!a & b & !cin)

begin

sum = 1;

carry = 0;

end

else if(!a & b & cin)

begin

sum = 0;

carry = 1;

end

else if(a & !b & !cin)

begin

sum = 1;

carry = 0;

end

else if(a & !b & cin)

begin

sum = 0;

carry = 1;

end

else if(a & b & !cin)

begin

sum = 0;

carry = 1;

end

else

begin

sum = 1;

carry = 1;

end

end

endmodule

Test Bench

module fa_tb;

reg a,b,cin;

wire sum,carry;

fa f1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));

initial

begin

a=0;b=0;cin=0;

$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);

#5 cin = 1;

#5 b = 1;

#5 cin = 0;

#5 a = 1;

#5 cin = 1;

#5 b = 0;

#5 cin = 0;

end

endmodule

4. 4 : 1 Multiplexer

a. Using case statement

module mux4to1_bh_case(input a,b,c,d, input [1:0]s, output reg y);

always @(a,b,c,d,s)

begin

case(s)

2'b00:y=a;

2'b01:y=b;

2'b10:y=c;

default:y=d;

endcase

end

endmodule

Testbench

module mux4to1_bh_tb;

reg a,b,c,d;

reg [1:0]s;

wire y;

mux4to1_bh_case m1(.a(a),.b(b),.c(c),.d(d),.s(s),.y(y));

initial

begin

a=0;b=0;c=0;d=0;s=2'b00;

$monitor("a=%b, b=%b, c=%d, d=%d, s=%b, y=%b",a,b,c,d,s,y);

#5 a = 1;

#5 s = 2'b01;

#5 b = 1;a = 0; d = 1;

#5 s = 2'b10;

#5 b = 0;

#5 c = 1;

#5 c = 0;b = 1;

#5 s = 2'b11;

#5 a = 1;

#5 b = 0;d = 0;

end

endmodule

5. 3 : 8 Decoder

a. Using if else statement

module dec3to8_if(input [2:0]a, output reg [7:0]y);

always@(a)

begin

if(a==3'b000)

y = {7'b0,1'b1};

else if(a==3'b001)

y = {6'b0,1'b1,1'b0};

else if(a==3'b010)

y = {5'b0,1'b1,2'b0};

else if(a==3'b011)

y = {4'b0,1'b1,3'b0};

else if(a==3'b100)

y = {3'b0,1'b1,4'b0};

else if(a==3'b101)

y = {2'b0,1'b1,5'b0};

else if(a==3'b110)

y = {1'b0,1'b1,6'b0};

else

y = {1'b1,7'b0};

end

endmodule

b. Using case statement

module dec3to8_case(input [2:0]a, output reg [7:0]y);

always@(a)

begin

case(a)

3'b000:y=8'b00000001;

3'b001:y=8'b00000010;

3'b010:y=8'b00000100;

3'b011:y=8'b00001000;

3'b100:y=8'b00010000;

3'b101:y=8'b00100000;

3'b110:y=8'b01000000;

3'b111:y=8'b10000000;

default:y=8'b00000000;

endcase

end

endmodule

Test Bench

module dec3to8_bh_tb;

reg [2:0]a;

wire [7:0]y;

dec3to8_if dec(.a(a),.y(y));

initial

begin

a = 3'b000;

$monitor("a = %b, y = %b",a,y);

#5 a = 3'b001;

#5 a = 3'b010;

#5 a = 3'b011;

#5 a = 3'b100;

#5 a = 3'b101;

#5 a = 3'b110;

#5 a = 3'b111;

end

endmodule

6. 8 : 3 Encoder


module enc8to3_if(input [7:0]a, output reg [2:0]y);

always@(a)

begin

if(a==8'b00000001)

y = 3'b000;

else if(a==8'b00000010)

y = 3'b001;

else if(a==8'b00000100)

y = 3'b010;

else if(a==8'b00001000)

y = 3'b011;

else if(a==8'b00010000)

y = 3'b100;

else if(a==8'b00100000)

y = 3'b101;

else if(a==8'b01000000)

y = 3'b110;

else if(a==8'b10000000)

y = 3'b111;

else

y = 3'bx;

end

endmodule

b. Using Case statement

module enc8to3_case(input [7:0]a, output reg [2:0]y);

always@(a)

begin

case(a)

8'b00000001:y = 3'b000;

8'b00000010:y = 3'b001;

8'b00000100:y = 3'b010;

8'b00001000:y = 3'b011;

8'b00010000:y = 3'b100;

8'b00100000:y = 3'b101;

8'b01000000:y = 3'b110;

8'b10000000:y = 3'b111;

default:y = 3'bxxx;

endcase

end

endmodule

Test Bench

module enc8to3_bh_tb;

reg [7:0]a;

wire [2:0]y;

enc8to3_if enc(.a(a),.y(y));

initial

begin

a = 8'b00000000;


#5 a = 8'b00000001;

#5 a = 8'b00000010;

#5 a = 8'b00000100;

#5 a = 8'b00001000;

#5 a = 8'b00010000;

#5 a = 8'b00100000;

#5 a = 8'b01000000;

#5 a = 8'b10000000;

end

endmodule

7. BCD to 7 Segment display Decoder


module bcdto7seg_if(input [3:0]a, output reg [6:0]y);

always@(a)

begin

if(a == 4'b0000)

y = 7'b1111110;

else if(a == 4'b0001)

y = 7'b0110000;

else if(a == 4'b0010)

y = 7'b1101101;

else if(a == 4'b0011)

y = 7'b1111001;

else if(a == 4'b0100)

y = 7'b0110011;

else if(a == 4'b0101)

y = 7'b1011010;

else if(a == 4'b0110)

y = 7'b1011111;

else if(a == 4'b0111)

y = 7'b1110000;

else if(a == 4'b1000)

y = 7'b1111111;

else if(a == 4'b1001)

y = 7'b1111011;

else

y = 7'b0;

end

endmodule

b. Using case Statement

module bcdto7seg_case(input [3:0]a, output reg [6:0]y);

always@(a)

begin

case(a)

4'b0000:y = 7'b1111110;

4'b0001:y = 7'b0110000;

4'b0010:y = 7'b1101101;

4'b0011:y = 7'b1111001;

4'b0100:y = 7'b0110011;

4'b0101:y = 7'b1011010;

4'b0110:y = 7'b1011111;

4'b0111:y = 7'b1110000;

4'b1000:y = 7'b1111111;

4'b1001:y = 7'b1111011;

default:y = 7'b0;

endcase

end

endmodule

Test Bench

module bcdto7seg_tb;

reg [3:0]a;

wire [6:0]y;

bcdto7seg_case bcddec(.a(a),.y(y));

initial

begin

a = 4'b0000;


#5 a=4'b0001;

#5 a=4'b0010;

#5 a=4'b0011;

#5 a=4'b0100;

#5 a=4'b1111;

#5 a=4'b0101;

#5 a=4'b0110;

#5 a=4'b0111;

#5 a=4'b1010;

#5 a=4'b1011;

#5 a=4'b1000;

#5 a=4'b1101;

#5 a=4'b1001;

end

endmodule

19 / 01 / 2015

8. 4 – Bit Asynchronous Counter starting from latch

SR Latch using NAND gates

module srlatch(input s,r,en, output q,qbar);

wire w1,w2,w3,w4;

nand g1(w1,s,en),

g2(w2,r,en),

g3(w3,w1,w4),

g4(w4,w2,w3);

assign q = w3,

qbar = w4;

endmodule

D Latch from SR Latch

module dlatch(input d,en, output q,qbar);

wire w5;

not g5(w5,d);

srlatch d_latch(.s(d),.r(w5),.en(en),.q(q),.qbar(qbar));

endmodule

D Flipflop using 2 D latches

module dff_ms(input d,clk, output q,qbar);

wire w1,w2;

not g1(w1,clk);

dlatch d1(.d(d),.en(clk),.q(w2),.qbar()),

d2(.d(w2),.en(w1),.q(q),.qbar(qbar));

endmodule

4 – bit Asynchronous Up counter using D flipflop

module cntr_dff_struct(input clk,d,rst, output[3:0]q);

dff_arst d1(.d(~q[0]),.clk(clk),.q(q[0]),.rst(rst)),

d2(.d(~q[1]),.clk(~q[0]),.q(q[1]),.rst(rst)),

d3(.d(~q[2]),.clk(~q[1]),.q(q[2]),.rst(rst)),

d4(.d(~q[3]),.clk(~q[2]),.q(q[3]),.rst(rst));

endmodule

Testbench

module cntr_dff_struct_tb;

reg d,clk,rst;

wire [3:0]q;

cntr_dff_struct d1(.d(d),.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;

$monitor("clk=%b, rst=%b, d=%b, q=%b", clk,rst,d,q);

#20 rst = 1;

#200 rst = 0;

#30 rst = 1;

end

endmodule

20 / 01 / 2015

9. Race Around Condition

Blocking Statements

module test_race(input clk);

reg [3:0]a,b;

initial

begin

Blocking statements


reg [3:0]a,b;

initial

begin

a = 4'b1101;

b = 4'b1110;

end

always@(posedge clk)

begin

a = b;

b = a;

end

endmodule

Output

a = 4’b1110

b = 4’b1110

a = 4'b1101;

b = 4'b1110;

end


a = b;


b = a;

end

endmodule

Output

a = 4’b1110

b = 4’b1110

Non Blocking statements


reg [3:0]a,b;

initial

begin

a = 4'b1101;

b = 4'b1110;

end


a <= b;

b <= a;

end

endmodule

Output

a = 4’b1110

b = 4’b1101

Non Blocking statements


reg [3:0]a,b;

initial

begin

a = 4'b1101;

b = 4'b1110;

end


a <= b;


b <= a;

end

endmodule

Output

a = 4’b1110

b = 4’b1101

10. COUNTERS

a. 4 – bit synchronous counter with synchronous resetmodule cntr4bit_syn_srst(input clk,rst, output reg [3:0]q); always@(posedge clk) begin if(!rst) q <= 4'b0000; else q <= q+1; end endmoduleTest Benchmodule cntr4bit_syn_tb;

reg clk,rst;

wire [3:0]q;

cntr4bit_syn_srst cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;

$monitor("clk=%b, rst=%b, q=%b", clk,rst,q);

#32 rst = 1;

//#54 rst = 0;

//#80 rst = 0;

//#5 rst = 1;

end

endmodule

b. n – bit synchronous counter with synchronous reset

module cntrnbit_syn_srst #(parameter n = 8)

(input clk,rst, output reg [n-1:0]q);


begin

if(!rst)

q <= {n{1'b0}};

else

q <= q+1;

end

endmodule

Test Bench

module cntrnbit_syn_tb #(parameter n = 8);

reg clk,rst;

wire [n-1:0]q;

cntrnbit_syn_srst cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#32 rst = 1;

#154 rst = 0;

#13 rst = 1;

#180 rst = 0;

#45 rst = 1;

end

endmodule

c. n – bit synchronous UPDOWN counter with asynchronous reset

module cntrnbit_ud_syn_arst #(parameter n = 8)

(input clk,rst,updown, output reg [n-1:0]q);

always@(posedge clk, negedge rst)

begin

if(!rst)

q <= {n{1'b0}};

else if(updown)

q <= q+1;

else

q <= q-1;

end

endmodule

Test Bench

module cntrnbit_ud_syn_tb #(parameter n = 8);

reg clk,rst,updown;

wire [n-1:0]q;

cntrnbit_ud_syn_arst cntr(.clk(clk),.rst(rst),.updown(updown),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;updown = 1;

$monitor("clk=%b, rst=%b, updown=%b, q=%b", clk,rst,updown,q);

#32 rst = 1;

#154 rst = 0;

#25 rst = 1;

#17 updown = 0;

#80 rst = 0;

#5 rst = 1;

#18 updown = 1;

#170 rst = 0;

#17 rst = 1;

end

endmodule

d. 4 – bit synchronous UPDOWN counter with synchronous reset

module cntr4bit_ud_syn_srst(input clk,rst,updown, output reg [3:0]q);


begin

if(!rst)

q <= 4'b0000;

else if(updown)

q <= q+1;

else

q <= q-1;

end

endmodule

Test Bench

module cntr4bit_ud_syn_tb;

reg clk,rst,updown;

wire [3:0]q;

cntr4bit_ud_syn_srst cntr(.clk(clk),.rst(rst),.updown(updown),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;updown = 1;


#32 rst = 1;

#54 rst = 0;

#5 rst = 1;

#17 updown = 0;

#80 rst = 0;

#5 rst = 1;

#18 updown = 1;

#70 rst = 0;

#17 rst = 1;

end

endmodule

e. n – bit synchronous UPDOWN counter with synchronous reset

module cntrnbit_ud_syn_srst #(parameter n = 8)

(input clk,rst,updown, output reg [n-1:0]q);


begin

if(!rst)

q <= {n{1'b0}};

else if(updown)

q <= q+1;

else

q <= q-1;

end

endmodule

Test Bench

module cntrnbit_ud_syn_tb #(parameter n = 8);

reg clk,rst,updown;

wire [n-1:0]q;

cntrnbit_ud_syn_srst cntr(.clk(clk),.rst(rst),.updown(updown),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;updown = 1;


#32 rst = 1;

#154 rst = 0;

#25 rst = 1;

#17 updown = 0;

#80 rst = 0;

#5 rst = 1;

#18 updown = 1;

#170 rst = 0;

#17 rst = 1;

end

endmodule

21 / 01 / 2015

11. TYPES OF TESTBENCHES

FULL ADDERa. File I / O Based Test Bench

module fa_tb_file; reg a,b,cin; wire sum,carry; integer f1; fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry)); initial //f1 = $fopen("fa_lin.xls"); f1 = $fopen("fa_lin.txt"); initial begin a=0;b=0;cin=0; $fmonitor(f1,$time,"a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry); #5 cin = 1; #5 b = 1; #5 cin = 0; #5 a = 1; #5 cin = 1; #5 b = 0; #5 cin = 0; endendmodule

b. Iterative Loop Based Test Bench

module fa_tb_loop;

reg a,b,cin; wire sum,carry; integer f1; fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry)); initial f1 = $fopen("fa_loop.txt"); initial begin {a,b,cin} = 3'b000; repeat(7) begin {a,b,cin} = {a,b,cin} + 3'b001; #10 $fdisplay(f1,$time,"a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,sum,carry); end end endmodule

c. Test Bench using Randomization

module fa_tb_rand; reg a,b,cin; wire sum,carry; fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry)); initial begin repeat(10) begin a = $random(); b = $random(); cin = $random(); #5 $display("a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,sum,carry); end end endmodule

d. Self Checking Test Bench

module fa_tb_self; reg a,b,cin; wire sum,carry; integer f1; fa_bh1 fa1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry)); initial

f1 = $fopen("fa_self1.txt"); initial begin {a,b,cin} = 3'b000; repeat(7) begin {a,b,cin} = {a,b,cin} + 3'b001; #10 $fdisplay(f1,$time,"a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,sum,carry); if((a+b+cin)!={carry,sum}) $fdisplay(f1,$time,"error"); else $fdisplay(f1,$time,"success"); end end endmodule

12. PRIORITY ENCODER

i ) Without Default conditions

a. Using Conditional Statement

module prienc_df(input [7:0]a, output [2:0]y); assign y = (a[0]==1'b1)? 3'b000: (a[1]==1'b1)? 3'b001: (a[2]==1'b1)? 3'b010: (a[3]==1'b1)? 3'b011: (a[4]==1'b1)? 3'b100: (a[5]==1'b1)? 3'b101: (a[6]==1'b1)? 3'b110: 3'b111;endmodule

b. Using if else statement

module prienc_if(input [7:0]a, output reg [2:0]y); always@(a) begin if(a[0] == 1'b1) y = 3'b000; else if(a[1] == 1'b1) y = 3'b001; else if(a[2] == 1'b1) y = 3'b010; else if(a[3] == 1'b1) y = 3'b011; else if(a[4] == 1'b1) y = 3'b100; else if(a[5] == 1'b1) y = 3'b101; else if(a[6] == 1'b1) y = 3'b110; else y = 3'b111; end endmodule

c. Using Casex Statement

module prienc_case(input [7:0]a, output reg [2:0]y); always@(a) begin casex (a) 8'bxxxxxxx1: y = 3'b000; 8'bxxxxxx10: y = 3'b001; 8'bxxxxx100: y = 3'b010; 8'bxxxx1000: y = 3'b011; 8'bxxx10000: y = 3'b100; 8'bxx100000: y = 3'b101;

8'bx1000000: y = 3'b110; 8'b10000000: y = 3'b111; endcase endendmodule

ii ) with Default Case

d. Using Conditional operator

module prienc_df1(input [7:0]a, output [2:0]y); assign y = (a[0]==1'b1)? 3'b000: (a[1]==1'b1)? 3'b001: (a[2]==1'b1)? 3'b010: (a[3]==1'b1)? 3'b011: (a[4]==1'b1)? 3'b100: (a[5]==1'b1)? 3'b101: (a[6]==1'b1)? 3'b110: (a[7]==1'b1)? 3'b111: 3'bx;endmodule

e. Using if else statementmodule prienc_if1(input [7:0]a, output reg [2:0]y);always@(a) begin if(a[0] == 1'b1) y = 3'b000; else if(a[1] == 1'b1)

y = 3'b001; else if(a[2] == 1'b1) y = 3'b010; else if(a[3] == 1'b1) y = 3'b011; else if(a[4] == 1'b1) y = 3'b100; else if(a[5] == 1'b1) y = 3'b101; else if(a[6] == 1'b1) y = 3'b110; else if(a[7] == 1'b1) y = 3'b111; else y = 3'bx; end endmodule

f. Using casex statement

module prienc_case1(input [7:0]a, output reg [2:0]y); always@(a) begin casex (a) 8'bxxxxxxx1: y = 3'b000; 8'bxxxxxx10: y = 3'b001; 8'bxxxxx100: y = 3'b010; 8'bxxxx1000: y = 3'b011; 8'bxxx10000: y = 3'b100; 8'bxx100000: y = 3'b101; 8'bx1000000: y = 3'b110; 8'b10000000: y = 3'b111; default: y = 3'bx; endcase

endendmodule

Test Benchmodule prienc_tb; reg [7:0]a; wire [2:0]y; integer f1; //prienc_df e(.a(a),.y(y)); // for dataflow //prienc_if e(.a(a),.y(y)); // for if else prienc_case e(.a(a),.y(y)); initial //f1 = $fopen("prienc_df.txt"); //f1 = $fopen("prienc_if.txt"); f1 = $fopen("prienc_case.txt"); initial begin a = 8'b1; $fmonitor(f1,$time,"a=%b,y=%b",a,y); #10 a = 8'b0; #10 a = 8'bxxxxxxxx; #10 a = 8'bzzzzzzzz; #10 a = 8'b11110000; #10 a = 8'bxxxxxx1x; #10 a = 8'bzzz1zzzx; #10 a = 8'bzzz1zzzz; #10 a = 8'bzzz1z10x; #10 a = 8'b111100xx; #10 a = 8'b00000010; #10 a = 8'bzzz1x00z; #10 a = 8'b1z1x0zx0; #10 a = 8'b1z1x0xx0; #10 a = 8'b1z1x00x0; #10 a = 8'b1z1x01x0;

#10 a = 8'b1z100xx0; #10 a = 8'b1z10000x; #10 a = 8'b1z1z000x; #10 a = 8'b000000x0; #10 a = 8'b100000x0; #10 a = 8'b000001x0; endendmodule

22 / 01 / 2015

13. n – bit Asynchronous Up counter using Generate For loop statement

Asynchronous D FF

module dff_arst(input clk,rst,d, output reg q);


begin

if(!rst)

q <= 1'b0;

else

q <= d;

end

endmodule

Asynchronous Up Countermodule cntrnbit_asyn_gen #(parameter n = 4)

(input clk,rst, output [n-1:0]q);

genvar i;

generate

for(i=0;i<n;i=i+1)

begin:f1

if(i==0)

dff_arst c1(.clk(clk),.rst(rst),.d(~q[i]),.q(q[i]));

else

dff_arst c2(.clk(~q[i-1]),.rst(rst),.d(~q[i]),.q(q[i]));

end

endgenerate

endmodule

Test Bench

module cntrnbit_async_tb #(parameter n = 4);

reg clk,rst;

wire [n-1:0]q;

cntrnbit_asyn_gen cntr(.clk(clk),.rst(rst),.q(q)); //for asynchronous counter

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#5 rst = 1;

#154 rst = 0;

#13 rst = 1;

#180 rst = 0;

#45 rst = 1;

end

endmodule

14. n - bit Full Adder Using Behavioral For loop statement

module fa_nbit_for #(parameter n=8)(input [n-1:0]a,b, input cin, output reg [n-1:0]s, output

reg co);

reg [n:0]c;

integer i;

always@(a,b,cin)

begin

c[0] = cin;

for(i=0;i<n;i=i+1)

begin

{c[i+1],s[i]} = a[i]+b[i]+c[i];

end

co = c[n];

end

endmodule

Test Bench

module nbitfa_tb #(parameter n=8);

reg [n-1:0]a,b;

reg cin;

wire [n-1:0]s;

wire co;

integer f2;

fa_nbit_for f1(.a(a),.b(b),.cin(cin),.s(s),.co(co));

initial

f2 = $fopen("nbit_fa1.txt");

initial

begin

repeat(20)

begin

cin = $random();

a = $random(); b = $random();

#5 $fdisplay(f2,$time,"a=%d,b=%d,cin=%d,s=%d,co=%d",a,b,cin,s,co);

end

end

endmodule

15. 8 : 1 MUX using Behavioral For loop statement

module mux8to1_for(input [7:0]a, input [2:0]sel, output reg y);

integer i;

always@(a,sel)

begin

for(i=0;i<8;i=i+1)

begin

if(i==sel)

y = a[i];

end

end

endmodule

Testbench

module mux8to1_for_tb;

reg [7:0]a;

reg [2:0]sel;

wire y;

mux8to1_for f1(.a(a),.sel(sel),.y(y));

initial

begin

a = 8'b11110000; sel = 3'b000;

$monitor("a=%b,sel=%d,y=%b",a,sel,y);

#10 sel = 3'b001;

#10 sel = 3'b00x;

#10 sel = 3'b110;

#10 sel = 3'b00x;

#10 sel = 3'b100;

#10 sel = 3'b010;

#10 sel = 3'b111;

#10 sel = 3'b101;

#10 sel = 3'b011;

#10 sel = 3'bx01;

#10 sel = 3'bxxz;

#10 sel = 3'bz01;

#10 sel = 3'b10z;

#10 sel = 3'b01x;

end

endmodule

16. n – bit Decoder Using Brhavioral For loop statementmodule decnbit_for #(parameter n = 3)(input [n-1:0]a,output reg [(2**n-1):0]y);

integer i;

always@(a)

begin

for(i=0; i<2**n ;i=i+1)

begin

if(i == a)

begin

if(i == 0)

y = 2'b10>>1;

else

y = 2'b10<<(i-1);

end

end

end

endmodule

Test Bench

module dec3bit_for_tb #(parameter n = 3);

reg [n-1:0]a;

wire [(2**n-1):0]y;

decnbit_for dec(.a(a),.y(y));

initial

begin

a = 3'b000;


#5 a = 3'b001;

#5 a = 3'b010;

#5 a = 3'b011;

#5 a = 3'bzzz;

#5 a = 3'b100;

#5 a = 3'b101;

#5 a = 3'b1x1;

#5 a = 3'bxxx;

#5 a = 3'b110;

#5 a = 3'b1z1;

#5 a = 3'b111;

end

endmodule

17. 8 : 3 Encoder using Behavioral For loop statement

module enc8to3_for(input [7:0]a, output reg [2:0]y);

integer i;

always@(a)

begin

for(i=0;i<8;i=i+1)

begin

if(a[i] == 1'b1)

y = i;

end

end

endmodule

Test Bench

module enc8to3_bh_tb;

reg [7:0]a;

wire [2:0]y;

enc8to3_for enc(.a(a),.y(y));

initial

begin

a = 8'b00000000;


#5 a = 8'b00000001;

#5 a = 8'b00000010;

#5 a = 8'b00000100;

#5 a = 8'b00001000;

#5 a = 8'b00010000;

#5 a = 8'b00100000;

#5 a = 8'b01000000;

#5 a = 8'b10000000;

end

endmodule

18. 4 – bit Johnson Counter

a. Using Generate For loop statement

module jc_4bit_gen (input clk,rst, output [3:0]q);

wire [4:0]w;

assign w[4] = ~w[0];

genvar i;

generate

for(i=4;i>0;i=i-1)

begin:f1

dff_arst d1(.clk(clk),.rst(rst),.d(w[i]),.q(w[i-1]));

end

endgenerate

assign q = w[3:0];

endmodule

b. Using Behavioral Modeling

module jc_4bit_for(input clk,rst, output reg [3:0]q);


begin

if(!rst)

q <= {4{1'b0}};

else

q <= {~q[0],q[3:1]};

end

endmodule

Test Bench

module cntr4bit_syn_tb;

reg clk,rst;

wire [3:0]q;

jc_4bit_gen cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#32 rst = 1;

end

endmodule

19. n – bit Johnson Counter

a. Using Generate For loop statement

module jc_nbit_gen #(parameter n = 8)(input clk,rst, output [n-1:0]q);

wire [n:0]w;

assign w[n] = ~w[0];

genvar i;

generate

for(i=n;i>0;i=i-1)

begin:f1

dff_arst d1(.clk(clk),.rst(rst),.d(w[i]),.q(w[i-1]));

end

endgenerate

assign q = w[n-1:0];

endmodule

b. Using Behavioral Modeling

module jc_nbit_for #(parameter n=8)(input clk,rst, output reg [n-1:0]q);


begin

if(!rst)

q <= {n{1'b0}};

else

q <= {~q[0],q[n-1:1]};

end

endmodule

Test Bench


reg clk,rst;

wire [n-1:0]q;

jc_nbit_gen cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#32 rst = 1;

#154 rst = 0;

#13 rst = 1;

#180 rst = 0;

#45 rst = 1;

end

endmodule

20. 4 – bit Ring Counter

module rc_4bit_for(input clk,rst, output reg [3:0]q);


begin

if(!rst)

q <= {1'b1,3'b0};

else

q <= {q[0],q[3:1]};

end

endmodule

Test Bench

module cntr4bit_syn_tb;

reg clk,rst;

wire [3:0]q;

jc_4bit_gen cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#32 rst = 1;

end

endmodule

21. n – bit Ring Counter

module rc_nbit_for #(parameter n=8)(input clk,rst, output reg [n-1:0]q);


begin

if(!rst)

q <= {1'b1,{n-1{1'b0}}};

else

q <= {q[0],q[n-1:1]};

end

endmodule

Test Bench


reg clk,rst;

wire [n-1:0]q;

rc_nbit_for cntr(.clk(clk),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 0;


#32 rst = 1;

#154 rst = 0;

#13 rst = 1;

#180 rst = 0;

#45 rst = 1;

end

endmodule

23 / 01 / 2015

22. T Flip flop in Behavioral Model

module tff(input t,clk,rst, output reg q);


begin

if(!rst)

q <= 1'b0;

else if(t==0)

q <= q;

else

q <= ~q;

end

endmodule

Test Bench

module tff_tb;

reg clk,rst,t;

wire q;

tff j1(.clk(clk),.t(t),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 1'b0; t=1'b0;

$monitor("clk=%b,rst=%b,t=%b,q=%b",clk,rst,t,q);

#12 rst = 1'b1;

#14 t=1'b1;

#27 t=1'b0;

#24 t=1'b1;

end

endmodule

23. J FF with asynchronous reset using Behavioral Model

module jkff(input j,k,clk,rst, output reg q);


begin

if(!rst)

q <= 1'b0;

else if(j==0&&k==0)

q <= q;

else if(j==0&&k==1)

q <= 1'b0;

else if(j==1&&k==0)

q <= 1'b1;

else if(j==1&&k==1)

q <= ~q;

else

q <= q;

end

endmodule

Test Bench

module jkff_tb;

reg clk,rst,j,k;

wire q;

jkff j1(.clk(clk),.j(j),.k(k),.rst(rst),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

rst = 1'b0; j=1'b0; k=1'b0;

$monitor("clk=%b,rst=%b,j=%b,k=%b,q=%b",clk,rst,j,k,q);

#12 rst = 1'b1;

#14 j=1'b1;

#17 k=1'b1;

#24 j=1'b0;

#27 k=1'b0;

#14 j=1'b0;

#17 k=1'b1;

end

endmodule

24. 4 : 1 MUX using only Conditional Operator

module mux4to1_cond (input [3:0]i, input [1:0]s, output y);

assign y = s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0]) ;

endmodule

Test Bench

module mux4to1_cond_tb;

reg [3:0]i;

reg [1:0]s;

wire y;

mux4to1_cond m1(.i(i),.s(s),.y(y));

initial

begin

i = 4’b1010; s = 2’b00;

$monitor(“i = %b, sel = %b, y = %b”,i,s,y);

#7 s = 2’b01;

#5 s = 2’b10;

#5 s = 2’b11;

#5 i = 4’b0101; s = 2’b00;

#7 s = 2’b01;

#5 s = 2’b10;

#5 s = 2’b11;

end

endmodule

25. n – bit Loadable, clk enabled, UpDown Counter

module cntrnbit_load #(parameter n = 4)

(input [n-1:0]d, input clk,ce,load,updown, output reg [n-1:0]q);


begin

if(!ce)

q <= q;

else if(load)

q <= d;

else if(updown)

q <= q+1;

else

q <= q-1;

end

endmodule

Test Bench

module cntrnbit_load_tb #(parameter n = 4);

reg [n-1:0]d;

reg clk,ce,load,updown;

wire [n-1:0]q;

cntrnbit_load c1(.d(d),.clk(clk),.ce(ce),.load(load),.updown(updown),.q(q));

initial

clk = 1'b0;

always

#5 clk = ~clk;

initial

begin

ce = 0; load = 1; updown = 1; d = 4'b0011;

$monitor("clk=%b, ce =%b, load = %b, data = %b, updown = %b, q=

%b",clk,ce,load,d,updown,q);

#17 ce = 1;

#15 load = 0;

# 80 updown = 0;

#7 d = 4'b1100;

#10 updown = 1;

#55 load = 1;

end

endmodule

26. 1 : 4 DEMUX in Behavioral Modeling

a. To infer latches at the output

module demux1to4 (input i, input [1:0]sel, output reg [3:0]y);

always@(sel)

begin

if(sel == 2’b00)

y[0] = i;

else if(sel == 2’b01)

y[1] = i;

else

y[2] = i;

end

endmodule

b. Not to infer latches at the output

module demux1to4 (input i, input [1:0]sel, output reg [3:0]y);

always@(sel)

begin

if(sel == 2’b00)

y[0] = i;


y[1] = i;


y[2] = i;


y[3] = i;

else

y = 4’bx;

end

endmodule

27. a. 4 – bit Parity Generator

module parity_gen(input [3:0]a, output y);

assign y = ^a;

endmodule

Test Bench

module parity_gen_tb;

reg [3:0]a;

wire y;

parity_gen pa1(.a(a),.y(y));

initial

begin

a = 4'b0000;

repeat(15)

begin

a = a + 4'b0001;

#10 $display("a=%b, y = %b”,a,y);

end

end

endmodule

4 – bit Parity Checker

module prity_check(input [4:0]a, output reg y);

always@(a)

begin

y = ^a;

if(y)

$display("error");

else

$display("No Error");

end

endmodule

Test Bench

module parity_check_tb;

reg [4:0]a;

wire y;

parity_check pa1(.a(a),.y(y));

initial

begin

a = 5'b00000;

repeat(31)

begin

a = a + 5'b00001;

#10 $display("a=%b, y = %b”,a,y);

end

end

endmodule

27 / 01 / 2015

28.Pattern Detector ( FSM )

a. 1101

module fsm1101

(input x,clk,rst,

output reg y);

parameter GN = 2'b00,

GOT1 = 2'b01,

GOT11 = 2'b10,

GOT110 = 2'b11;

reg [1:0]state,next;


begin

if(!rst)

state <= GN;

else

state <= next;

end

always@(state,x)

begin

case(state)

GN:if(x)

begin

next = GOT1;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b0;

end

GOT1:if(x)

begin

next = GOT11;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b0;

end

GOT11:if(x)

begin

next = GOT11;

y = 1'b0;

end

else

begin

next = GOT110;

y = 1'b0;

end

GOT110:if(x)

begin

next = GOT1;

y = 1'b1;

end

else

begin

next = GN;

y = 1'b0;

end

endcase

end

endmodule

Test Bench

module fsm1101_tb;

reg clk,x,rst;

wire y;

fsm1101 f1(.clk(clk),.rst(rst),.x(x),.y(y));

initial

begin

clk=0;

end

always

begin

#5 clk=~clk;

end

initial

begin

rst = 1'b0;

#40 rst=1'b1;

#220 rst = 1'b0;

#20 rst = 1'b1;

end

initial

begin

#15 x=1;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=1;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=1;

#10 x=0;

#10 x=1;

#10 x=1;

end

endmodule

b. 0111

module fsm0111

(input x,clk,rst,

output reg y);


GOT0 = 2'b01,

GOT01 = 2'b10,

GOT011 = 2'b11;



begin

if(!rst)

state <= GN;

else

state <= next;

end

always@(state,x)

begin

case(state)

GN:if(x)

begin

next = GN;

y = 1'b0;

end

else

begin

next = GOT0;

y = 1'b0;

end

GOT0:if(x)

begin

next = GOT01;

y = 1'b0;

end

else

begin

next = GOT0;

y = 1'b0;

end

GOT01:if(x)

begin

next = GOT011;

y = 1'b0;

end

else

begin

next = GOT0;

y = 1'b0;

end

GOT011:if(x)

begin

next = GN;

y = 1'b1;

end

else

begin

next = GOT0;

y = 1'b0;

end

endcase

end

endmodule

Test Bench

module fsm0111_tb;

reg clk,x,rst;

wire y;

fsm0111 f1(.clk(clk),.rst(rst),.x(x),.y(y));

initial

begin

clk=0;

end

always

begin

#5 clk=~clk;

end

initial

begin

rst = 1'b0;

#40 rst=1'b1;

#220 rst = 1'b0;

#20 rst = 1'b1;

end

initial

begin

#15 x=1;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=0;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=1;

end

endmodule

c. 1110

module fsm_1110

(input x,clk,rst,

output reg y);


GOT1 = 2'b01,

GOT11 = 2'b10,

GOT111 = 2'b11;



begin

if(!rst)

state <= GN;

else

state <= next;

end

always@(state,x)

begin

case(state)

GN:if(x)

begin

next = GOT1;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b0;

end

GOT1:if(x)

begin

next = GOT11;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b0;

end

GOT11:if(x)

begin

next = GOT111;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b0;

end

GOT111:if(x)

begin

next = GOT111;

y = 1'b0;

end

else

begin

next = GN;

y = 1'b1;

end

endcase

end

endmodule

Test Bench

module fsm_1110_tb;

reg clk,x,rst;

wire y;

fsm_1110 f1(.clk(clk),.rst(rst),.x(x),.y(y));

initial

begin

clk=0;

end

always

begin

#5 clk=~clk;

end

initial

begin

rst = 1'b0;

#40 rst=1'b1;

#220 rst = 1'b0;

#20 rst = 1'b1;

end

initial

begin

#15 x=1;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=0;

#10 x=0;

#10 x=1;

#10 x=1;

#10 x=1;

#10 x=1;

end

endmodule

Documents

Verilog Basic Programs