1

VERILOG DESCRIPTION OF A BASIC 4-BIT

PROCESSOR

Part 1: Implementation of the TOC on the DE2 Board using Verilog - Performed in Lab #1

Part 2: Extend the TOC to Achieve a 4-Bit Processor

- Done in Other Parts of Course (If Time Permits)

2

GOAL: IMPLEMENT A 4-BIT PROCESSOR IN THE FPGA OF THE DE2 BOARD

• Incrementally develop the Basic TOC

– Implemented in Laboratory 1

• Following additions (in Lectures) will be added if time permits

– Add Accumulator Functionality

– Add Multiplexers and Memory

– Add Address Generator Unit

– Add Computer Control Unit (CCU)

3

BLOCK DIAGRAM OF BASIC TOC

REGA REGB

REGR

ALU

7-SEG DISPLAY

Switches for Data

Clock

Switches for

Control

LEDs for

Unit Testing

4

ULTIMATE OBJECTIVE: A BASIC 4-BIT SOFT PROCESSOR IMPLEMENTED ON DE2 BOARD

5

ALTERA’S DE2 BOARD

6

SEVERAL PERIPHERAL I/O DEVICES

Red LEDs Green LEDs

FPGA Chip

18 Slider Switches (SW[17:0]) 4 Push Buttons (KEY[3:0])

8 7-Segments

(HEX)

7

SWITCH NAMES

• 18 Slider Switches

– SW (Vector Name)

– SW[17], SW[16], … SW[0] (Component Names)

• 4 Push Button Switches

– KEY (Vector Name)

– KEY[3], KEY[2], KEY[1], KEY[0] (Component Names)

8

LED NAMES

• 18 Red Light Emitting Diodes (LEDs)

– LEDR (Vector Name)

– LEDR[17], LEDR[16], …LEDR[0] (Component Names)

• 8 Green Light Emitting Diodes (LEDs)

– LEDG (Vector Name)

– LEDG[7], LEDG[6], … LEDG[0] (Component Names)

9

HEXADECIMAL DISPLAY NAMES

• Eight 7-Segment Hexadecimal Display Digits – HEX7, HEX6, HEX5, …, HEX1, HEX0 (Vector Names)

– HEXn[0] (A-segment of Digit n)

– HEXn[1] (B-segment of Digit n)

– HEXn[2] (C-segment of Digit n)

– HEXn[3] (D-segment of Digit n)

– HEXn[4] (E-segment of Digit n)

– HEXn[5] (F-segment of Digit n)

– HEXn[6] (G-segment of Digit n)

– HEXn[7] (Dec. Point of Digit n)

n = 0, 1, …, 7; the Hexadecimal digit.

Example: HEX0

10

PIN CONNECTION CONNECTION OF PERIPHERALS TO FPGA CHIP

• Each peripheral is connected (wired) to specific pins of the FPGA chip

• Slider Switches – SW[17], SW[16], … SW[0] (PIN_Y23, … PIN_AB28)

• Push Button Switches – KEY[3], KEY[2], KEY[1], KEY[0] (PIN_R24, …, PIN_M23)

• Red LEDs – LEDR[17], LEDR[16], … LEDR [0] (PIN_H15, …, PIN_G19)

• Green LEDs – LEDG[17], LEDG[16], … LEDG [0] (PIN_F17, …, PIN_E21)

• HEX Digits – HEX0[6], HEX0[5], … HEX0 [0] (PIN_H22, …, PIN_G18)

11

INCREMENTAL DEVELOPMENT PROCEDURE

• Split the TOC into a number of sub-circuits.

• Implement the TOC in an incremental fashion, adding and testing one sub-circuit at a time.

• Each sub-circuit is tested in isolation (Unit Testing)

– Red and Green LEDs used for unit testing (not actually part of the TOC).

12

TOC DIVISION SPLITTING THE TOC INTO A 5 INCREMENTAL DEVELOPMENT PHASES

• Phase 1 – REGA (Test Register A, output to LEDs)

• Phase 2 – REGA and REGB (Test Registers A and B, output to LEDs)

• Phase 3 – ALU (Test ALU with the Registers A and B, output to LEDs)

• Phase 4 – REGR (Test Registers R with ALU, REGA, and REGB , output to LEDs)

• Phase 5 – 7-Segment Display (Test 7-Segment Display with REGR, ALU, REGA, and REGB,

output to Hex display)

13

PHASE 1: REGA UNIT TESTING

REGA

Switches for Data

Red LEDs

Slider Switches

A_R/Wn

CLKn Switches

for Control Slider/PB Switches

DBUS

14

PHASE 3: REGA AND REGB UNIT TESTING

REGA

Switches for Data

Red LEDs

Slider Switches

A_R/Wn

CLKn

DBUS

REGB

Red LEDs

B_R/Wn

CLKn

15

REGB

PHASE 3: REGA, REGB, & ALU UNIT TESTING

REGA

Switches for Data

Slider Switches

A_R/Wn

CLKn

DBUS

B_R/Wn

CLKn

ALU

Red LEDs Red LEDs

M S3

S2

S1

S0

Slider Switches

Red LEDs

16

PHASE 4: REGA, REGB, ALU, & REGR UNIT TESTING

REGB REGA

Switches for Data

Slider Switches

A_R/Wn

CLKn

DBUS

B_R/Wn

CLKn

ALU

Red LEDs Red LEDs

M S3

S2

S1

S0

Slider Switches

REGR R_R/Wn

CLK

Red LEDs

Red LEDs

17

PHASE 5: REGA, REGB, ALU, REGR, & HEX SYSTEM TESTING

REGB REGA

Switches for Data

Slider Switches

A_R/Wn

CLKn

DBUS

B_R/Wn

CLKn

ALU

Red LEDs Red LEDs

M S3

S2

S1

S0

Slider Switches

REGR

7-Segment Display

CLK

Red LEDs

Red LEDs

18

PHASE 1: REGA UNIT TEST

Slider Switches

SW[0] SW[1] SW[2] SW[3]

Assigned Names to FPGA Pins

KEY0

Push Button Switch

FPGA

RegA

SW[4]

DBUS

Reg

AW

n

Wn Clock

Clo

ckn

D0 D1 D2 D3

Q0 Q1 Q2 Q3

LEDR[3]

LEDR[2]

LEDR[1]

LEDR[0]

RED LEDS

RegAQ[3]

RegAQ[2]

RegAQ[1]

RegAQ[0]

DE2 Board Components

DE2 Board Component

Clo

ck

19

VERILOG DESCRIPTION OF REGISTER A 4-BIT REGISTER

FILE: TOC_REGA.v

module TOC_REGA (SW, KEY, LEDR);

input [4:0] SW;

input [0:0] KEY;

output [3:0] LEDR;

wire [3:0] DBUS, RegAQ;

wire RegAWn, Clock, Clockn;

assign LEDR [3:0] = RegAQ [3:0];

assign Clockn = !Clock;

assign RegAWn = SW[4], Clock = KEY[0];

assign DBUS[3] = SW[3], DBUS[2] = SW[2];

assign DBUS[1] = SW[1], DBUS[0] = SW[0];

reg4 AReg (DBUS, RegAWn, Clockn, RegAQ);

endmodule

Instantiates a reg4

FILE: TOC_REGA.v (Continued)

module reg4 (D, Wn, Clock, Q);

input [3:0] D;

input Clock, Wn;

output reg [3:0] Q;

always @ (posedge Clock)

if (Wn==0)

Q <= D;

endmodule

Sub- Circuit

Top

-lev

el M

od

ule

20

MODULE CONNECTION TO PINS

• The declared inputs and outputs of the top-level module need to be specified as pin numbers of the FPGA:

– This is because the compiler connects the declared inputs and outputs of the top-level design file to pins on the FPGA chip.

FILE: TOP_LEVEL.v

module TOP_LEVEL (PIN_12, PIN_34, PIN_1234);

…

endmodule

21

MODULE CONNECTION TO PINS

• Alternatively, you can give names to the inputs and outputs, instead of pin numbers:

– If you do this, then you must also specify names of the pin numbers on the FPGA, and these names should match.

– If the names of your inputs and outputs do not match the assigned names of the pins on the FPGA, then the compiler will arbitrarily assign your inputs and outputs to random pins on the FPGA.

FILE: TOC_REGA.v

module TOC_REGA (SW, KEY, LEDR);

input [4:0] SW;

input [0:0] KEY;

output [3:0] LEDR;

…

endmodule

22

PIN ASSIGNMENT CONNECTIONS SPECIFIED IN FILE (DE2_115.qsf)

• Pin specification file may be imported into the Quartus II software – Facilitates pin mapping

– Assigns peripheral names to pins on the FPGA

– Pins of FPGA are wired to peripherals

– Your hardware description can use these names to interface to the peripherals

23

ANALYSIS

• Top level design file has inputs SW and KEY0; and outputs LEDR – These inputs/outputs are connected to the pins on the FPGA which have

been assigned the same names by the import procedure

– These FPGA pins are connected to the Slider Switch, Push Button, and Red LED Peripherals on the DE2 board.

TOC_REGA Circuit

SW[4]…SW[0]

LEDR[3]…LEDR[0]

KEY[0]

KEY[0] SW[4]…SW[0]

LEDR[3]…LEDR[0]

FILE: TOC_REGA.v

module TOC_REGA (SW, KEY, LEDR);

input [4:0] SW;

input [0:0] KEY;

output [3:0] LEDR;

…

24

TEMPLATE reg4

• A template for a sub-circuit is designed and named as reg4.

– This sub-circuit has inputs D, Clock, and Wn; and output Q

– Note that these are names within the module (sub-circuit)

• A template is not actually realized in the circuit, but just declared in the source code

RegA

Wn Clock D0 D1 D2 D3

Q0 Q1 Q2 Q3

module reg4 (D, Wn, Clock, Q);

input [3:0] D;

input Clock, Wn;

output reg [3:0] Q;

always @ (posedge Clock)

if (Wn==0)

Q <= D;

endmodule

25

INSTANTIATION OF reg4 AND CONNECTION TO REST OF CIRCUIT

• The following statement creates (realizes) a 4-bit register reg4 AReg (DBUS, RegAWn, Clockn, RegAQ);

– This makes a 4-bit register and names the register “AReg”

– Wires are connected to various points of the circuit:

input [4:0] SW;

input [0:0] KEY;

output [3:0] LEDR;

wire [3:0] DBUS, RegAQ; //declaration

wire RegAWn, Clock, Clockn; //declaration

reg4 AReg (DBUS, RegAWn, Clockn, RegAQ);

assign Clockn = !Clock, Clock = KEY[0];

assign LEDR [3:0] = RegAQ [3:0];

assign RegAWn = SW[4];

assign DBUS[3:0] = SW[3:0];

SW[0] SW[1] SW[2] SW[3] KEY0

RegA

SW[4]

DBUS

Reg

AW

n

Wn Clock

Clo

ckn

D0 D1 D2 D3

Q0 Q1 Q2 Q3

LEDR[3]

LEDR[2]

LEDR[1]

LEDR[0]

RegAQ[3]

RegAQ[2]

RegAQ[1]

RegAQ[0]

Clo

ck