Verilog Basics 10 Synthesis
Embed Size (px)
Citation preview
-
7/31/2019 Verilog Basics 10 Synthesis
1/15
1
Digital System Design
Synthesis
Dr. Bassam Jamil
-
7/31/2019 Verilog Basics 10 Synthesis
2/15
2
Design Flow
-
7/31/2019 Verilog Basics 10 Synthesis
3/15
3
What is Synthesis Definition
The process of converting a high-level descriptionof the design
into an optimized gate-levelrepresentation, given :
Standard library/technology library
Design constraints
-
7/31/2019 Verilog Basics 10 Synthesis
4/15
-
7/31/2019 Verilog Basics 10 Synthesis
5/15
5
Target Library Example
-
7/31/2019 Verilog Basics 10 Synthesis
6/15
6
Design Constraints
-
7/31/2019 Verilog Basics 10 Synthesis
7/157
Why Synthesis
-
7/31/2019 Verilog Basics 10 Synthesis
8/158
Logic Synthesis
-
7/31/2019 Verilog Basics 10 Synthesis
9/159
General Model of Synchronous Circuits
-
7/31/2019 Verilog Basics 10 Synthesis
10/1510
Clock Rate Limitations
-
7/31/2019 Verilog Basics 10 Synthesis
11/1511
Clock Rate Limitations
-
7/31/2019 Verilog Basics 10 Synthesis
12/1512
Logic Synthesis Steps
-
7/31/2019 Verilog Basics 10 Synthesis
13/1513
Optimization Criteria
-
7/31/2019 Verilog Basics 10 Synthesis
14/1514
-
7/31/2019 Verilog Basics 10 Synthesis
15/1515
