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Digital System Design
Verilog: FSMD Concepts and Example
Dr. Bassam Jamil
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FSMD
FSMD is Finite State Machine (FSM) withdatapath
Datapath is computational blocks
Adders/Subtractors
Shifters/Rotators
Multipliers
Dividers
etc
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FSDM
In the design process, start first with algorithm inhigh level
language
Then convert the algorithm to FSDM
Sometimes, a behavioral model substitute FSDM\
Then Implement the design in Verilog
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Example
We will consider two implementations of GCD
Both are correct Just learn how different approaches lead to
different
implementations.
First Implementation uses state diagrams
Second implementations start with behavioralmodel
Now to the FIRST IMPLEMTATION
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Greatest Common Divisor (GCD)
Inputs :
ld : load m and n : numbers
Output
gcd: great common divisor result
done: operation is complete
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GCD Example: FSM and Datapath
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GCD Example: FSM and Datapath
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CGD Example: I/O and State
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GCD Example: Single-case Design
end
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GCD Design
SECOND IMPLEMETNATION
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GCD In C
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Behavioral Model for GCD
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Testing Behavioral Model
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Deriving RTL
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RTL Design- Step 1: Define Port Interface
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RTL Design- Step 2: Define DatapathFunctional Units
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RTL Design- Step 2: Define Control Unit
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Datapath Module Interface
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Connect The Modules
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Connect the Modules
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Control Block
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Control Unit: FSM Implementation
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FSM Implementation
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FSM Implementation: Outputs
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Testing: Design the Testbench
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Testing: Checking the RTL
