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8/10/2019 Verilog Code for 4
http://slidepdf.com/reader/full/verilog-code-for-4 1/1
//Verilog code for 4-bit Johnson counter [synchronous counter]
module jhncntr(clk, q);
input clk;output [3:0] q;
reg [3:0] q;reg [3:0] temp;always@(posedge clk)
begincase (temp)
4'b0000: temp = 4'b1000;4'b1000: temp = 4'b1100;4'b1100: temp = 4'b1110;4'b1110: temp = 4'b1111;4'b1111: temp = 4'b0111;4'b0111: temp = 4'b0011;4'b0011: temp = 4'b0001;4'b0001: temp = 4'b0000;
default temp = 4'b0000;endcaseq= temp;end
endmodule
//Testbench for 4-bit Johnson counter [synchronous counter]
module jhncntrtest_v;
// Inputsreg clk;
// Outputswire [3:0] q;
// Instantiate the Unit Under Test (UUT) jhncntr uut (
.clk(clk),
.q(q));
always#10 clk=~clk;
initial begin// Initialize Inputs
clk = 0;#400;$stop;
end
endmodule