What is Verilog Verilog is first introduced in 1984 for Gateway Verilog-XL digital simulator In 1989, Gateway acquired by Cadence. Then in 1990, Cadence release the Verilog language and Verilog PLI to public. Open Verilog International(OVI) was formed to maintain the Verilog standard, in 1993, OVI releases the Verilog 2.0 Reference Manual, then becomes the IEEE (Verilog-1995)
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Verilog tutorial Hong-Hui Chen 05/17/2002 VLSI Design Course
Outline What is Verilog? Register transfer level (RTL) Up_counter
example Test_bench for Up_counter Get a simulator Simulation and
verification Synthesis Back end flow and a real CHIP Recommended
books What is Verilog Verilog is first introduced in 1984 for
Gateway Verilog-XL digital simulator In 1989, Gateway acquired by
Cadence. Then in 1990, Cadence release the Verilog language and
Verilog PLI to public. Open Verilog International(OVI) was formed
to maintain the Verilog standard, in 1993, OVI releases the Verilog
2.0 Reference Manual, then becomes the IEEE (Verilog-1995) Register
transfer level (RTL) Elements with memorial ability ->
flip-flops -> sequential circuit Combinational circuit is used
to calculate the next state of the flip-flops Up_counter example
Four sample designs for up_counter: up_counter_hello_world.v
up_counter_max.v up_counter_max_freeze.v
up_counter_max_freeze_pre_load.v Up_counter: in out declaration
module UP_COUNTER_hello_world(clock,reset,value_now); input
clock,reset; output [7:0]value_now; reg [7:0]value_now; // Q value
for filp-flops endmodule Up_counter: combinational ckt `ifdef
WAY_NO1 // D -> Combinational circuit wire [7:0]value_now_d; //
D values for flip-flops assign
value_now_d=reset?8'b0:(value_now+1'b1); `else // D ->
Combinational circuit reg [7:0]value_now_d; // D values for
flip-flops or value_now) // sensitivity list begin if(reset)
vaule_now_d=8'd0; else value_now_d=value_now+1'b1; end `endif
Up_counter: sequential ckt A edge triggered always block will infer
real flip-flops clock) begin value_now
