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Very Large Scale Integration II - VLSI II Verilog HDL Basics Hayri U ğur UYANIK ITU VLSI Laborator ies Istanbul Technical University. Outline. Verilog Simulation Setup Language Fundamentals Design Entities Concurrent Statements Data Types and Objects Operators Conditional Constructs - PowerPoint PPT Presentation
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04/22/23
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Very Large Scale Integration II - VLSI II
Verilog HDL Basics
Hayri Uğur UYANIK
ITU VLSI LaboratoriesIstanbul Technical University
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Outline Verilog Simulation Setup Language Fundamentals
– Design Entities– Concurrent Statements– Data Types and Objects– Operators– Conditional Constructs– Other– Simulation Fundamentals
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Verilog Simulation Setup
TestBench Module
Input Vectors Output VectorsDUT
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Language Fundamentals Design Entities Concurrent Statements Data Types and Objects Operators Conditional Constructs Other Simulation Fundamentals
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Design Entities Only “module” design entity
module MODULE1(input1, input_bus, output1, output_bus, inout1);input input1;input [<size-1>:0] input_bus;output output1;output [<size-1>:0] output_bus;inout inout1;SUBMODULE1 U1(submodule1_input1, submodule1_output1);….endmodule
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Concurrent Statements Statements executed in parallel
always @(<sensitivity list>) begin<some combinational or sequential operations>;
end
assign <combinational operations>;
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Data Types and Objects Logic Values: 0 1 X Z Numbers: width'radix value
– Binary: 8'b10001011– Octal: 8'o213– Hexadecimal: 8'h8B– Decimal: 8'd139– No radix = Decimal 139
wire, reg: Physical– wire: output of assign block– reg: output of always or initial (test purpose) block
parameter: Somewhat Physical integer: Mostly Test Purpose
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Operators Bus Operators Arithmetic Operators Bitwise Operators Reduction Operators Logical Operators
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Bus Operators A = 8'b10001011
Operator Description Example
[ ] Bit/Part Select A[0] = 1'b1A[5:2] = 4'b0010
{ } Concatenation {A[5:2],A[7:6],2'b01} = 8'b00101001
{{ }} Replication {3{A[7:6]}} = 6'b101010
<< Shift Left A<<2 = 8'b00101100
>> Shift Right A>>3 = 8‘b00010001
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Arithmetic Operators A = 8'b10001011 = 139
Operator Description Example
+ Addition A + 12 = 151 = 8'10010111
- Subtraction A – 10 = 129 = 8'10000001
* Multiplication A * 3 = 417 = 9'110100001
/ Division A / 2 = 69 = 7'b1000101
% Modulus A % 5 = 4 = 3'b100
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Bitwise Operators A = 8'b10001011
Operator Description Example
~ Inverse / NOT ~A = 8'b01110100
& AND A[2] & A[1] = 1'b0
| OR A[2] | A[1] = 1'b1
^ XOR A[2] ^ A[1] = 1'b1
~^ XNOR A[2] ~^ A[1] = 1'b0
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Reduction Operators A = 8'b10001011
Operator Description Example
& AND &A = A[0] & A[1] & … A[7] = 1'b0
~& NAND ~&A = ~(A[0] & A[1] & … A[7]) = 1'b1
| OR |A = A[0] | A[1] | … A[7] = 1'b1
~| NOR ~|A = ~(A[0] | A[1] | … A[7]) = 1'b0
^ XOR ^A = A[0] ^ A[1] ^ … A[7] = 1'b0
~^ XNOR ~^A = ~(A[0] ^ A[1] ^ … A[7]) = 1'b1
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Logical Operators A = 8'b10001011
Operator Description Example
! NOT !A[1] = FALSE, !A[2] = TRUE
&& AND A[0] && A[1] = TRUE
|| OR A[0] || A[2] = TRUE
== EQUAL A[3:0] == 4'b1011 = TRUE
!= NOT EQUAL A[3:0] != 4'b1011 = FALSE
<,<=,>,>= COMPARE A[3:0] < 13 = TRUE
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Conditional Constructsif – else
if(<Logical Statement1>) begin<Some Operations>;
end
else if(<Logical Statement2>) begin<Some Operations>;
end
else begin<Some Operations>;
end
case
case (<Select>)<Value1> : begin
<Operations>;end<Value2> : begin
<Operations>;end…default: begin
<Operations>;end
endcase
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Other Comments
///* ….. */
End of statement<Statement>;
Assignments– Blocking (Assignment in order) =– Non-blocking (Assignment in parallel) <=
Timing`timescale <unit>/<precision>
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Simulation Fundamentals Delays
# <Number of Units> Loops
repeat, while, for, forever Simulation Sequence
initial begin<Simulation Sequence>;
end System Tasks
– File I/O ($fopen, $fwrite, $fscanf.. etc)– Read Memory From File ($readmemb, $readmemh)– Stop Simulation ($stop)– Quit Simulation ($finish)
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Loops Repeat
initial begin repeat (30) begin @(posedge CLK); #1 DATA_IN = $random; endend
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Loops While
initial begin while (EMPTY==1'b0) begin @(posedge CLK); #1 read_fifo = 1'b1; endend
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Loops For
intitial for (i=0; i<15; i=i+1) DATA[i] = 1'b0;end
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Loops Forever
initial forever begin CLK = 1'b0; #5 CLK = 1'b1; #5; end
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Code Examplesmodule Full_Adder8(A, B, Sum, Carry_Out);
input [7:0] A, B;output [7:0] Sum;output Carry_Out;
assign {Carry_Out,Sum} = A + B;
endmodule
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Code Examplesmodule Full_Adder8(A, B, Sum, Carry_Out);
input [7:0] A, B;output [7:0] Sum;output Carry_Out;
reg [7:0] Sum;reg Carry_Out;
always@(A or B) begin{Carry_Out,Sum} = A + B;
end
endmodule
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Code Examplesmodule Full_Adder8_Clock(CLK,A, B, Sum, Carry_Out);
input [7:0] A, B;input CLK;output [7:0] Sum;output Carry_Out;
reg [7:0] Sum;reg Carry_Out;
always@(posedge CLK) begin{Carry_Out,Sum} <= A + B;
end
endmodule
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Code Examplesmodule Test_Full_Adder8_Clock;
reg CLK;reg [7:0] A, B;wire [7:0] Sum;wire Carry_Out;
Full_Adder8_Clock U1(CLK,A, B, Sum, Carry_Out);
initial beginCLK = 0;A = 30;B = 40;
#8 A = 20; //8th time unitB = 10;
#10 A = 100;B = 100; //18th time unit
#10 $finish;end
always #5 CLK = ~CLK;
endmodule
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Code Examplesmodule Shift_Reg_4_Good(CLK, RSTB, D, Q);
input CLK, RSTB;input D;output [3:0] Q;
reg [3:0] Q;
always@(posedge CLK or negedge RSTB) beginif(!RSTB) begin
Q <= 4'b0000;endelse begin
Q[0] <= D;Q[1] <= Q[0];Q[2] <= Q[1];Q[3] <= Q[2];
endend
endmodule
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Code Examplesmodule Shift_Reg_4_Ugly(CLK, RSTB, D, Q);
input CLK, RSTB;input D;output [3:0] Q;
reg [3:0] Q;
always@(posedge CLK or negedge RSTB) beginif(!RSTB) begin
Q = 4'b0000;endelse begin
Q[3] = Q[2];Q[2] = Q[1];Q[1] = Q[0];Q[0] = D;
endend
endmodule
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References Smith D. J., 1996. HDL Chip Design Xilinx Help
