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2011 Xilinx, Inc. All Rights ReservedLab1 IntroThis material exempt per Department of Commerce license exception TSU
Laboratory 3: VGA controller
implementation (solution)
using Xilinx EDK/SDK 10.1 SP3
University of PannoniaDept. Of Electrical Engineering and Information Systems
Instructor: Zsolt Vrshzi, PhD.
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Xilinx Literatures Xilinx University Program:
http://www.xilinx.com/university/
Xilinx Embedded Development Kit http://www.xilinx.com/support/documentation/dt_edk.htm Xilinx TFT-LCD IP core: http://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdf VGA controller (background): Digilent Nexys-2 board Reference Manual http://www.digilentinc.com/Data/Products/NEXYS2/ Nexys2_rm.pdf
12a- 2 Lab1 Intro
http://www.xilinx.com/university/http://www.xilinx.com/university/http://www.xilinx.com/university/http://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/support/documentation/dt_edk.htmhttp://www.xilinx.com/university/7/16/2019 VGA controller implementation.pdf
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MicroBlaze
LMBBRAMCntlr
BRAM
LMBBRAMCntlr
UART
GPIO
MDM
LEDs
PLBBus
SRAM
Flash
EMCCNTLR
Instruction Data
MicroBlaze SystemTask: Add XPS TFT Controller to your embedded system design(based
on
Lab
2)
PSBs
GPIODIP
You will add the Xilinx TFT Controller
instances and connect them to theVGA connector on the board
TFT
GPIO
VGA
interface
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XPS TFT Controller
(3. DVI interface
is included
in
the
design if
the
parameter
C_TFT_INTERFACE = 1.)
*4. VGA interface
is included
in
the
design if
the
parameter
C_TFT_INTERFACE = 0 is set.
See
xps_tft.pdf for
details. VGA
outputports
http://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdf7/16/2019 VGA controller implementation.pdf
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XPS TFT Controller
Features
Connects as 64-bit masteron PLB V4.6 bus of 64 or 128
bits data
width
Connects as a 32-bit Slave on the DCR V2.9 bus orPLBV4.6 bus of32, 64 and 128 bits data width
Supports DCR daisy chain protocol
(not
used
in
this
design)
Parameterizable TFT interface for18-bit VGA (or 24-bit DVI) Supports 25 Mhz TFT clock for display resolution of
640480 pixels
at 60 Hz refresh rate
Supports configuration of external Chrontel
DVI
video output chip
(not
used
in
this
design)
Chrontel
Transmitter Chip can
be programmed
through I2C interface
Supports separate clock (asynchronous) domain for PLB interfaceand
TFT interface
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EDK Design Flow
Add a XPS TFT Controllerperipheral
into
the design (based on Lab 2)Step 1: Copy
and open the
previous
Project (BSB)
Step 2:
Add and Connect
TFT
Peripheral to
the System
Step 3:
Configure the
TFT
Peripheral(s)
Step 4:
Make
External TFT
PeripheralConnections
Step 5:
Analyze the
MHS file
and
generate
BitstreamStep 6: Add
Software
Application
and
Compile
in SDK
Step 7: Verify
the Design in
Hardware
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Step 1-2-3 Copy all contents of the Lab2 folder into the Lab3. Start XPS/EDK. Open Lab3 project From IP Catalog view add an IO Modules XPS TFT v.1.00.a peripheral
Double click, or mouse right + select Add IP
User Tab all settings are default except for the following
Unselect the TFT Interface Base Address of the PLB Attached Video Memory:
= 0x90000000 ( map t o Mi cr onSRAM base address)
System Tab Set manually or generate addresses properly
Base Address: 0x90000000 High Address: 0x9000f f f f ( Map t o t he whol e Mi cr on SRAM
memor y capaci t y)
16 MB!
0x90000000
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Step 3
Bus Interface Tab:
Rename IP core xps_tft_0 tft_controller
Select
mb_plb
both
for
MPLB and SPLB ports
(OR click
on
brown
circles in
bus
connections, alternatively)
Addresses Tab:
Check
the
address
parameters
of the
tft_controller
NOTE: addresses does not overlap to each other and can be generated automatically (also
try
it!)
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Step
3
Double click on the clock_generator_0
In
ports
view
select
CLKOUT1
Required
frequency
(for
TFT controller): 25,000,000
Hz
Buffered: TRUE
Connected
to: New Connection
Check
SYS_TFT_Clk
(clock_generator_0_CLKOUT1 added)
Click
on
Validate
Clocks
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Note
If
CLKOUT1 port of the
clock_generator_0 instance
is not
displayed
on the System Assembly View Ports tab then you must refresh the GUI.
The 25 MHz DCM
clock
is connected
to
the TFT VGA clock
(640x480@60Hz)
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Step 3 Make external the selected 6 signals as
below: *TFT_VGA_B: 2-bit Blue
ch.
*TFT_VGA_G: 3-bit Green ch
TFT_VGA_R: 3-bit Red
ch
**TFT_DE: Data Enable
TFT_VSYNC: Vertical
Synchronization
TFT_HSYNC: Horizontal
Synchronization signal ** See xps_tft.pdffor details.
* See
Nexys2_rm.pdf
for
details.
http://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdf7/16/2019 VGA controller implementation.pdf
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Step 3 internal signals Padding 6-bit [5:0] R, G, and B color components with 0s. Remark: R, G are 3-bit wide, while B is 2-bit
Use
the
concatenation
(&) operation
with
the
given
number
of
binary
value
0b0
Padded
with
0s > 6 bits
of
R/G/B components
(VGA
controller
output)
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Step 4 external ports Change the range of the TFT_VGA_R / G / and B_pins as follows:
Tie
tft_controller_TFT_DE_pin to
1,
therefore
select
net_vcc
(it
always enables
data
out):
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Step 4 Edit system.ucf
Give
some
new
pin constraints
about
color
channels, and synchronization
ports Click on the system.ucffile under the Project tab
Copy
the
#VGA section
of the
Nexys2_General.ucf
provided
by Digilent
Inc into
the
system.ucf.
Important: Rename
pin names
according
to
the
source
below
in
order
to
match with
external
ports
name
of the
elaborated
Embedded
System!
### Addi t i onal si gnal s f or TFT cont r ol l er
NET t f t _cont r ol l er _TFT_VGA_R_pi n LOC = R9; # Bank = 2, Pi n name = I O/ D5, Type = DUAL, Sch name = RED0NET t f t _cont r ol l er _TFT_VGA_R_pi n LOC = T8; # Bank = 2, Pi n name = I O_L10N_2, Type = I / O, Sch name = RED1
NET t f t _cont r ol l er _TFT_VGA_R_pi n LOC = R8; # Bank = 2, Pi n name = I O_L10P_2, Type = I / O, Sch name = RED2NET t f t _cont r ol l er _TFT_VGA_G_pi n LOC = N8; # Bank = 2, Pi n name = I O_L09N_2, Type = I / O, Sch name = GRN0NET t f t _cont r ol l er _TFT_VGA_G_pi n LOC = P8; # Bank = 2, Pi n name = I O_L09P_2, Type = I / O, Sch name = GRN1NET t f t _cont r ol l er _TFT_VGA_G_pi n LOC = P6; # Bank = 2, Pi n name = I O_L05N_2, Type = I / O, Sch name = GRN2NET t f t _cont r ol l er _TFT_VGA_B_pi n LOC = U5; # Bank = 2, Pi n name = I O/ VREF_2, Type = VREF, Sch name = BLU1NET t f t _cont r ol l er _TFT_VGA_B_pi n LOC = U4; # Bank = 2, Pi n name = I O_L03P_2/ DOUT/ BUSY, Type = DUAL, Sch name = BLU2
NET TFT_VSYNC_pi n LOC = U3 | PULLUP;
NET TFT_HSYNC_pi n LOC = T4 | PULLUP;
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Step
5
Run Generate Netlist
Running
synthesis
process
(XST)
Elaborating IPs (check all components in MHS file) create
HDL wrappers
of the
embedded
BSB
Finally
generate
HW netlist
.ngc (e.g.
system.ngc file)
Run Generate Bitstream
Implement
Design (MAP->PLACE->ROUTE proc).
System.ncd is generated
Generate bitstream file for dowloading it to the FPGA with .bit (e.g. system.bit) Note: Check Report file (system.par) for resource utilization
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Questions Open the system.mhs file, study its contents, and answerthe following questions
Number of external ports:
___________________
Number of external ports that are output
(O):
___________________
Number of external ports that are input
(I):
___________________
Num. of external ports that are bidirectional
(IO):
___________________
Number
of clock
ports: ___________________
Freq: _________
Number
of reset
ports: ___________________
Polarity: _________
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Questions
List the instances to which the dcm_clk_s isconnected:
________________________________________
_____
List the instances connected to the mb_plb bus:
______________________________________________
List the instances connected to the
clock_generator_0_CLKOUT1 bus:________________________________________
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Questions
Draw the address map of the system,providing instance names:
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Questions
Check Report files (system.par) or log messages in Consol window after the
placement process step):
Logi c Ut i l i zat i on:Number of Sl i ce Fl i p Fl ops: _____ out of 17, 344 11%
Number of 4 i nput LUTs: __ __ _ out of 17, 344 19%
Logi c Di st r i but i on:Number of occupi ed Sl i s: _____ out of 8, 672 29%
Number of Ext er nal I OBs __ ___ out of 250 22%Number of Ext er nal I nput I OBs ____ _
Number of Ext ernal Out put I OBs ___ __Number of Ext er nal Bi di r I OBs _____
Number of BSCANs _____ out of 1 100%Number of BUFGMUXs _____ out of 24 8%
Number of DCMs _____ out of 8 12%Number of MULT18X18SI Os _____ out of 28 10%Number of RAMB16s _____ out of 28 71%Number of Sl i ces ___ __ out of 8672 29%Number of SLI CEMs _____ out of 4336 6%
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Xilinx SDK 10.1
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SDK 10.1 Step 1.) Run Xilinx Platform Studio EDK Select workplace / XPS Project directory (under LAB 3)
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Select Application Wizard Create a new SDK Application project
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Add project name
Add project name: VGATest andprocessor instance microBlaze_0
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Add project type
Project type: Xilinx MicroBlaze Executable Configurations: Debug / Release / Profile
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VGATest main.c Simple VGATest main.c application
created Note: Automatic build is set by default (if
you want to change: Project Build Automatically is not checked)
SW platform will
be created
(generated
from .MSS file)
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SW platform
microblaze_0_sw_platform
(right click -> generate Libraries and BSP or LIBGen icon)
Archives: .a (binary)
Microblaze_0 Code
Include*
See xparameters.h (generated from .MHS)
Lib
LibSrc
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DipTest
SW application
VGATest
{microblaze_0_sw_platform} Binaries (.elf)
Debug
(.elf)
main.c Additional headers and sources
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GPIO drivers
and applications
C:\Xilinx\10.1\EDK\sw\XilinxProcessorIPLib\drivers\ tft_v1_00_a: TFT LCD v1.00.a driver functions (low-and high-level driver functions [cpp, h])
/Build: OS dependent Makefiles
/Data:. t c l + . mdd ( dr i ver descr i pt or s)
/Doc: API in
html
form
(see index.html)
/Examples: simple
example
applications
(use
drivers)
e.g.
xtft_example.c
functions
/Src: sources
of low-, and higher-level
drivers
xtft.h, .c
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gpio_header.h
Declares XTf t _Dr awSol i dBox ( ) function forprototyping Declares Tf t Exampl e ( ) function for prototyping Dependencies: #include
#include
#include "xbasic_types.h"
#include "xstatus.h"
#include "xparameters.h"
#include "xtft.h"
See
driver\example\xtft_example.cfor
further
details!
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Step
2.) Generate
Linker
Script
If necessary, set all sections of the .elf fileinto
the
internal
BRAM memory
Select [ilmb_cntlr_dlmb_cntlr] -> Generate
SDK C t t
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SDK: Custom program segments (compile sw application)
.text the executable code .rodata any read-only data used in the execution of the code .data where read-write variables andpointers are stored .bss a part of the data segment containingstatically-allocated variables .heap where dynamically allocated memoryis located
.stack where
function-CALL
parameters
and other temporary data is stored
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Step
3.) Build
SW application
After building the VGATest softwareapplication the size of the generated,downloadable VGATest.elf file as follows:
************** Det er mi ni ng Si ze of ELF Fi l e **************
mb- si ze VGATest . el ft ext dat a bss dec hexf i l ename
9694 1472 1104 12270 2f eeVGATest . el f
Bui l d compl et e f or pr oj ect VGATest
OK.
It
is (12 270 bytes
of
total program code) fitted to the 32KByte BRAM internal
memory.
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Step
4. Terminal Program
Set the following parameters properly(see the parameters of xps_uartlite in the .mhs file!)
Com
port: COMX
Baud Rate: 9600 Data Bits: 8 Stop Bits: 1 Parity Bit: None Flow control: none
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Select Device Configuration menu -> Bitstream settings
Select
compiled
DipTest.elffile for
running
MicroBlaze
sw
codes
Connect the Xilinx JTAG-Platform USB cable to Nexys-2boards JTAG interface
Select Device Configuration menu -> Program FPGA
Bitstream (system.bit) BRAM Memory
Map (.bmm) + VGATest.elf
-> D:\FPGA\BEAGYAZOTT_RENDSZEREK\10_1\03_LAB\SDK\SDK_projects\implementation\download_sdk.bit
Step 5. Method a.) Programming the FPGA via Xilinx Impact
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Step 5. Method b.) Programming the FPGAvia Digilent Adept
Instead of using the Xilinx iMpact, we use Digilent Adept Suite! programmer provided byDigilentInc (vendor of the FPGA board).
Browse
your
SDK_pr oj ect \ i mpl ement at i on\
directory for download_sdk.bit bitstream file. Use and set properly the terminal program (e.g.Windows Hyperterminal, Teraterm
Pro, or
Putty
etc.)
At the final step Program the FPGA! At now the Lab 3 is completed in SDK 10.1SP3
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Lab2 Intro
Question
What is the size of.elfprogram, and the differentprogram sections? Which is the base_address and high_address (oraddress size) of the push button TFT_LCD
peripheral?
Which header .h file contains the MicroBlazesystem parameters for various peripherals?