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VHDL Data Types Module F3.1

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VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not supported by synthesis tools

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VHDL Data Objects Constant Variable Signal File* * Not supported by synthesis tools

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Identifiers May contain A-Z, a-z, 0-9, _ Must start with letter May not end with _ May not include two consecutive _ VHDL is case insensitive Sel sel and SEL refer to same object

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Identifier Examples A2G valid 8bit_counter invalid -- starts with number _NewValue invalid -- starts with _ first# invalid -- illegal character

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Characters and Strings Characters A, 0, 1, $, x, * Strings string of characters 00101101 0X110ZZ1

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Characters and Strings Bit Strings B011111010110 O3726 X7D6

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Integer Data Type Integer Minimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647 Example assignments to a variable of type integer : ARCHITECTURE test_int OF test IS BEGIN PROCESS (X) VARIABLE a: INTEGER; BEGIN a := 1; -- OK a := -1; -- OK a := 1.0; -- illegal END PROCESS; END test_int; ARCHITECTURE test_int OF test IS BEGIN PROCESS (X) VARIABLE a: INTEGER; BEGIN a := 1; -- OK a := -1; -- OK a := 1.0; -- illegal END PROCESS; END test_int;

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Integer Data Type Minimum range for any implementation: - 2,147,483,647 to 2,147,483,647 Define range of integer minimizes synthesized logic type CountValue is range 0 to 15; type Twenties is range 20 to 29; type Thirties is range 39 downto 30; Range should start with 0 Synthesis tools use number of bits as if starting at 0

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Example of Integer Data Type process(addr) variable j: integer range 0 to 35; variable addru: unsigned(7 downto 0); begin for i in 7 downto 0 loop addru(i) := addr(i); end loop; j := conv_integer(addru); M