Vi t l MVi t l MVirtual MemoryVirtual Memory

Jin-Soo Kim (jinsookim@skku.edu)Jin Soo Kim (jinsookim@skku.edu)Computer Systems Laboratory

Sungkyunkwan Universityhtt // l kk dhttp://csl.skku.edu

Virtual MemoryVirtual MemoryVirtual MemoryVirtual MemoryUse main memory as a “cache” for secondary y y(disk) storage• Managed jointly by CPU hardware and the OSg j y y

Programs share main memory• Each gets a private virtual address space holding its• Each gets a private virtual address space holding its

frequently used code and data• Protected from other programsProtected from other programs

CPU and OS translate virtual addresses to physical addressesphysical addresses• VM “block” is called a page• VM translation “miss” is called a page fault

2ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

• VM translation miss is called a page fault

Address TranslationAddress TranslationAddress TranslationAddress TranslationFixed-size pages (e.g., 4KB)p g ( g )

3ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Page Fault PenaltyPage Fault PenaltyPage Fault PenaltyPage Fault PenaltyOn page fault, the page must be fetched from p g p gdisk• Takes millions of clock cyclesy• Handled by OS code

Try to minimize page fault rate• Fully associative placement• Fully associative placement• Smart replacement algorithms

4ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Page Tables (1)Page Tables (1)Page Tables (1)Page Tables (1)Stores placement informationp• Array of page table entries, indexed by virtual page

number• page table register in CPU points to page table in

physical memory

If page is present in memory• PTE stores the physical page numberp y p g• Plus other status bits (referenced, dirty, …)

If page is not presentIf page is not present• PTE can refer to location in swap space on disk

5ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Page Tables (2)Page Tables (2)Page Tables (2)Page Tables (2)Translation using a page tableg p g

6ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Page Tables (3)Page Tables (3)Page Tables (3)Page Tables (3)Mapping pages to storagepp g p g g

7ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Replacement and WritesReplacement and WritesReplacement and WritesReplacement and WritesTo reduce page fault rate, prefer least-p g precently used (LRU) replacement• Reference bit (aka use bit) in PTE set to 1 on access ( )

to page• Periodically cleared to 0 by OS• A page with reference bit = 0 has not been used

recently

Disk writes take millions of cycles• Block at once, not individual locations• Use write-back: write through is impractical• Dirty bit in PTE set when page is written

8ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

y p g

TLB (1)TLB (1)TLB (1)TLB (1)Address translation would appear to require pp qextra memory references• One to access the PTE• Then the actual memory access

B t t t bl h d l litBut access to page tables has good locality• So use a fast cache of PTEs within the CPU• Called a Translation Look-aside Buffer (TLB)• Typical: 16-512 PTEs, 0.5-1 cycle for hit, 10-100 cycles

f i 0 01% 1% ifor miss, 0.01%-1% miss rate• Misses could be handled by hardware or software

9ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

TLB (2)TLB (2)TLB (2)TLB (2)Fast translation using a TLBg

10ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

TLB (3)TLB (3)TLB (3)TLB (3)TLB misses: if page is in memoryp g y• Load the PTE from memory and retry• Could be handled in hardware

– Can get complex for more complicated page table structures

• Or in software– Raise a special exception, with optimized handler

TLB misses: if page is not in memory (pageTLB misses: if page is not in memory (page fault)

OS handles fetching the page and updating the page• OS handles fetching the page and updating the page table

• Then restart the faulting instruction

11ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

• Then restart the faulting instruction

TLB (4)TLB (4)TLB (4)TLB (4)TLB miss handler• TLB miss indicates

– Page present, but PTE not in TLB– Page not present

• Must recognize TLB miss before destination register ioverwritten

– Raise exception

H dl i PTE f t TLB• Handler copies PTE from memory to TLB– Then restarts instruction– If page not present page fault will occurIf page not present, page fault will occur

12ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Page Fault HandlerPage Fault HandlerPage Fault HandlerPage Fault HandlerHandling page faultsg p g• Use faulting virtual address to find PTE• Locate page on diskp g• Choose page to replace

– If dirty, write to disk first

• Read page into memory and update page table• Make process runnable againp g

– Restart from faulting instruction

13ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

Memory ProtectionMemory ProtectionMemory ProtectionMemory ProtectionDifferent tasks can share parts of their virtual paddress spaces• But need to protect against errant accessp g• Requires OS assistance

H d t f OS t tiHardware support for OS protection• Privileged supervisor mode (aka kernel mode)• Privileged instructions• Page tables and other state information only

ibl i i daccessible in supervisor mode• System call exception (e.g., syscall in MIPS)

14ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

TLB & Cache InteractionTLB & Cache InteractionTLB & Cache InteractionTLB & Cache InteractionIf cache tag uses gphysical address• Need to translate

before cache lookup

Alternative: useAlternative: use virtual address tag

C li ti d• Complications due to aliasing

• Different virtual• Different virtual addresses for shared physical address

15ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

p ys ca add ess

Integrating VM and Cache (1)Integrating VM and Cache (1)

Physically addressed caches

g g ( )g g ( )

• Allows multiple processes to have blocks in cache at the same time.

• Allows multiple processes to share pages• Allows multiple processes to share pages.• Address translation is on the critical path.

MemoryTLB

VAPATLB hit

CachePA

Cache

Pagetables

TLB miss Cachehit

miss

page

PTEd

fault

16ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

data data

Integrating VM and Cache (2)Integrating VM and Cache (2)

Virtually addressed, virtually tagged caches

g g ( )g g ( )

• Homonym problem: – Each process has a different translation of the same virtual address.

Address synonyms or aliases problem• Address synonyms or aliases problem.– Two different virtual addresses point to the same physical address.

MemoryTLB

VA VATLB hit

Cache

PA

Cache

Pagetables

TLB missCachehit

Cachemiss

pagefault

PTEdata data

fault

17ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

data data

Integrating VM and Cache (3)Integrating VM and Cache (3)

Virtually addressed, physically tagged caches

g g ( )g g ( )

• Use virtual address to parallel access to the TLB and cache.• TLB produces the PFN – which must match the physical tag of

the accessed cache line for it to be a “hit”the accessed cache line for it to be a hit .

VAVPN offset

Memory

CachePageTLBPA

page

VPN offset

CachePagetables

TLBhit

TLBmiss

TLBpagefault

?

PFNhit miss

PTE

Cachemiss

=?

PFN

Cachehit

18ICE3003: Computer Architecture | Fall 2009 | Jin-Soo Kim (jinsookim@skku.edu)

data data