FPGA Based Implementation & Power Analysis of Parameterized
Walsh Sequences
Gaurav Purohit1, V.K Chaubey2
Department of EEE BITS- Pilani, Pilani Campus
Pilani, India gp.bits@ gmail.com1, [email protected]
Kota Solomon Raju3, Divya Vyas Digital Systems Group CSIR -
CEERI Pilani
Pilani, India [email protected]
Abstract This paper presents FPGA based implementation of the
theory which replaces a general Sine and cosine function by set of
orthogonal functions i.e. Walsh function. The paper further
compares Parameterized Serial In Serial Out architectures based on
classical counter approach. The investigation consider FPGA
parameters like Area, Speed and Power and shows that using
Gray-increment based architecture instead of Binary saves 6mW of
power per symbol (64 Walsh chips per symbol) with 30% reduction in
area. The design is implemented in VHDL code, simulated in MATLAB
System Generator environment and validated with MATLAB Simulink
Model. The design targeted Xilinx Virtex-5 XC5VLX50T-1ff1136 FPGA
device for the implementation and comparison. The design found
their uses in many popular applications like Software Define Radio
(SDR) including multiuser communications such as CDMA, WCDMA, VLSI
testing, pattern recognition as well as image and signal
processing.
Keywords-CDMA, Rademacher function, SDR, System Generator,
WCDMA, Walsh sequences, Walsh function.
I. INTRODUCTION WALSH functions are a complete set of periodic
two- valued {+1,-1} orthogonal functions that can be used in
somewhat the same manner as Fourier functions. J.L Walsh in his
article A closed set of normal orthogonal functions of 1923 defined
orthogonal functions, which is closed in a standard interval (0, 1)
and every function takes the values {+1,-1} except the final number
of discrete points, which is zero [1]. Walshs definition seems more
appealing to engineers because of the analogy with trigonometric
functions in terms of ordering the functions according to the
increasing average number of zero crossings in a unit interval,
called sequency. However, they have aroused great interest in
recent years in wireless communication as they are used as
channelization code in many standards such as CDMA2000 (Code
Division Multiple Access), WCDMA (Wideband Code Division Multiple
Access) [2].
They are used for the elimination or the reduction of
interference within the users and within the channels and
furthermore for their identification. They have vast applications
in the field of communications, fast
Fourier transforms, audio and video signal processing, filtering
and multiplexing have been widely reported in literature [3]-[4]
specially for multimode radio SDR (Software Defined Radio) and
Reconfigurable Radio as in CDMA standard, where the individual
channels are distinguished from each other by mutual orthogonality
of signals. It is therefore, necessary to create mutually
orthogonal sequences, through which information is transmitted by
various channels spread. The Table I shows the application of Walsh
code in the CDMA Reverse channels [5].
This paper presents a customized, elegant, and concise solution
for building hazard free, noiseless 64-orthogonal set using
Rademacher function. Furthermore presents the comparison is based
on three main parameter viz. power, speed and area for two
prominent SISO architecture i.e. using classical binary counter and
Gray counter.
Table I Walsh functions for reverse CDMA channel
The paper is structured as follows: Section 2 illustrates about
generation of the Walsh sequence and previous works to provide
appropriate background. In Section 3, describes FPGA implementation
of SISO architectures. In Section 4, we investigate and evaluate
our results by comparing the two implemented architectures.
Sponsors: CSIR MHRD, DELHI SRF Fellowship
Proceeding of the 2014 IEEE Students' Technology Symposium
TS14P01 363 978-1-4799-2608-4/14/$31.00 2014 IEEE 292
II. WALSH FUNCTION GENERATORS
There are two different kinds of Walsh function generators are
in use the first generates only one Walsh function at a time out of
a large possible number. Whereas the second method generates a
complete set of Walsh functions simultaneously. Our implementations
generate only one Walsh function at a time and are shown with two
different architectures based on Rademacher function. The
difference is that first architecture uses classical binary counter
and gray index whereas other by gray counter and gray index. Let us
see how Rademacher functions are used for generating Walsh sequence
[6]. Rademacher functions of order N are set of 1+log2N orthogonal
functions consisting of N=2^k rectangular pulses where, k is
integer. These pulses assume alternately the values +1 and -1 in an
interval of (0, T). The Rademacher functions of order N are defined
by the relation,
Rn (t) = sgn (sin 2n t), t (T, 0), n = 1, 2 ... K (1) Where R0
(t) = 1, -1 for x < 0 Sgn(x) = 0 for x = 0 +1 for x > 0 (2)
After generating Rademacher functions these are converted to
Rademacher sequences. This operation yields conversion into binary
logic (+10 & -11). The Walsh sequences are generated as a
modulo-2 sum of Rademacher functions. This process is based on
Walsh function index sequence conversion into the Gray code. Index
sequence of Walsh function is simply Walsh function index in binary
code Xi = (xi1, xi2xiK) The Gray code Gi = (gi1, gi2 giK) is
created as follows:
gi1 = xi1 (3) gik = xiJ-1 xiJ J = 2,3...K (4) The Walsh
sequences are exactly formed as the modulo-2 sum of R0 and the
other Rademacher sequences {Rj} that are not associated with zero
values of Gi. This can be formulated as follows: Wi = R0(t) [ R1(t)
if gi1 = 1 ] [R2(t) if gi2 = 1] (5) Wi = R0 RK +1 j (6)
j:gij =1
Walsh functions can be defined in terms of a difference
equation, by their symmetry properties or by products of Rademacher
functions [7]. The difference equation method
is an iterative process. It is not suitable for generating Walsh
functions since errors in timing will accumulate for higher order
functions. Peterson has suggested a Walsh function generator based
on the symmetry properties [8]. Most other generators use products
of Rademacher functions. They generate first the set of Rademacher
functions by means of binary counters. The first such generator was
described by Harmuth [9]. It uses half-adders to perform the
multiplication of the Rademacher functions. Lebert [10] constructed
another interesting type that uses the trailing edges of selected
Rademacher functions to set and reset a flip-flop to generate a
single Walsh function. A similar generator that uses gates instead
of differentiators was described by Yuen [11]. Another one proposed
by Nawrath [12] uses multiplexers. Regarding implementation a
prototype Walsh Function Generator (WFG) for a NASA satellite
called the ESTAR (Electronically Scanned Thinned Array Radiometer)
has been designed and tested by William A. Chren using a single
Xilinx XC302OPC68-50 FPGA, another by Yukihiro and Tsutomu but
their FPGA implementations show their feasibility up to n= 14 [13].
One parallel method is shown by G. Evans for CDMA IS-95 but that
method is having ASIC Flow [14][15]. Our implementation uses
conventional approach but shows complete FPGA flow with comparative
analysis of power, area and speed which give an easiest approach to
select between two conventional available methods.
Figure 1 SISO architecture based on classical counter
approach
Proceeding of the 2014 IEEE Students' Technology Symposium
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S.No. Parameter NOISY BOYArchitecture 1
GENTLEMAN Architecture 2
1 Slice utilization 5 52 Flip Flops 12 73 Look Up Table 14 104
IOS 14 14
S.No. Parameter NOISY BOY Architecture 1
(In watts)
GENTLEMAN Architecture 2
(In watts) 1 Clock 0.003 0.0032 Logic 0.00013 0.000483 Signal
0.00020 0.000694 IOS 0.018 0.0125 Device leakage 0.448 0.448Total
0.470 0.464
S.No. Parameter NOISY BOY Architecture 1
(In watts)
GENTLEMAN Architecture 2
(In watts) 1 Clock 0.010 0.0092 Logic 0.00025 0.000783 Signal
0.00040 0.001294 IOS 0.062 0.0325 Device leakage 0.448 0.448Total
0.521 0.490
IV. RESULTS The implementation shows that Noisy boy i.e. first
architecture as shown in Fig.1 are having glitches at many
transition at output waveform shown in Fig. 5 whereas gentleman
i.e. our second architecture with gray counter is hazard free and
noiseless because of its single transition per clock. Further
investigation related to area is shown in table 2 shows that
Architecture 2 has 30% less area consumption compared to first.
Results are cross verified with system generator based resource
estimator. [ 1 6 ]
Table II Estimated device utilization for the Two
Architecture
Both the architecture runs with maximum frequency 600 MHz
(synthesized) with corresponding minimum delay 1.667 ns. The power
analysis has been done with minimum frequency 100 MHz i.e. time 10
ns as well as for maximum frequency i.e. 600 MHz and time 1.667 ns.
The table 3 & 4 will report the power consumption of one symbol
per 65 clocks or can say 64 bit output and one for reset at
beginning. The investigation shows Architecture first (noisy boy)
consumes 6mW more power for the same operation then the
architecture second (Gentleman).
Table III Estimated power for the Two Architecture AT 100
MHz
Table IV Estimated power for the Two Architecture AT 600 MHz
V. CONCLUSIONS The paper gives a finest look over FPGA based
implementation of Walsh Sequences i.e. 64-ary orthogonal codes
using Xilinx System Generator with MATLAB environment. The
simulation of VHDL code is validated with MATLAB Simulink copyright
block. Furthermore power, area and speed analysis is represented
which are required for FPGA based development. The architecture
first i.e. noisy boy give glitches at output waveform w.r.t
gentleman i.e. second Architecture which give us a best results
without any tradeoff in frequency of operation.
VI. ACKNOWLEDGMENT This paper is produced with the CSIR-SRF,
MHRD Fellowship. The author would like to thank Mrs. Anu Gupta, HOD
Department of EEE, BITS-Pilani and CSIR- CEERI for their
support.
VII. REFERENCES [1] J. L. Walsh, "A closed set of normal
orthogonal functions," AJM. Vol.
45. Pp. - 5-24, 1923. [2] Lee, J. S., Miller L. E.,CDMA System
Engineering Handbook,
London: Artech House, 1998, pp.6873. [3] Jos, S., Nair, J.P. ,
Sen, D. , Naniyat, A. Method of Generating
Multiple Sets of Orthogonal Codes with Wide Choice of Spreading
Factors Wireless Communications Letters, IEEE, Jul. 9 2012, pp.
492- 495.
[4] Teng Su., Feng Yu., A Family of Fast HadamardFourier
Transform Algorithms, Signal Processing Letters, IEEE, Jul. 10,
2012, pp. 583 586.
[5] Physical Layer Standard for cdma2000 Spread Spectrum
Systems. Available: [online]
http://www.3gpp2.org/public_html/specs/c.s0002-d_v1.0_021704.pdf,
Mar.-2013.
[6] H. Harmuth, Transmission of Information by Orthogonal
Functions.2nd New York: Springer, 1972.
[7] D. A. Swick, "Walsh function generation," IEEE Trans.
Inform. Theory, vol. IT-15, pp. 167-170, Jan. 1969.
[8] H. L. Peterson, "Generation of Walsh functions," in 1970
Proc.Symp. and Workshop on Applications of Walsh Functions, Naval
Research Lab., Washington, D.C., Apr. 4, 1970, pp.55-56.
[9] H. Harmuth, "Grundzuege einer Filtertheorie fur die
Maeanderfunktionen An," Archiv der Elektrischen Ubertragung, vol.
18, pp. 544-554, Sept. 1964.
[10] F. J. Lebert, "Walsh function generator for a million
different functions," in 1970 Proc. Symp. and Workshop on
Applications of Walsh Functions, Naval Research Lab., Washington,
D.C., Mar. 31-Apr. 4, 1970, pp. 52-54.
[11] C. K. Yuen, "New Walsh function generator," Electron.
Lett., vol. 7, p. 605, 1971.
[12] R. Nawrath, "A new Walsh generator and estimation of the
total orthogonality error of these generators," in 1972 Proc. Symp.
on Application of Walsh Functions, The Catholic University of
America, Washington, D.C., March 27-29, 1972, pp. 122-127.
[13] Chren, W.A., Walsh function generator using a field
programmable gate array [for ESTAR], ASIC Conference and Exhibit,
1993. Proceedings., Sixth Annual IEEE International,1993, pp. 341-
344.
[14] G. Bi ,B.G. Evans,: Hardware structure for Walsh-Hadamard
transforms, Electronics Letters, 1998 , pp. 2005 - 2006.
[15] Purohit, G.; Chaubey, V.K. ; Raju, K.S.;Reddy, P.V., "FPGA
based implementation and testing of OVSF code," International
Conference on Advanced Electronic Systems (ICAES-2013), CEERI,
Pilani, India. 21-23, September 2013.
[16] Xilinx System Generator User's Guide, www. Xilinx.com.
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