Virtex-5 FPGA RocketIO GTP TransceiverVirtex-5 FPGA RocketIO GTP Transceiver UG196 (v1.9) March 25, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification

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Virtex-5 FPGA RocketIO GTP TransceiverUser Guide

UG196 (v1.9) March 25, 2009

www.BDTIC.com/XILINX

Virtex-5 FPGA RocketIO GTP Transceiver www.xilinx.com UG196 (v1.9) March 25, 2009

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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UG196 (v1.9) March 25, 2009 www.xilinx.com Virtex-5 FPGA RocketIO GTP Transceiver

Revision HistoryThe following table shows the revision history for this document. an

Date Version Revision

09/06/06 1.0 Initial release to CD.

10/13/06 1.1 Initial release to www.xilinx.com

02/02/07 1.2 Added SXT packages to “Package Placement Information” in Chapter 4. Inserted RX buffer overflow/underflow footnotes to Table 7-28 and Table 7-30. Added “SelectIO to GTP Crosstalk Guidelines” in Chapter 10. Added “SelectIO to Serial Transceiver Crosstalk Guidelines” in Chapter 11. Added Appendix E, “Low Latency Design.” Removed Virtex-II Pro X FPGA references.

05/25/07 1.3 Chapter 1: Revised line rates in the “Overview,” page 23. Added to RXBYTEISALIGNED description and removed CRC ports in Table 1-3, page 28. Corrected PCOMMA_DETECT entry and removed CRC_INIT[31:0] attribute in Table 1-5. CRC ports are not part of the GTP_DUAL primitive. See Chapter 8.

Chapter 3: Added “Providing Clocks in Simulation,” page 50. Added multirate clocking design caveats and link to Appendix F.

Chapter 4: Added a note 2 to Table 4-1, page 55.

Chapter 5: Added to note 5 in Figure 5-1, page 68. Added PCS_COM_CFG and notes to Figure 5-2, page 71. Revised Equation 5-1. Changed PLL clock frequency for FC1, FC2, SFI-5, TFI-5, and the HD-SDI standard in Table 5-3, page 71. Revised the notes for Figure 5-5, page 79. Added PRBSCNTRESET and PLLPOWERDOWN, and revised GTPRESET description in Table 5-6, page 81. Revised “GTP Component-Level Resets” and “Link Idle Reset Support,” page 83. Added note to RXPOWERDOWN in Table 5-9, page 89. Added note to Table 5-11, page 91.

Chapter 6: Added a BUFG to Figure 6-5. Revised PMA_COM_CFG, OVERSAMPLE_MODE, and added three attributes to Table 6-8, page 112. Revised the “Using the TX Phase-Alignment Circuit to Bypass the TX Buffer,” page 113. Revised Figure 6-12, page 114. Added INTDATAWIDTH to Table 6-12, page 116. Revised OVERSAMPLE_MODE in Table 6-14, page 118. Revised TX_DIFF_BOOST in Table 6-16, page 120. Added default value to Table 6-18, page 121.

Chapter 7: Revised Figure 7-2, page 132. Updated Table 7-3. Added OOB nominal values to Table 7-6. Added “Tuning the CDR,” page 144. Revised Table 7-12, page 146. Added note 1 to Table 7-29, page 169. Revised CLK_COR_MAX_LAT.

Chapter 8: Added clarification to the CRC block description.

Chapter 9: Made changes to “Near-End PCS Loopback,” “Near-End PMA Loopback,” “Far-End PMA Loopback,” and “Far-End PCS Loopback,” including adding “Marginal Conditions and Limitations.” Added Table 9-2.

Chapter 10: Clarified “REFCLK Guidelines,” page 223. Added Figure 10-12. Added TERMINATION_IMP to Table 10-2. Added note on analog supplies to Table 10-5, Table 10-16, and Table 10-17. Added SelectIO adjacent to MGTCLK tables at the end of the chapter. Edited “AC Coupling,” page 227. Added an additional guideline to “Filter Network Design Guidelines.”

Appendix D: Added PCS_COM_CFG to Table D-2, Table D-7, and Table D-8. Revised bit 4 and 6 in Table D-3.

Appendix E: Added note 2 to Table E-2, page 323.

Added Appendix F.



Virtex-5 FPGA RocketIO GTP Transceiver www.xilinx.com UG196 (v1.9) March 25, 2009

09/12/07 1.4 Revised maximum line rate from 3.2 Gb/s to 3.75 Gb/s in entire document.

Removed SAS standards from Table 1-1 and Table 5-3. Added notes to Table 5-3. Added note 2 to Figure 5-3, page 77. Added clarification to note 4 under Figure 5-5, page 79. Added notes to Table 5-6, page 81. Added bullet under “Link Idle Reset Support,” page 83. Clarified situations in Table 5-8, page 86 and added note 2 to Table 5-9, page 89. Replaced REFCLKPOWERDNB with REFCLKPWRDNB. Added notes to Figure 5-10, page 93.

Revised Figure 6-12, page 114. Increased CDR rate tolerance on page 141.

Revised Table 7-11, page 145.

Revised “Using the CRC Blocks” section including Figure 8-3 and adding Figure 8-4, page 198.

Changed specific banks for FF1136 and FF1738 in Table 10-17, page 229. Removed Optimal Cable Length section on page 248.

In Table D-1, page 291, revised PLL_DIVSEL_FB changed binary value for attribute value 5.

Added Figure E-1, page 321. Revised PMA + Interface in Table E-1, page 322 and Table E-2. Also revised Comma Alignment and Not Oversampling in Table E-2, page 323.

Added note to Figure F-2, page 327.

12/11/07 1.5 Made minor copy-edits. Added new reference in Preface [Ref 1] and revised others. Fixed directions of MGTRXN/MGTRXP and MGTTXN/MGTTXP ports in Table 1-2, page 27. Corrected domain of RXELECIDLE port in Table 1-3, page 28 and Table 7-5, page 136. Added summary tables of CRC ports (Table 1-4, page 36) and CRC attributes (Table 1-6, page 43). Corrected GTP_DUAL placement for XC5VSX50T in Figure 4-3, page 61. Added four LXT packages to Chapter 4: XC5VLX20T-FF323, XC5VLX30T-FF323, XC5VLX155T-FF1136, and XC5VLX155T-FF1738. Added statement about needing a stable reference clock to “After Turning on a Reference Clock,” page 87. Corrected arrow directions in Figure 6-9, page 108. Changed the number of TXUSRCLK2 clock cycles to wait in “Using the TX Phase-Alignment Circuit to Bypass the TX Buffer,” page 113. Changed the number of TXUSRCLK2 clock cycles in Figure 6-12, page 114. Revised Table 6-9, page 113 and added a new footnote. Inserted clock domain for TXENPRBSTST ports in Table 6-12, page 116. Reversed Boost On and Boost Off designations and adjusted default setting in Table 6-18, page 121. Rewrote last paragraph in “Differential Voltage Control,” page 120. Revised Example 6 values in Table 7-7, page 140. Updated Table 7-11, page 145. Changed PLL_CLKDIV_FB in Equation 7-6 to PLL_DIVSEL_FB. Revised Figure 7-11, page 155. Changed RX_BUFFER in “Enabling Clock Correction,” page 178 to RX_BUFFER_USE. Revised Slave Elastic Buffer contents in Figure 7-33, page 187. Added footnote to Table 10-1, page 207. Added “Boundary-Scan Testing Guidelines,” page 222. Revised first bullet under “Unused and Partially Used GTP_DUAL Column Guidelines,” page 223. Added XC5VLX155T to the footnotes in Table 10-20, page 231 and Table 10-21, page 231. Added new subsection “FPGA Logic Interface,” page 275. Updated Table A-12, page 276 and added three footnotes. Updated latencies in Table E-1, page 322 and Table E-2, page 323. Added “Index,” page 329.

02/11/08 1.6 Made minor copy-edits. Updated links to Xilinx website. Revised bullets in PCI Express and OC-12/48 protocol descriptions in Table 1-1, page 23. Revised Figure 5-1, page 68. Updated conditions for Equation 5-1. Updated PLLPOWERDOWN and TXDETECTRX descriptions in Table 5-6, page 81. Corrected arrow direction in Figure 6-2, page 100, Figure 6-3, page 100, Figure 7-34, page 190, and Figure 7-35, page 190. Rewrote “Boundary-Scan Testing Guidelines,” page 222 and “Unused and Partially Used GTP_DUAL Column Guidelines,” page 223.




UG196 (v1.9) March 25, 2009 www.xilinx.com Virtex-5 FPGA RocketIO GTP Transceiver

09/23/08 1.7 Added 3G-SDI to Table 1-1, page 23 and Table 5-3, page 71. Revised RXPRBSERR port description in Table 1-3, page 28 and Table 7-18, page 153 to equals or exceeds. Corrected direction of RXVALID to Out in Table 7-5, page 136. Revised PRBS_ERR_THRESHOLD attribute description in Table 7-19, page 153 to equals or exceeds. Corrected the overflow and underflow encodings of RXBUFSTATUS in Table 7-28, page 168 and Table 7-30, page 175. In Table 10-5, page 223, renamed table title, corrected power supply names, and added MGTRREF. Added note about BGA adjacency guidelines to “SelectIO to GTP Crosstalk Guidelines,” page 229.

11/10/08 1.8 • Added table note 1 to Table 1-1, page 23 on spread-spectrum clocking. • Added SIM_MODE attribute to Table 1-5, page 36 and Table 3-1, page 48. • Added “SIM_MODE,” page 49. • Added table note 6 to Table 5-3, page 71. • Added RXRESET as a recommended reset to the “After connecting RXN/RXP” row

in Table 5-8, page 86 and to “After Connecting RXP/RXN,” page 87. • Changed “power control” to “power down” throughout “Generic GTP_DUAL

Power-Down Capabilities,” page 90. • Removed Relative Power Savings and Recovery Time columns from Table 5-11,

page 91. In Table 6-4, page 106, corrected encoding of TXKERR and TXRUNDISP and defined them based on the interface width.

• Revised “TXINHIBIT,” page 122. • Added paragraph about PLL_RXDIVSEL_OUT to “Normal Operation Mode,” page

144. • Added table note 4 to Table 7-11, page 145. • Revised bits [23:16] and table note in Table 7-12, page 146.• Added note above Figure 10-2, page 210.• Updated Figure 10-2. • Added Figure 10-3, page 210 and associated note. • Added three bulleted notes under Figure 10-4, page 211. • Renamed “Unused and Partially Used GTP_DUAL Column Guidelines,” page 223. • Rewrote “Partially used GTP_DUAL column,” page 223. • In Table 10-6, page 223, updated table note 1 and added table note 2.

12/01/08 1.8.1 Corrected Section 1 header.

03/25/09 1.9 • In Chapter 10, added new sections “Resistor Calibration Circuit” on page 208 and “Power Supply Design and Filtering” on page 213.

• Revised “Providing Power” on page 217 in Chapter 10.




Virtex-5 FPGA RocketIO GTP Transceiver www.xilinx.com UG196 (v1.9) March 25, 2009www.BDTIC.com/XILINX


Virtex-5 FPGA RocketIO GTP Transceiver www.xilinx.com 7UG196 (v1.9) March 25, 2009

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Section 1: FPGA Level Design

Chapter 1: Introduction to the RocketIO GTP TransceiverOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 2: RocketIO GTP Transceiver Wizard

Chapter 3: SimulationOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49SmartModel Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SIM_GTPRESET_SPEEDUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49SIM_MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49SIM_PLL_PERDIV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49SIM_RECEIVER_DETECT_PASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power-Up and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Link Idle Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Providing Clocks in Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Defining GSR/GTS in a Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Simulation Environment Setup Example (ModelSim SE 6.1d on Linux) . . . . . . . . . . 52SIM_PLL_PERDIV2 Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Example for PCI Express Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Example for Gigabit Ethernet Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Example for XAUI Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table of Contents



8 www.xilinx.com Virtex-5 FPGA RocketIO GTP TransceiverUG196 (v1.9) March 25, 2009

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Chapter 4: ImplementationOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Example of a UCF for GTP_DUAL Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Package Placement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Chapter 5: Tile FeaturesTile Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Shared PMA PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Configuring the Shared PMA PLL for XAUI Operation . . . . . . . . . . . . . . . . . . . . . . . . . 72Configuring the Shared PMA PLL for OC-48 Operation . . . . . . . . . . . . . . . . . . . . . . . . 73Configuring the Shared PMA PLL for Gigabit Ethernet Operation . . . . . . . . . . . . . . . . 74Configuring the Shared PMA PLL for PCI Express Operation . . . . . . . . . . . . . . . . . . . . 75

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Clocking from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Clocking from a Neighboring GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Clocking using GREFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

GTP Reset in Response to Completion of Configuration . . . . . . . . . . . . . . . . . . . . . . . . 82GTP Reset When the GTPRESET Port is Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83GTP Component-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Link Idle Reset Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Resetting the GTP_DUAL Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Generic GTP_DUAL Power-Down Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Power-Down Features for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Power-Down Transition Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95





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Chapter 6: GTP Transmitter (TX)Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98


Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Connecting TXUSRCLK and TXUSRCLK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101TXOUTCLK Driving a GTP TX in 1-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101TXOUTCLK Driving GTP TX in 2-Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath . . . . . . . . . . . . . . . 103REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface. . . . . . . . . . . . . . 104

Configurable 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Enabling 8B/10B Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078B/10B Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107K Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088B/10B Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

TX Buffering, Phase Alignment, and Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . 109Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Using the TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Using the TX Phase-Alignment Circuit to Bypass the TX Buffer . . . . . . . . . . . . . . . . . 113Using the TX Phase-Alignment Circuit to Minimize TX Skew . . . . . . . . . . . . . . . . . . . 114

TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TX PRBS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Parallel In to Serial Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Configurable TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Differential Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122TXINHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Receive Detect Support for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 123Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123




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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

TX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Beacon Signaling for PCI Express Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127OOB Signaling for SATA Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Chapter 7: GTP Receiver (RX)Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129RX Termination and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Optional Built-in AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Configurable Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Configurable Termination Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Optional Configurable RX Linear Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

RX OOB/Beacon Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Detecting Electrical Idle for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Detecting OOB for SATA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140RX Clock Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141


CDR Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Tuning the CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Horizontal Sample Point Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Serial In to Parallel Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Configuring the 5x Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Configuring the PCS Internal Datapath and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Activating and Operating the Oversampling Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

PRBS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153




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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Configurable Comma Alignment and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154


Enabling Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Configuring Comma Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Activating Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Alignment Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Alignment Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Manual Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Configurable Loss-of-Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Configurable 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Enabling the 8B/10B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648B/10B Decoder Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164K Characters and 8B/10B Commas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165RX Running Disparity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Disparity Errors and Not-in-Table Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Configurable RX Elastic Buffer and Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . 167Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Using the RX Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Using RX Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Bypassing the RX Elastic Buffer while Using Built-in Oversampling . . . . . . . . . . . . . . 173

Configurable Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Enabling Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Setting RX Elastic Buffer Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Setting Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Clock Correction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Monitoring Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Configurable Channel Bonding (Lane Deskew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Enabling Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Channel Bonding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Connecting Channel Bonding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Setting the Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185Setting the Maximum Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Precedence between Channel Bonding and Clock Correction . . . . . . . . . . . . . . . . . . . 187

FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188




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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Configuring the Width of the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189Connecting RXUSRCLK and RXUSRCLK2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Chapter 8: Cyclic Redundancy CheckOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Using CRC for Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195The CRC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Using the CRC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Integrating the CRC Blocks for TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Integrating the CRC Blocks for RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Implementation of the CRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Chapter 9: LoopbackOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Near-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Near-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Far-End PMA Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Marginal Conditions and Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Far-End PCS Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Chapter 10: GTP-to-Board InterfaceAnalog Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Resistor Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208Power Supply Design and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Linear Regulator Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Regulator Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Ferrite Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Capacitor Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Filter Network Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Boundary-Scan Testing Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Providing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Partially Used Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Fully Unused Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Fully Used Column. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

REFCLK Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223




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GTP Reference Clock Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Sourcing More Than One Differential Clock Input Pair from One Oscillator . . . . . . . . 226Switching between Two Different Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 227AC Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Unused Reference Clock Inputs of GTP_DUAL Tiles for Clock Forwarding . . . . . . . . 227

Examples of Vendors and Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228SelectIO to GTP Crosstalk Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Section 2: Board Level Design

Chapter 11: Design Constraints OverviewPowering Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Power Distribution Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Regulator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Clock Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238External Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238SelectIO to Serial Transceiver Crosstalk Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Chapter 12: PCB Materials and TracesHow Fast is Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Trace Characteristic Impedance Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Chapter 13: Design of TransitionsExcess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251




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SMT Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255P/N Crossover Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Chapter 14: Guidelines and ExamplesSummary of Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263BGA Escape Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264HM-Zd Design Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Section 3: Appendices

Appendix A: MGT to GTP Transceiver Design MigrationOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Primary Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

MGTs per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Encoding Support and Clock Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273Other Minor Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275FPGA Logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Defining Clock Correction and Channel Bonding Sequences . . . . . . . . . . . . . . . . . . . 276RXSTATUS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Pre-emphasis, Differential Swing, and Equalization . . . . . . . . . . . . . . . . . . . . . . . . 277

Appendix B: OOB/Beacon SignalingOOB Signaling for SATA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Beacon Signaling for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP_DUAL TileDRP Address by Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293DRP Address by Bit Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308




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Appendix E: Low Latency DesignGTP TX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322GTP RX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Appendix F: Advanced ClockingExample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329




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Preface

About This Guide

This document shows how to use the RocketIO™ GTP transceivers in Virtex®-5 FPGAs. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5.

Guide ContentsThis manual contains the following chapters and appendices:

• “Section 1: FPGA Level Design”♦ Chapter 1, “Introduction to the RocketIO GTP Transceiver”

♦ Chapter 2, “RocketIO GTP Transceiver Wizard”

♦ Chapter 3, “Simulation”

♦ Chapter 4, “Implementation”

♦ Chapter 5, “Tile Features”

♦ Chapter 6, “GTP Transmitter (TX)”

♦ Chapter 7, “GTP Receiver (RX)”

♦ Chapter 8, “Cyclic Redundancy Check”

♦ Chapter 9, “Loopback”

♦ Chapter 10, “GTP-to-Board Interface”

• “Section 2: Board Level Design”♦ Chapter 11, “Design Constraints Overview”

♦ Chapter 12, “PCB Materials and Traces”

♦ Chapter 13, “Design of Transitions”

♦ Chapter 14, “Guidelines and Examples”

• “Section 3: Appendices”♦ Appendix A, “MGT to GTP Transceiver Design Migration”

♦ Appendix B, “OOB/Beacon Signaling”

♦ Appendix C, “8B/10B Valid Characters”

♦ Appendix D, “DRP Address Map of the GTP_DUAL Tile”

♦ Appendix E, “Low Latency Design”

♦ Appendix F, “Advanced Clocking”


http://www.xilinx.comhttp://www.xilinx.com/virtex5


Preface: About This GuideR

Additional DocumentationThe following documents are also available for download at http://www.xilinx.com/virtex5.

• Virtex-5 Family OverviewThe features and product selection of the Virtex-5 family are outlined in this overview.

• Virtex-5 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family.

• Virtex-5 FPGA User GuideThis user guide includes chapters on:

♦ Clocking Resources

♦ Clock Management Technology (CMT)

♦ Phase-Locked Loops (PLLs)

♦ Block RAM and FIFO memory

♦ Configurable Logic Blocks (CLBs)

♦ SelectIO™ Resources

♦ I/O Logic Resources

♦ Advanced I/O Logic Resources

• Virtex-5 FPGA RocketIO GTX Transceiver User GuideThis guide describes the RocketIO™ GTX transceivers available in the Virtex-5 TXT and FXT platforms.

• Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User GuideThis user guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, TXT, and FXT platform devices.

• Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express DesignsThis user guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT, and FXT platform devices for PCI Express® designs.

• Virtex-5 XtremeDSP Design ConsiderationsThis guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48E.

• Virtex-5 FPGA Configuration GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

• Virtex-5 FPGA System Monitor User GuideThe System Monitor functionality available in all the Virtex-5 devices is outlined in this guide.

• Virtex-5 FPGA Packaging and Pinout SpecificationThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.


http://www.xilinx.comhttp://www.xilinx.com/virtex5


Additional Support ResourcesR

The following documents provide supplemental material useful to this user guide:

1. Athavale, Abhijit and Carl Christensen. High-Speed Serial I/O Made Simple.http://www.xilinx.com/publications/books/serialio/serialio-book.pdf

2. Synthesis and Simulation Design Guidehttp://www.xilinx.com/support/software_manuals.htm

3. Granberg, Tom. Handbook of Digital Techniques for High-Speed Design. Prentice-Hall. ISBN-10: 0-13-142291-X. ISBN-13: 978-0131422919.

4. Grover, Frederick W., Ph.D. 1946. Inductance Calculations: Working Formulas and Tables. New York: D. Van Nostrand Company, Inc.

5. Johnson, Howard, Martin Graham. High-Speed Signal Propagation: Advanced Black Magic. Prentice-Hall. ISBN-10: 0-13-084408-X. ISBN-13: 978-0130844088.

6. Montrose, Mark I. 1999. EMC and the Printed Circuit Board. The Institute of Electrical and Electronics Engineers, Inc. ISBN 0-7803-4703-X.

7. Smith, Larry D. November 1984. Decoupling Capacitor Calculations for CMOS Circuits. Proceedings EPEP Conference.

8. Williams, Ross N. The Painless Guide to CRC Error Detection Algorithms.http://www.ross.net/crc/ (CRC pitstop).

9. DS083, Virtex-II Pro and Virtex-II Pro X Platform FPGAs Complete Data Sheet.

10. UG024, RocketIO Transceiver User Guide.

11. UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide.

12. XAPP209, IEEE 802.3 Cyclic Redundancy Check.

13. XAPP562, Configurable LocalLink CRC Reference Design.

14. UG351, Virtex-5 FPGA RocketIO Transceiver Signal Integrity Simulation Kit User Guide.

Additional Support ResourcesTo find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support/mysupport.htm.

Typographical ConventionsThis document uses the following typographical conventions. An example illustrates each convention.

Convention Meaning or Use Example

Italic font

References to other documents See the Virtex-5 Configuration Guide for more information.

Emphasis in text The address (F) is asserted after clock event 2.

Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex5


http://www.xilinx.com/virtex5http://www.xilinx.comhttp://www.xilinx.com/support/software_manuals.htmhttp://www.ross.net/crc/http://www.xilinx.com/support/documentation/data_sheets/ds083.pdfhttp://www.xilinx.com/support/documentation/boards_and_kits/ug024.pdfhttp://www.xilinx.com/support/documentation/user_guides/ug076.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp209.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp562.pdfhttp://www.xilinx.com/support/documentation/index.htmhttp://www.xilinx.com/publications/books/serialio/serialio-book.pdfhttp://www.xilinx.com/support/documentation/user_guides/ug351.pdfhttp://www.xilinx.com/support/mysupport.htm


Preface: About This GuideR

Online DocumentThe following conventions are used in this document:

Convention Meaning or Use Example

Blue text Cross-reference link to a location in the current document

See the section “Additional Documentation” for details.

Refer to “Clock Management Technology (CMT)” in Chapter 2 for details.

Blue, underlined text Hyperlink to a website (URL)Go to http://www.xilinx.com for the latest documentation.




R

Section 1: FPGA Level Design

This section provides the information needed to incorporate RocketIO™ GTP transceivers into an FPGA design, including:

• The features and characteristics of the GTP transceivers• How to use the RocketIO GTP Wizard to configure the transceivers• Mapping of transceiver instances to device resources• Simulation of GTP transceiver designs• Board-level clocking and power requirements

This section includes the following chapters:

“Introduction to the RocketIO GTP Transceiver”

“RocketIO GTP Transceiver Wizard”

“Simulation”

“Implementation”

“Tile Features”

“GTP Transmitter (TX)”

“GTP Receiver (RX)”

“Cyclic Redundancy Check”

“Loopback”

“GTP-to-Board Interface”




Section 1: FPGA Level DesignR




R

Chapter 1

Introduction to the RocketIO GTP Transceiver

OverviewThe RocketIO™ GTP transceiver is a power-efficient transceiver for Virtex®-5 FPGAs. The GTP transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:

• Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing, and coupling

• Programmable TX pre-emphasis and RX equalization for optimized signal integrity• Line rates from 100 Mb/s to 3.75 Gb/s, with optional 5x digital oversampling

required for rates between 100 Mb/s and 500 Mb/s

• Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel bonding, and clock correction

• Fixed latency modes for minimized, deterministic datapath latency• Beacon signaling for PCI Express® designs and Out-of-Band signaling including

COM signal support for SATA designs

The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref 1], which discusses high-speed serial transceiver technology and its applications.

Table 1-1 lists some of the standard protocols designers can implement using the GTP transceiver. The Xilinx CORE Generator™ tool includes a Wizard to automatically configure GTP transceivers to support one of these protocols or perform custom configuration (see Chapter 2, “RocketIO GTP Transceiver Wizard”).

Table 1-1: List of Standards Supported by the GTP_DUAL Tile

Protocols SupportedProtocol Data Rates

SupportedMiscellaneous Features

PCI Express, Rev. 1.0a

PCI Express, Rev. 1.1

2.5 Gb/s • TX receive detect• Loss of Signal (LOS)/Idle state detect• Low power states• Beacon signaling• Ground referenced termination

XAUI 802.3ae D5p0 3.125 Gb/s LOS

OC-12/48 622.08/2488.32 Mb/s Allow bypassing FIFOs for synchronous operation




Chapter 1: Introduction to the RocketIO GTP TransceiverR

GTP transceivers are placed as dual transceiver GTP_DUAL tiles in Virtex-5 LXT and SXT platform devices. This configuration allows two transceivers to share a single PLL with the TX and RX functions of both, reducing size and power consumption.

Figure 1-1 shows GTP_DUAL tile placement in an example Virtex-5 device (XC5VLX110T). All the GTP_DUAL tiles form a single GTP_DUAL column on the right side of the device as shown in Figure 1-1. Additional information on the functional blocks in Figure 1-1 is available in the following locations:

• Chapter 8, “Cyclic Redundancy Check,” provides more details on the CRC blocks in Figure 1-1.

• The Virtex-5 FPGA Configuration Guide provides more information on the Config and Clock, CMT, and I/O blocks.

• The Virtex-5 Embedded Tri-Mode Ethernet MAC User Guide provides detailed information on the Ethernet MAC.

• The Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs provides detailed information on PCI Express compliance.

FC-1, Rev. 4.0 1.0625 Gb/s Rate negotiation (allows operating the TX and RX at different speeds)

FC-2, Rev. 4.0 2.125 Gb/s

10GFC 3.1875 Gb/s

SDI

HD-SDI

DVB-ASI

3G-SDI

143/176/270/360 Mb/s

1.485/1.4835 Gb/s

270 Mb/s

2.970 Gb/s

10GBASE-CX4 802.3ak/D4.0 3.125 Gb/s

Gigabit Ethernet (1000BASE-CX 802.3z/D5.0)

1.25 Gb/s

SATA Generation 1/2, Rev. 1.0a

SATA Generation 2, Rev. 1.0a

1.5 Gb/s(1)

3.0 Gb/s

• Rate negotiation for Generation 2 (entire link operates at Generation 1/Generation 2 speeds)

• LOS• OOB beacon

Serial RapidIO 1.25/2.5/3.125 Gb/s

CPRI, Version 2.0 614.4/1228.8/2457.6 Mb/s

Infiniband (Volume 2, Release 1.1)

2.5 Gb/s

SFI-5 2.488 – 3.125 Gb/s Synchronous clocking (bypass FIFOs)

OBSAI RP3 (Spec. Issue 1.0) 768/1536/3072 Mb/s

Aurora 100 Mb/s – 3.75 Gb/s

Notes: 1. Spread-spectrum clocking (SSC) is only supported for line rates greater than 2 Gb/s.

Table 1-1: List of Standards Supported by the GTP_DUAL Tile (Continued)

Protocols SupportedProtocol Data Rates

SupportedMiscellaneous Features




OverviewR

Figure 1-1: GTP_DUAL Tile Inside the Virtex-5 XC5VLX110T FPGA

Virtex-5 FPGA (XC5VLX110T)

Configand

Clock

EthernetMAC

EthernetMAC

GTP_DUALX0_Y7

GTP_DUALX0_Y6

GTP_DUALX0_Y5

GTP_DUALX0_Y4

GTP_DUALX0_Y3

GTP_DUALX0_Y2

GTP_DUALX0_Y1

GTP_DUALX0_Y0

CMT

GTP_DUAL

Column

CMT

CMT

CMT

CMT

CMT

I/OColumn

I/OColumn

CRCBlocks

CRCBlocks

CRCBlocks

CRCBlocks

CRCBlocks

CRCBlocks

CRCBlocks

CRCBlocks

UG196_c1_01_120307

PCIExpress

Block

Notes: 1. This figure does not illustrate exact size, location, or scale of the functional blocks to each other. It does show the correct

number of available resources.2. To improve clarity, this figure does not show the CLB, DSP, and Block RAM columns.





Figure 1-2 shows a diagram of a GTP_DUAL tile, containing two GTP transceivers and a shared resources block. The GTP_DUAL tile is the HDL primitive used to operate GTP transceivers in the FPGA.

Figure 1-2: GTP_DUAL Tile Block Diagram

RX-PMA RX-PCS

GTP1

GTP0

GTP_DUAL Tile

FPGA PinsPackage Pins

Shared Resources

TX-PMA TX-PCS

UG196_c1_02_112107

RX-PMA RX-PCS

TX-PMA TX-PCS

SharedPMAPLL

PLL LockDetection

ResetControl

TXDATA0[15:0]TXBYPASS8B10B0[1:0]TXCHARISK0[1:0]TXCHARDISPMODE0[1:0]TXCHARDISPVAL0[1:0]

TXDATA1[15:0]TXBYPASS8B10B1[1:0]TXCHARISK1[1:0]TXCHARDISPMODE1[1:0]TXCHARDISPVAL1[1:0]

RXPOWERDOWN0[1:0]RXSTATUS0[2:0]RXDATA0[15:0]RXNOTINTABLE0[1:0]RXDISPERR0[1:0]RXCHARISCOMMA0[1:0]RXCHARISSK0[1:0]RXRUNDISP0[1:0]RXVALID0[1:0]

RXPOWERDOWN1[1:0]RXSTATUS1[2:0]RXDATA1[15:0]RXNOTINTABLE1[1:0]RXDISPERR1[1:0]RXCHARISCOMMA1[1:0]RXCHARISSK1[1:0]RXRUNDISP1[1:0]

TXOUTCLK0TXUSRCLK0TXUSRCLK20RXUSRCLK0RXUSRCLK20RXRECCLK0

CLKIN(1)

TXOUTCLK1

Data From

FP

GA

TXUSRCLK1TXUSRCLK21RXUSRCLK1RXUSRCLK21RXRECCLK1

Clocking

PowerControl DRP

TXP0MGTTXP0

TXN0MGTTXN0

RXP0MGTRXP0

RXN0MGTRXN0

TXP1MGTTXP1

TXN1MGTTXN1

RXP1MGTRXP1

RXN1MGTRXN1

AVTTTX

AVTTRX

AVTTTX

AVCC

AVCCPLL

AVCC

Data From

FP

GA

Data To F

PG

A

MGTAVCC

MGTAVCCPLL

MGTAVCC

MGTAVTTTX

MGTAVTTRX

MGTAVTTTX

Data To F

PG

A

RXVALID1[1:0]

GTP TX

GTP RX

GTP TX

GTP RX

7

6

6

7

4 5

3

21

Notes: 1. CLKIN is a simplification for a clock source. See Figure 5-3, page 77 for details on CLKIN.




Ports and AttributesR

The procedures for configuring and using each of the seven major blocks in the GTP_DUAL tile shown in Figure 1-2 are discussed in detail in these sections:

1. “Shared PMA PLL,” page 68 (Chapter 5)

2. “Reset,” page 80 (Chapter 5)

3. “Clocking,” page 76 (Chapter 5)

4. “Power Control,” page 89 (Chapter 5)

5. “Dynamic Reconfiguration Port,” page 95 (Chapter 5)

6. “GTP Transmitter (TX),” page 97 (Chapter 6)

7. “GTP Receiver (RX),” page 129 (Chapter 7)

Ports and AttributesThis section contains alphabetical tables of pins (Table 1-2), ports (Table 1-3 and Table 1-4), and attributes (Table 1-5 and Table 1-6). In all Port and Attribute tables in this guide, names that end with 0 are for the GTP0 transceiver on the tile, and names that end with 1 are for the GTP1 transceiver. Names that do not end with 0 or 1 are shared.

Table 1-2 lists alphabetically the signal names, directions, and descriptions of the GTP_DUAL analog pins and provides links to their detailed descriptions.

Table 1-2: GTP_DUAL Analog Pin Summary

Pin Dir Description Section (Page)

MGTAVCCPLL In

Analog supply for the shared PMA PLL, the clock routing, and the muxing network of the GTP_DUAL tile.

Analog Design Guidelines (page 207)

MGTAVTTRX InAnalog supply for the receiver circuits and the termination of the GTP_DUAL tile.


MGTAVTTRXC InAnalog supply for the resistor calibration and the standby circuit of the entire device.


MGTAVTTTX In

Analog supply for the transmitter termination and driver circuits of the GTP_DUAL tile.


MGTAVCC InAnalog supply for the internal analog circuits of the GTP_DUAL tile.


MGTREFCLKP

MGTREFCLKNIn

Differential clock input pin pair for the reference clock of the GTP_DUAL tile.


MGTRREF InReference resistor input for the entire device.






Table 1-3 lists alphabetically the signal names, clock domains, directions, and descriptions for the GTP_DUAL ports, and provides links to their detailed descriptions.

MGTRXN0

MGTRXP0

MGTRXN1

MGTRXP1

In (Pad)Differential complements forming a differential receiver input pair for each transceiver.

RX Termination and Equalization (page 131)

MGTTXN0

MGTTXP0

MGTTXN1

MGTTXP1

Out (Pad)

Differential complements forming a differential transmitter output pair for each transceiver.

Configurable TX Driver (page 120)

Table 1-2: GTP_DUAL Analog Pin Summary (Continued)

Pin Dir Description Section (Page)

Table 1-3: GTP_DUAL Port Summary

Port Dir Domain Description Section (Page)

CLKIN In AsyncReference clock input to the shared PMA PLL.

Shared PMA PLL (page 69), Clocking (page 78), Power Control (page 89)

DADDR[6:0] In DCLK DRP address bus.Dynamic Reconfiguration Port (page 95)

DCLK In N/A DRP interface clock.Dynamic Reconfiguration Port (page 95)

DEN In DCLK Enables DRP read or write operations.Dynamic Reconfiguration Port (page 95)

DI[15:0] In DCLKData bus for writing configuration data from the FPGA logic to the GTP_DUAL tile.

Dynamic Reconfiguration Port (page 95)

DO[15:0] Out DCLKData bus for reading configuration data from the GTP_DUAL tile to the FPGA logic.


DRDY Out DCLKIndicates the operation is complete for DRP write operations or data is valid for DRP read operations.


DWE In DCLKIndicates whether the DRP operation is a read or a write.


GTPRESET In AsyncStarts the full GTP_DUAL reset sequence.

Reset (page 81)

GTPTEST[3:0] In AsyncFactory test pins. Must be strapped Low for normal operation.





INTDATAWIDTH In Async

Sets the internal datapath width for the GTP_DUAL tile.

0: 8-bit internal datapath width

1: 10-bit internal datapath width

Shared PMA PLL (page 69), FPGA TX Interface (page 98), TX PRBS Generator (page 116), Parallel In to Serial Out (page 117), Serial In to Parallel Out (page 147), PRBS Detection (page 153), Configurable RX Elastic Buffer and Phase Alignment (page 168), Configurable Clock Correction (page 175), Configurable Channel Bonding (Lane Deskew) (page 181), FPGA RX Interface (page 188)

LOOPBACK0[2:0]

LOOPBACK1[2:0]In Async Sets the loopback mode. Loopback (page 202)

PHYSTATUS0

PHYSTATUS1Out Async

Indicates completion of several PHY functions, including power management state transitions and receiver detection.

Receive Detect Support for PCI Express Operation (page 123)

PLLLKDET Out AsyncIndicates that the VCO rate is within acceptable tolerances of the desired rate.

Shared PMA PLL (page 69)

PLLLKDETEN In Async Enables the PLL lock detector. Shared PMA PLL (page 69)

PLLPOWERDOWN In Async Powers down the shared PMA PLL. Reset (page 81), Power Control (page 89)

PRBSCNTRESET0

PRBSCNTRESET1In RXUSRCLK2 Resets the PRBS error counter. Reset (page 81), PRBS

Detection (page 153)

REFCLKOUT Out N/AProvides access to the reference clock provided to the shared PMA PLL (CLKIN).

Shared PMA PLL (page 69), Clocking (page 78), FPGA TX Interface (page 98), TX Buffering, Phase Alignment, and Buffer Bypass (page 111), FPGA RX Interface (page 188)

REFCLKPWRDNB In AsyncPowers down the GTP reference clock circuit (active Low).

Power Control (page 89)

RESETDONE0

RESETDONE1Out Async

Indicates when the GTP transceiver has finished reset and is ready for use.

Reset (page 81), RX Clock Data Recovery (page 141)

Table 1-3: GTP_DUAL Port Summary (Continued)






RXBUFRESET0

RXBUFRESET1In Async Resets the RX buffer logic.

Reset (page 81), Configurable RX Elastic Buffer and Phase Alignment (page 168), Configurable Clock Correction (page 175)

RXBUFSTATUS0[2:0]

RXBUFSTATUS1[2:0]Out RXUSRCLK2

Indicates the overflow/underflow status of the RX buffer.

Configurable RX Elastic Buffer and Phase Alignment (page 168), Configurable Clock Correction (page 175)

RXBYTEISALIGNED0

RXBYTEISALIGNED1Out RXUSRCLK2

Indicates if the parallel data stream is properly aligned on byte boundaries according to comma detection. When PCOMMA_ALIGN = TRUE, asserted for alignment to PCOMMA value. When MCOMMA_ALIGN = TRUE, asserted for alignment to MCOMMA value.

Configurable Comma Alignment and Detection (page 155)

RXBYTEREALIGN0

RXBYTEREALIGN1Out RXUSRCLK2

Indicates if the byte alignment within the serial data stream has changed due to a comma detection.


RXCDRRESET0

RXCDRRESET1In RXUSRCLK2

Reset for the RX CDR. Also resets the rest of the RX PCS.


RXCHANBONDSEQ0

RXCHANBONDSEQ1Out RXUSRCLK2

Indicates when RXDATA contains the start of a channel bonding sequence.

Configurable Channel Bonding (Lane Deskew) (page 181)

RXCHANISALIGNED0

RXCHANISALIGNED1Out RXUSRCLK2

Indicates if the channel is properly aligned with the master transceiver according to observed channel bonding sequences in the data stream.


RXCHANREALIGN0

RXCHANREALIGN1Out RXUSRCLK2

Held High for at least one cycle when the receiver has changed.


RXCHARISCOMMA0[1:0]

RXCHARISCOMMA1[1:0]Out RXUSRCLK2

Asserted when RXDATA is an 8B/10B comma.

Configurable 8B/10B Decoder (page 163)

RXCHARISK0[1:0]

RXCHARISK1[1:0]Out RXUSRCLK2

Asserted when RXDATA is an 8B/10B K character.


RXCHBONDI0[2:0]

RXCHBONDI1[2:0]In RXUSRCLK

FPGA channel bonding control. Used only by slaves.








RXCHBONDO0[2:0]

RXCHBONDO1[2:0]Out RXUSRCLK FPGA channel bonding control.


RXCLKCORCNT0[2:0]

RXCLKCORCNT1[2:0]Out RXUSRCLK2

Reports the status of the elastic buffer clock correction.

Configurable Clock Correction (page 175)

RXCOMMADET0

RXCOMMADET1Out RXUSRCLK2

Asserted when the comma alignment block detects a comma.


RXCOMMADETUSE0

RXCOMMADETUSE1In RXUSRCLK2

Activates the comma detection and alignment circuit.


RXDATA0

RXDATA1Out RXUSRCLK2

Receive data bus of the receive interface to the FPGA.

FPGA RX Interface (page 188)

RXDATAWIDTH0

RXDATAWIDTH1In RXUSRCLK2

Selects the width of the RXDATA receive data connection to the FPGA.

FPGA RX Interface (page 188)

RXDEC8B10BUSE0

RXDEC8B10BUSE1In RXUSRCLK2 Enables the 8B/10B decoder.


RXDISPERR0[1:0]

RXDISPERR1[1:0]Out RXUSRCLK2

Indicates if RXDATA was received with a disparity error.


RXELECIDLE0

RXELECIDLE1Out Async

Indicates the differential voltage between RXN and RXP dropped below the minimum threshold.

RX OOB/Beacon Signaling (page 136)

RXELECIDLERESET0

RXELECIDLERESET1In Async

Resets the RX Clock Data Recovery circuit, used by the mandatory Link Idle Reset circuit.


RXENCHANSYNC0

RXENCHANSYNC1In RXUSRCLK2 Enables channel bonding.


RXENELECIDLERESETB In AsyncEnables the RXELECIDLERESET inputs, used by the mandatory Link Idle Reset circuit (active Low).


RXENEQB0

RXENEQB1In Async Enables receiver equalization (active

Low).RX Termination and Equalization (page 131)

RXENMCOMMAALIGN0

RXENMCOMMAALIGN1In RXUSRCLK2 Aligns the byte boundary when comma

minus is detected.


RXENPCOMMAALIGN0

RXENPCOMMAALIGN1In RXUSRCLK2

Aligns the byte boundary when comma plus is detected.


RXENPRBSTST0[1:0]

RXENPRBSTST1[1:0]In RXUSRCLK2 Receiver test pattern checker control.

PRBS Detection (page 153)







RXENSAMPLEALIGN0

RXENSAMPLEALIGN1In RXUSRCLK2

When High, the 5x oversampler in the PCS continually adjusts its sample point. When Low, it samples only at the point that was active before the port went Low.

Oversampling (page 149)

RXEQMIX0[1:0]

RXEQMIX1[1:0]In Async

Sets the wideband/high-pass mix ratio for the RX equalizer.


RXEQPOLE0[3:0]

RXEQPOLE1[3:0]In Async

Sets high-pass filter pole location for the RX equalizer.


RXLOSSOFSYNC0[1:0]

RXLOSSOFSYNC1[1:0]Out RXUSRCLK2

FPGA status related to byte stream synchronization, depending on the state of the RX_LOSS_OF_SYNC_FSM attribute.

Configurable Loss-of-Sync State Machine (page 161)

RXNOTINTABLE0[1:0]

RXNOTINTABLE1[1:0]Out RXUSRCLK2

Indicates if RXDATA is the result of an illegal 8B/10B code and is in error.


RXOVERSAMPLEERR0

RXOVERSAMPLEERR1Out RXUSRCLK2

Indicates the FIFO in oversampling circuit has either overflowed or underflowed.

Oversampling (page 149)

RXPMASETPHASE0

RXPMASETPHASE1In RXUSRCLK2

Aligns the PMA receiver recovered clock with the PCS user clocks, allowing the RX elastic buffer to be bypassed.

Configurable RX Elastic Buffer and Phase Alignment (page 168)

RXPOLARITY0

RXPOLARITY1In RXUSRCLK2 Inverts the polarity of incoming data.

RX Polarity Control (page 1

Documents

Virtex-5 FPGA RocketIO GTP TransceiverVirtex-5 FPGA RocketIO GTP Transceiver UG196 (v1.9) March 25, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification