Vlsi Lab Manual(Microwind)

7/25/2019 Vlsi Lab Manual(Microwind)

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DEPARTMENT

OFELECTRONICS AND COMMUNICATION

ENGINEERING


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VLSI Laboratory

The students are required to design the schematic diagrams using CMOS logic and to

draw the layout diagrams to perform the following experiments using CMOS 130nm

Technology with necessary E! tools "Mentor #raphics$Tanner%&

List of Experimets!

1& esign and implementation of an in'erter

(& esign and implementation of uni'ersal gates

3& esign and implementation of full adder

)& esign and implementation of full su*tractor

+& esign and implementation of ,S-latch

.& esign and implementation of -latch

/& esign and implementation asynchronous counter

& esign and mplementation of static ,!M cell

2& esign and mplementation of differential amplifier

10& esign and mplementation of ring oscillator

E"#ipmet Re"#ire$!

1& Microwind3&1 and SC3 software-latest 'ersion

(& 4ersonal computer with necessary peripherals&


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DSC%&

DSC% is software for logic design& 5ased on primiti'es6 a hierarchical circuit can *e

*uilt and simulated& t also includes delay and power consumption e'aluation& 7ith the help

of this software one can implement digital circuits at its *asic gate primiti'es or at its

transistor le'el&

The following step *y step procedure gi'es you how to use this software to implement

circuits at transistor le'el&

1& To open the software dou*le clic8 on the SC3 icon on your des8top

t opens the default window as shown *elow


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(& To design the circuit6 select the necessary components which are shown in sym*ol

li*rary on right hand side and drag and drop on the wor8 area6 use *uttons for input

and 9E for output and also insert : and #; which are also part of sym*ol

li*rary as shown *elow&

3& Made the interconnections as per the circuit diagram using add a line option

)& ;ow to o*ser'e the functionality of the circuit6 run simulation using this icon


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7hen 9E glow6 it indicates a high output6 that


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After s#''essf#( 'omp(etio of 'ir'#it $esi)* +e +i(( )o for (ayo#t

$esi) #si) t,e s',emati' as refere'e i Mi'ro+i$ &-. soft+are too(-

T,e step by step pro'e$#re as fo((o+s

Mi'ro+i$ &-.

Mi'ro+i$ is a tool for designing and simulating circuits at layout le'el& The tool features

full editing facilities "copy6 cut6 past6 duplicate6 mo'e%6 'arious 'iews "MOS characteristics6

( cross section6 3 process 'iewer%6 and an analog simulator&


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1& To open the software dou*le clic8 on the microwind31 icon on your des8top

t opens the default window as shown *elow

On the right hand side it contains all the necessary layers used in layout design under palette

window&


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(& 5efore start designing the layout6 select the design rule file as follows6 flieselect

foundrychoose default&rul

3& To design an in'erter we need two transistors ;MOS and 4MOS6 a MOS transistor is

formed when a poly silicon layer is crossed with diffusion layer

)& The ploy silicon layer indicates gate terminal6 where the diffusion layer ends acts as

source and drain which are interchangea*le&

;ow the interconnections can *e completed *y using metal1 layer as shown


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+& ;ow to =oin different layers use contact cuts6 as gi'en in palette window&

.& ;ow add input to ploy layer6 *y choosing add pulse6 for output add a 'isi*le node at

drain-drain contact metal layer as shown *elow


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/& ;ow run the simulation *y using the icon


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LA/OUT DESIGN RULESN0 1e((r.2. Miim#m +i$t, .2 3

r.24 5et+ee +e((s .2 3

r..2 Miim#m +e(( Area .66 3 4

Diff#sior42. Miim#m N7 a$ P7 $iff#sio +i$t, 63

r424 5et+ee t+o P7 a$ N7 $iff#sios 63

r42& Extra N0+e(( after P7 $iff#sio 83


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r426 5et+ee N7 $iff#sio a$ 0+e(( 83

r4.2 Miim#m $iff#sio area .83 4

Po(ysi(i'o

r&2. Po(ysi(i'o 1i$t, 43

r&24 Po(ysi(i'o )ate o Diff#sio 43

r&29 Extra Po(ysi(i'o s#rro#$i) Diff#sio &3

r&26 5et+ee t+o Po(ysi(i'o boxes &3

Cota'tr62. Cota't +i$t, 43

r62& Extra $iff#sio s#rro#$i) 'ota't .3


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r626 Extra Po(y s#rro#$i) 'ota't .3

r62: Extra meta( s#rro#$i) 'ota't .3

Meta(r:2. 5et+ee t+o Meta(s 63

r:.2 Miim#m Meta( area .83 4


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Experimet ; .

CMOS INVERTER

AIM!To design and implement the layout of CMOS in'erter

SOFT1ARE TOOLS! SC3 "Schematic Editor%

MC,O7;3&1 "9ayout Editor%

LOGIC S/M5OL < TRUT% TA5LE!

CMOS CIRCUIT DIAGRAM!


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DSC%& SC%EMATIC!

MICRO1IND&-. LA/OUT!

DSC%& SC%EMATIC SIMULATION!


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MICRO1IND&-. LA/OUT SIMULATION!

RESULT!


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Experimet ; 4

UNIVERSAL GATES

AIM!esign and mplementation of >ni'ersal #ates



LOGIC S/M5OL* CMOS CIRCUIT DIAGRAM* TRUT% TA5LE!

DSC%& SC%EMATIC!

NAND NOR


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NAND NOR


NAND


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NOR


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NAND

NOR

RESULT!


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Exer'ise ; .

5ASIC GATES

AIM!esign and mplementation of 5asic #ates "!;6 O,6 E?-O,%




CMOS CIRCUIT DIAGRAM =AND GATE>!

DSC%& SC%EMATIC =AND GATE>!


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MICRO1IND&-. LA/OUT =AND GATE>!

DSC%& SC%EMATIC SIMULATION =AND GATE>!

MICRO1IND&-. LA/OUT SIMULATION =AND GATE>!


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CMOS CIRCUIT DIAGRAM =OR GATE>!

DSC%& SC%EMATIC =OR GATE>!

MICRO1IND&-. LA/OUT =OR GATE>!


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DSC%& SC%EMATIC SIMULATION =OR GATE>!

MICRO1IND&-. LA/OUT SIMULATION =OR GATE>!



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CMOS CIRCUIT DIAGRAM =E?0OR GATE>!

DSC%& SC%EMATIC =E?0OR GATE>!

MICRO1IND&-. LA/OUT =E?0OR GATE>!


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DSC%& SC%EMATIC SIMULATION =E?0OR GATE>!

MICRO1IND&-. LA/OUT SIMULATION =E?0OR GATE>!

RESULT!


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Exer'ise ; 4

%ALF ADDER

AIM!To design and implement the layout of half adder




INPUTSOUTPU

TS

A 5 CARR/

0 0 0

0 1 0

1 0 0

1 1 1

DSC%& SC%EMATIC!



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RESULT!

Experimet ; &

FULL ADDER

AIM!To design and implement the layout of full adder





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DSC%& SC%EMATIC!


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RESULT!

Experimet ; 6

FULL SU5TRACTOR

AIM!To design and implement the layout of full su*tractor




DSC%& SC%EMATIC!


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RESULT!

Experimet ; :

RS ; LATC%

AIM!To design and implement the layout of ,S-9atch




DSC%& SC%EMATIC!


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RESULT!

Experimet ; 8

D ; LATC%

AIM!To design and implement the layout of -9atch




DSC%& SC%EMATIC!


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RESULT!

Experimet ; 9

AS/NC%RONOUS COUNTER

AIM!To design and implement the layout of asynchronous counter




DSC%& SC%EMATIC!


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RESULT!

Experimet ; @

STATIC RAM CELL

AIM!To design and implement the layout of Static ,!M Cell




DSC%& SC%EMATIC!


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RESULT!

Experimet ;

DIFFERENTIAL AMPLIFIER

AIM!To design and implement the layout of ifferential !mplifier




DSC%& SC%EMATIC!


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RESULT!

Experimet ; .2

RING OSCILLATOR

AIM!To design and implement the layout of ,ing Oscillator




DSC%& SC%EMATIC!


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RESULT!

Documents

Vlsi Lab Manual(Microwind)