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VLSI-SoC’12 Technical Program Meeting. General Chair: Matthew Guthaus Program Chairs: Ayse Coskun, Andy Burg. Santa Cruz, 7 th October 2012, 17:00. Agenda. 17:00 – 17:15 Introduction 17:15 – 17:30 Program structure and statistics 17:30 – 18:15 Topic feedback for next year - PowerPoint PPT Presentation
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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VLSI-SoC’12 Technical Program Meeting
General Chair: Matthew Guthaus
Program Chairs: Ayse Coskun, Andy Burg
Santa Cruz, 7th October 2012, 17:00
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Agenda
17:00 – 17:15 Introduction17:15 – 17:30 Program structure and statistics 17:30 – 18:15 Topic feedback for next year18:15 – 18:30 Submission deadline for next year18:30 – 18:45 Procedure for selection of papers for the Springer book and best paper award (announced in the closing session of the conference)18:45 – 19:00 Any Other Business19:00 – Welcome apero
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Technical Program Committee• 12 technical tracks
• 8-10 members per topic (mostly 8), including 2 topic co-chairs
• In total 115 TPC topic members, including the 24 topic chairs
• 1 Special Session chairs and 1 PhD Forum chair
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Tracks• AMS Design• Bio-electronics/Bio-sensing• DSP-CAS• Digital VLSI/Memories• Emerging Techn./Devices• Interconnect/NoC
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• Low-Power/Thermal• Prototyping/Verification• Reconfigurable Systems• SoC/Embedded• Synthesis/Co-design• Variability/Test
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Technical Program Committee
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
TPC involvement
• TPC members did in general a very good work with few exceptions
• Regular papers were reviewed by at least 3 reviewers (average 4), with very few exceptions
• Submissions from TPC members: ~37
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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110 valid regular scientific papers have been submitted
excluding bogus and late submissions
13 submissions to 2 special sessions
20 papers submitted to the PhD forum (total)
Paper submissions (1)
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Paper submissions (2)Track 2012 2011Bio-elect./Bio-sensing 5 Microsensing 3DSP-CAS 13 18Digital VLSI/Memories 15 AMS Design 9 21Emerging Techn./Devices 1 3D, Phys.Des, EM mod. 6New Dev., MEMS, uSys 7Reconfigurable Systems 9 Synthesis/Co-design 2 Recon. Sys & Compilers 8Logic & HL Synth 6Interconnect/NoC 8 SoC/Embedded 12 Systems on Chip 32Embedded systems 4Variability/Test 19 20Low-Power/Thermal 10 12Prototyping/Verification 7 12
Focus more on electronics for biomedical
Provide a track for transistor-level digital, reduce load on AMS track
Stronger focus on emerging technologies with focus on devices rather than MEMS
Reduce load on SoC track by separating out interconnect
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Paper submissions (3)
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Paper selection Posters
Weighted average score > 0.4
Highest average score within posters: 1.0 with 1 exception (1.3)
Regular papers
Weighted average score > 1.0 with 3 exceptions (1x0.6, 2x0.8)
Highest weighted average score: 2.5
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Paper selection Regular papers
Initially 36 papers accepted and 19 posters, but 1 regular paper + 1 poster was withdrawn
Finally, 35 regular papers accepted and 18 posters Regular papers are published as 6-page long papers, and posters as 4-page short papers (Some complaints from authors)
Paper acceptance rate:
Regular papers : 31.8 % Regular + poster papers : 49.0 %
2 special sessions with 5/5 and 4/8 accepted (open submission)
19 PhD forum papers accepted (out of 20), but 2 withdrawn
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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PhD Forum Format: poster session (no paper)
Submission : 1 page abstract for review
Advertising: General call for PhD student papers (mildly successful as in prev. years): 5 submissions Separate invitation to authors of accepted papers to submit a PhD forum paper on “the general topic of their PhD research” (must be different from their paper, i.e., broader scope)
Total: 17 posters to be presented
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Technical Program Structure• 12 regular sessions with 45 papers in 2 parallel tracks
• 2 special sessions with 9 papers
• 2 poster sessions, with 18 posters combined with coffee breaks
• PhD forum with 17 posters
• 3 keynotes
• 1 embedded tutorial
• 1 panel
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Keynote Talks
• Yusuf Leblebici, EPFL, Director of Microelectronic Systems Laboratory– Designing 3D multiprocessor systems
• Luigi Capodieci, GLOBALFOUNDRIES, Director of DFM/CAD
– DFM, IC Scaling
• Erik Brunvand, University of Utah, Associate Professor
– Processor architectures for ray-tracing
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Special sessions(1) Memristive Computing
Organizer: Sung-Mo (Steve) Kang, UC Santa Cruz
• Fernando Corinto, Alon Ascoli and Marco Gilli. A novel elementary memristive system.
• Dmitri Strukov and Advait Madhavan. Mapping Image and Network Processing Tasks onto High-Throughput CMOL FPGA Circuits.
• Dmitri Strukov, Ligang Gao and Fabien Alibart. Analog-Input Analog-Weight Dot Product Operation with Ag/a-Si/Pt Memristive Devices.
• Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba and Yusuf Leblebici. GMS: Generic Memristive Structure Concept for 3-D FPGAs.
• Ravi Patel and Eby Friedman. Arithmetic Encoding for Memristive Multi-Bit Storage.
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Special Sessions(2) Open Source Tools and Methodologies for Research
Organizer: Jose Renau, UC Santa Cruz, USA•Niket Choudhary, Brandon Dwiel and Eric Rotenberg. A Physical Design Study of FabScalar-generated Superscalar Cores •Anton Tšepurov, Günter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik and Valentin Tihhomirov. A Scalable Model Based RTL Framework zamiaCAD for Static Analysis •Daniel Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao and Philip Brisk. A Digital Microfluidic Biochip Synthesis Framework
•Gregory Faust, Runjie Zhang, Kevin Skadron, Mircea Stan and Brett Meyer. ArchFP:
Rapid Prototyping of pre-RTL Floorplans
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Embedded Tutorial• Embedded Tutorial: Silicon Photonics Circuits and
Architectures for Many-Core Systems• Organizer: Ajay Joshi, Boston University, USA• Speakers:
Ajay Joshi, Boston University, USARon Ho, Oracle, USAMatthew Farrens, UC Davis, USA
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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PanelPanel Session: Analog VLSI Design at the End of CMOS Scaling: What is ahead?Organizer: Sergio Bampi, UFRGS, Brazil
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
Conference Stats• Registrations total: 103
– EUROPE 28– ASIA 13– MIDDLE EAST 4– NORTH AMERICA 50– SOUTH AMERICA 6– INDIA 2
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20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Best paper AwardSelection criterion: review score > 2.0
Candidates:
• Award to be announced during the closing session
• TPC members will vote and discuss during Wed. lunch.
• Printed forms available
Authors/Title Review Scores Averg TopicN. Di Spigna, D. Schinke, S. Jayanti, V. Misra and P. Franzon. A Novel Double Floating-Gate Unified Memory Device
2(3),3(3) 2.5Emerging technologies and new devices for
large-scale integration
J. Constantin, A. Dogan, O. Andersson, P. Meinerzhagen, J. N. Rodrigues, D. Atienza and A. Burg. An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
2(3),3(2),2(2) 2.3Reconfigurable systems, application specific processors, FPGAs (Architectures and Tools)
D. Sabena, M. Sonza Reorda and L. Sterpone. A new method for the automatic generation of optimized Software-Based Self-Test programs for VLIW processors.
3(2),2(2),2(3) 2.3Design for variability, reliability, fault tolerance,
and test
S. Kim and M. Guthaus. Dynamic Voltage Scaling for SEU-Tolerance in Low-Power Memories
3(4),1(3),2(2) 2.1Transistor-level digital VLSI circuits and
memories
20th IFIP/IEEE VLSI-SoC
Santa Cruz, CA USA,
October 7-10, 2012
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Submission Dates• Original submission deadline: April 1st • Postponed until May 3rd
due to low number of submissions
• Issue: collides with many other deadlines
• Postpone initial submission deadline?• Ask for early abstract submission / paper registration?
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