VLSI_1_A

Course Outline

((EEEE62056205) VLSI Design) VLSI Design

By Dr. Yaseer A. DurraniDept. of Electronics Engineering

University of Engineering & Technology, Taxila

Course Outline� Introduction to VLSI

� Back End

– IC Fabrication Process

� Front End

– CMOS Circuits Layout

– MOS Transistor Theory

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– Static & Dynamic Logic Circuits

– VLSI Embedded Systems

Reference Books� VLSI Design, H.C. M. Glesner

� VLSI Design Circuit Methodology, Liming Xiu

� The VLSI Handbook, Wai-Kai Chen

� Digital Design & Fabrication, V. G. Oklobdzija

� Modern VLSI Deisgn, Wayne Wolf

� CMOS VLSI Design 3rd Ed., Weste & Harris

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Grading policy� Assignments 08%

� Quizzes 12%

� Mid 20%

� Course Project/Case Studies 20%

� Final 40%

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Introduction to VLSI Design

(EE6205) VLSI Design(EE6205) VLSI Design

By Dr. Yaseer A. DurraniDept. of Electronics Engineering

University of Engineering & Technology, Taxila

5

Outline

� What is a VLSI Circuit?

� VLSI Challenges

� Major Approaches in VLSI

– ASIC, FPFA, PLD, PLA, PAL etc.

� Levels of Abstraction

� System on Chip Design

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� System on Chip Design

� Low Power Designs

What is a VLSI Circuit?

� Very Large Scale Integrated Circuit

� Process of integration of millions of transistors in a single chip

� VLSI design involves all aspects of creating in IC

•ƒ Integration of (mathematical expression) dx•ƒ Integration of (Transistors and complex logic gates)

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� VLSI design process is classified into 2 categories– Front End: Performs all aspects of design before

handing design over foundry for manufacture inGDSII (graphical design system II) format

– Back End: IC manufacturer (foundry) handles mostBack End tasks that are Mask generation, Waferprocessing, Testing, Delivery of samples, Finalmass production

What is a VLSI Circuit?� Many disciplines have contributed in VLSI design:

– Solid-State Physics– Material Science– Lithography & Fabrication– Device Modeling– Circuit Design & Layout– Architecture– Algorithms– CAD Tools

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– CAD Tools

Why VLSI?� Integration improves the design

– Lower parasitic = higher speed

– Lower power consumption

– Physically smaller

� Integration reduces manufacturing cost - (almost) no manual assembly

Era Date Complexity

(Number of logic blocks/chip)

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Single Transistor 1959 Less than 1

Unit Logic (one gate) 1960 1

Multi-function 1962 2-4

Complex Function 1964 5-20

Medium Scale Integration 1967 20-200

Large Scale Integration 1972 200-2000

Very Large Scale Integration 1978 2000-20000

Ultra Large Scale Integration 1989 20000-?

Giga Scale Integration Future ………

� Technology scaling doubled the number of devices in an IC(processors, FPGAs, …, etc) every 2-3 years

� Scaling also provided devices with reduced delay � frequencydoubling (with aggressive pipelining) � increased power density

� Increases in clock frequency slowed down (or stopped); availabledevices are used to create multi-processor (multi-core) processors

Why VLSI?

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Technology Trends� Processor

– Logic capacity increases ~ 30% per year

– Clock frequency increases ~ 20% per year

– Cost per function decreases ~20% per year

� Memory

– DRAM capacity: increases ~ 60% per year

(4x every 3 years)

– Speed: increases ~ 10% per year

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– Cost per bit: decreases ~25% per year

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35

Logic trans/cm2 6.2M 18M 39M 84M 180M 390M

Cost/trans (mc) 1.735 .580 .255 .110 .049 .022

#pads/chip 1867 2553 3492 4776 6532 8935

Clock (MHz) 1250 2100 3500 6000 10000 16900

Chip size (mm2) 340 430 520 620 750 900

Wiring levels 6-7 7 7-8 8-9 9 10

Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5

High-perf pow (W) 90 130 160 170 175 183

Productivity Gap

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complexity growth rate

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gap

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81

19

85

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89

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93

19

97

20

01

20

05

20

09

21% / Yr. compound

productivity growth rate

VLSI Design Challenge� Goal: Circuit design with increasing complexity with shorter times

� Medium of implementation: VLSI gives designer to control over almost everything:• Architecture, Logic Design, Speed, Area, Power, …

� Densities are increasing, costs decreasing with each passing year

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How to partition a

complex SoC design into

manageable blocks?

How to analyze &

How to check entire

design for localized

voltage drops?

How to calculate & fix

timing in presence of

VLSI Chip Design Issues

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reduce chip power

consumption?

How to ensure reliability

against electromigration

& hot electron effects?

timing in presence of

crosstalk and noise?

How to guarantee

manufacturability by

correct layout?

Source: Design Aids for Low Power, Jan M. Rabaey

IC Products� Processors

– CPU, DSP, Controllers� Memory chips

– RAM, ROM, EEPROM� Analog

– Mobile communication,audio/video processing

� Programmable– CPLD, PLA, PAL, FPGA

Medical

Point of Service

Home Automation

Wearable

Network sensors

Secondary displays

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– CPLD, PLA, PAL, FPGA� Embedded systems

– Used in cars, factories– Network cards

� System-on-Chip (SoC)

Distributed systems

Entertainment

Thin Client

PND

ConsumerRoboticsPortable media

Industrial Automation

Telematics

Thin Client

Printed Circuit Board (PCB)

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IC Design Alternatives

Standard Components Application Specific ICs

Fixed Application Application by

ProgrammingSemi

CustomSilicon

CompilationFull

Custom

Major Approaches in VLSI Design

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CompilationCustom

Logic FamiliesHardware

Programming(MASK)

SoftwareProgramming

TTL/CMOS

PLAROM

MicroprocessorEPROM,EEPROM

PLD


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Application-Specific Standard Product (ASSP)

Standard IC

(off the shelf)

ASIC(User-Specified)

SSI/MSI LSI/VLSI Semi-custom Full-custom

User-programmableStandard Digital/AnalogStandard


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User-programmable

PLDs FPGAs

StandardLibrary cells

Digital/AnalogMixed Signal

Standard ASICs

All Masks

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� IC that customized for a particular use, rather than intended for general-purpose use

� Modern ASICs often include entire uP, Memory including ROM, RAM,EEPROM, flash memory, Digital voice recorder etc.

� ASIC has grown from 5,000 gates to over 100 million

� Properties:

– Custom design, labor intensive, high volume opportunities, Standardparts for quick time to market applications, Economics of design,

Application-Specific Integrated Circuit (ASIC)

parts for quick time to market applications, Economics of design,Fast prototyping

� CAD Tools:

– System-level design: Concept to VHDL/C

– Physical design: VHDL/C to silicon

– Timing closure (Monterey, Magma, Synopsys, Cadence, Avant!)

� Design Strategies:

– Hierarchy, Regularity, Modularity, Locality

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Application Specific Standard Product (ASSP)� IC that implements a specific function that appeals to a wide market

� It combine a collection of functions & designed by or for one customer

� ASSPs are used in all industries, from automotive to communications

� Examples: Video and/or audio encoding and/or decoding

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Types of ASIC� Full-Custom ASICs:

– Custom-made from scratch for a specific application

– Their ultimate purpose is decided by the designer

– All the photolithographic layers of IC are already fully defined, leaving no

room for modification during manufacturing

� Semi-Custom ASICs:

– Partly customized to perform different functions within the field of their

general area of application

– Designers allowed some modification during manufacturing, although the

masks for diffused layers are already fully defined

� Platform ASICs:

– Designed & produced from defined set of methodologies, intellectual

properties & well-defined design of silicon that shortens the design cycle and

minimizes development costs

– Made from predefined platform slices, where each slice is a

premanufactured device, platform logic or entire system

– Premanufactured material reduces development costs

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Full Custom Design

Comp

Via

Metal2

I/O Pad

Macro Cell

� Engineers design manually some or all cells, circuits or layouts� Circuits are highly optimized for speed, area, or power� Design style is only suitable for very high performance circuitries

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A/D

PLA I/O

RAM

Metal1

Metal2

Glue Logic(Standard

Cell Design)

Macro CellDesign

� Users can select a desired platform based on their needs

� Offers high performance with characteristics of both ASIC & FPGA

� Verification costs can be significantly lower than ASIC because major functions

on platform might be preverified

� ASIC performance is better than platformed ASIC and it is better than FPGA

� Platform ASIC trades the high performance of ASIC with shorter time to market

& lower development cost. The platform ASIC approach is gaining momentum

due to its relatively lower cost as compared to an ASIC. But for very large

volume products, its unit cost could be higher than ASIC

Platform/Structured Design

volume products, its unit cost could be higher than ASIC

� Pre-designing processors like ARM or MIPs processors, clock, power

distribution & test structures

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� Group of transistor & interconnect that provides Boolean logic function(AND, OR, XOR, XNOR, buffer, inverter, flip-flop or latch)

� Utilization of functional blocks to achieve very high gate density andgood electrical performance

� Standard-cell design fits b/w Gate Array & Full Custom design

� Cell-based methodology makes it possible for one designer to focus onhigh-level (logical function) aspect of digital design, while anotherdesigner focuses on the implementation (physical) aspect

Standard-Cell Design

designer focuses on the implementation (physical) aspect

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Standard Cell Design

D C C B

A C C

CellMetal1Metal2

GNDVDD

Cell library

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A C C

D C D B

BCCC

C D

A B

Cell library

Standard Cell Library� Collection of Standard-Cells: These cells are realized as fixed-height, variable-

width full-custom cells, which enables them to be placed in rows, easing the

process of automated digital layout. The cells are typically optimized full-

custom layouts, which minimize delays and area

� Typical library contains two main components:

– Library Database - Consists of layout, schematic, symbol, abstract, and

other logical or simulation views

– Timing Abstract - Generally in Liberty format, to provide functional

definitions, timing, power, and noise information for each cell

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definitions, timing, power, and noise information for each cell

� Standard-cell library contain additional components:

– Full layout of the cells

– Spice models of the cells

– Verilog/VHDL models

– Parasitic Extraction model

– DRC/LVS rule decks

– Behavioral model

– Timing & Testing model

– Circuit Schematic

– Wire-load & Routing model

Physical

DesignTechnology

Mapping

Synthesis

IC Design Steps

SpecificationsHigh-level

DescriptionFunctionalDescription

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Packaging Fabri-cation

Placed& RoutedDesign

X=(AB*CD)+

(A+D)+(A(B+C))

Y = (A(B+C)+AC+

D+A(BC+D))

Gate-levelDesign

LogicDescription

Documents

VLSI_1_A