WAFFEN-UND KOSTUMKUNDE JOURNAL ISSN NO: 0042-9945 … · Vedic number juggling said on genetic Indian Vedas gives another enlargement figuring to finish fast increment. The Sutras

LOW POWER AND AREA EFFICIENT 64 BIT FLOATING POINT VEDIC MULTIPLIER DESIGN FOR

HIGH SPEED OPERATION IN DSP APPLICATIONS USING 90 NM TECHNOLOGY

1Pooja Krishnamurthy Revankar 2Dr H C Hadimani 3Dr Srinivasarao Udara

Department of E & C, G M Institute of Technology, Davangere, India

Department of E & C, G M Institute of Technology, Davangere, India

Department of E & C, S T J Institute of Technology, Ranebennur, India

[email protected] [email protected] [email protected]

Abstract

Any processor's execution is subject to three critical factors in particular speed, region and

power. A superior exchange off between these components makes the processor, a powerful one.

Multipliers are the normally utilized designs inside the processor. On the off chance that the

execution of these multipliers is enhanced then ground-breaking processors can be made in

future. In this paper, the proposed multiplier configuration in view of the sutra'Urdhva

Tiryakbhyam' of Vedic arithmetic is examined and the execution aftereffects of the multiplier are

contrasted and traditional multipliers. Vedic science is an antiquated arithmetic system which

depends on 16 sutras, gives unmistakable thoughts for getting arrangements easily. The design of

64 bit Vedic multiplier is done using Verilog the processes such as simulation and synthesis are

done using cadence tool using 45nm technology.

KEYWORDS: Vedic multiplier, 64bit, Verilog, Simulation, Synthesis, 45nm Technology

WAFFEN-UND KOSTUMKUNDE JOURNAL

Volume XI, Issue II, February/2020

ISSN NO: 0042-9945

Page No:121

INTRODUCTION

Multiplier is a basic practical square of a

chip since multiplication is should have been

performed over and again in every logical

computation. The quick what's more, low

power multipliers are required in minimal

size remote sensor frameworks and various

other DSP (Digital Signal Processing)

applications. They are furthermore used as a

piece of various figuring’s, for example,

FFT , DFT. There are two fundamental

increase techniques to be specific Booth

augmentation calculation and Array

duplication calculation utilized for the

outline of multipliers. The speed of increase

(and in addition control scattering) is

overwhelmingly controlled by the

engendering postponement of the full adders

and half adders utilized expansion fractional

items.

Handling applications is tremendously

diminished, signals spoken recurrence area.

Quick Fourier changes are all around

utilized for different application fields in

engineering, correspondence, and science.

These days, each procedure ought to be

quick and effective. Quick Fourier change is

a viable calculation to figure the 'n' point

DFT. this calculation has substantial scope

of uses in correspondence, signal and picture

handling, its Implementation needs

incredible number of complex increase

steps. So for our benefit and make the entire

technique straightforward and defer free, we

require an effective multiplier.

The most broadly utilized standard for

Binary gliding point calculation is the

Binary Floating Point IEEE754 Standard.

Skimming settles various portrayal issues.

Settled point is confined to a settled farthest

point which limits it from speaking to

expansive or little numbers additionally

separated; Settled point is bound to a settled

most distant point which limits it from

addressing sweeping or little numbers.

Furthermore when two tremendous numbers

are isolated, a settled point is displayed to

loss of precision.

Vedic number juggling said on genetic

Indian Vedas gives another enlargement

figuring to finish fast increment. The Sutras

UT and Nikilam Sutras give most clear

technique for mental estimation when

performing growth.

METHODOLOGY

The speed of a processor extraordinarily

relies upon its multiplier's execution. In this

undertaking, another approach is

investigated for the multiplier configuration

in view of old Vedic Mathematics. In Vedic

science, the computation of all the

incomplete items required for duplication is

acquired well ahead of time. These halfway

items are then included based the Vedic

Mathematics calculation to acquire the last

item.

UrdhvaTiryakbhyam sutra is known as

"vertically and across" and it is a general

increase recipe which can be connected to

all kind of duplication. The forte of this

sutra is that halfway item age and expansion

should be possible at the same time. It is

more effective in paired duplication and it is

appropriate for parallel handling which

thusly diminishes delay in an outline.

This sutra is for the most part utilized for the

augmentation of binary numbers and the

duplication equation can be relevant to a

wide range of increase. In Vedic multiplier

the calculation time is less when contrasted



ISSN NO: 0042-9945

Page No:122

and different multipliers and it is

autonomous of clock recurrence. Because of

its consistent acknowledged effectively

UrdhvaTiryakbhyam Sutra is a standout

amongst the most profoundly favored

calculations for performing duplication. The

calculation is sufficiently able to be utilized

for the increase of whole numbers and also

binary numbers.

UrdhvaTiryakbhyam Sutra:

"Urdhva-Tiryakbhyam"signifies "Vertically-

transversely" in Sanskrit. This duplication

system can be associated with all examples

of computation for N bit numbers. Urdhava-

Tiryakbhyam [UT Sutra] uses parallel

duplication and shows abnormal state of

parallelism appeared differently in relation

to other parallel multipliers. Ordinary

parallel duplication technique incomplete

items get summed up after the age of every

single fractional item. On account UT,

duplication vertically and across implies

summation will happens soon after

incomplete items a section produced.

Flow Chart of the Design

Figure 1.1: Vedic Multiplier Flowchart (2-

Bit )

Floating Point Multiplication:

For DSP applications, IEEE 754 drifting

point standard is generally utilized today.

The IEEE [Institute of Electrical and

Electronics Engineers] characterizes a

Standard for gliding point portrayal and

math. This IEEE754 standard is the broadly

acknowledged portrayal for drifting numbers

despite the fact that there are numerous

different portrayals.

Consider a skimming point number - 2.94

*103. The '- ' image shows the sign part of

the number, the '294' demonstrates the

critical digits of the number and finally the

'3' demonstrates the scalar factor segment of

the number. The noteworthy digits is named

as the mantissa of the number and scalar

factor is called as example of the number.

The general portrayal organize is of the

accompanying and is appeared in figure 3: (-

1) S* M * 2E (1) Where, S - Sign piece. M -

Mantissa bit E - Exponent bit.

Figure 1.2: IEEE-754 double

PrecisionFloating Point Pattern

Design Steps of Single Precision Floating

Point Multiplier



ISSN NO: 0042-9945

Page No:123

Figure 1.3: floating point multiplier diagram

PROPOSED VEDIC MULTIPLIER

The proposed design uses Vedic

mathematics based on UrdhvaTiryakabhyam

sutra for the multiplication of the mantissa

part in IEEE 754 single precision floating

point multiplication. In this proposed

multiplier the base block used as first stage

implementation is 3*3 block which is shown

in figure 1.1. Here we needs 64b it vedic

multiplier for the multiplication of mantissa

part. The 3*3 b lock consists of two half

adders, one full adder and three 2 bit adders

as shown in figure 1.1. From this 3*3 block,

6*6 multiplier block is designed. From this

6*6 multiplier block, 12*12 multiplier

blocks is designed and similarly from this

24*24 multiplier block, 64*64 multiplier

block is designed and implemented. These

blocks require Vedic multipliers and ripple

carry adders for getting the final output.

Implementation of 16x16 Bits Vedic

Multiplier

Figure 1.4:Implementation of 16x16 Bits

Vedic Multiplier

The 16X16 bit multiplier structured using

8X8 bits blocks as shown in Figure 6. In this

Figure the 16 bit multiplicand A can be

decomposed into pair of 8 bits AH-AL.

Similarly multiplicand B can be

decomposed into BH-BL. The outputs of

8X8 bit multipliers are added accordingly to

obtain the 32 bits final product. Thus, in the

final stage two adders are also required.

Implementation of 32x32 Bits

VedicMultiplier


Vedic Multiplier

The 32 bits multiplicand A is decomposed

into pair of 16 bits AH-AL. Similarly

multiplicand B can be decomposed into BH-

BL. The outputs of 16X16 bit multipliers are



ISSN NO: 0042-9945

Page No:124

added accordingly to obtain the 64 bits final

product. Thus, in the final stage two adders

are also required.

Implementation of 64x64 Bits Vedic

Multiplier


Vedic Multiplier.

The 64 bits multiplicand A is decomposed

into pair of 32 bits AH-AL. Similarly

multiplicand B can be decomposed into BH-

BL. The outputs of 32X32 bit multipliers are

added accordingly to obtain the 128 bits

final product. Thus, in the final stage two

adders are also required.

SIMULATIONRESULTS(Xilinx)

SCHEMATIC

INTERNAL SCHEMATIC



ISSN NO: 0042-9945

Page No:125

Using Xilinx Tool:

Synthesis results of 64 bit floating point

Vedic multiplier

The proposed work synthesis results carried

out from Cadence genus tool. In this current

design after verifying the simulation results,

it is necessary to get the synthesis results

which are useful for further digital

implementation of the 64 bit floating point

Vedic multiplier. By using this method the

number of adders was reduced when

compared with existing designs of

compressor based multipliers. The delay at

each stage has also been reduced. Hence, the

proposed multiplier shows substantial

improvement in area and power delay

product.

Name of the

Module Power (W) Area(µm) Timing(ns)

64 bit floating

point Vedic

multiplier

377.639 W

62

1500



ISSN NO: 0042-9945

Page No:126

Using Cadence Tool:

Figure 6.10 Showing complete synthesis

results with 64 bit multiplication

Comparisons of results:

CONCLUSION

The current design 64 bit manages the

outline of High speed coasting point Vedic

multiplier for FFT calculation. The benefits

of Vedic Multiplication over the ordinary

duplication procedures are examined. The

correlation between the two methods is

appeared in the outcome. From the outcome

we can find that the parameters like

territory, memory, CPU speed devoured by

Vedic augmentation procedure not as much

as the customary method. The proposed

Vedic augmentation technique is totally

unique in relation to traditional duplication

outline. Here bigger b locks are planned

from the littler pieces. The plan and

execution troubles for contributions of huge

number are diminished and seclusion is

expanded. UT from Vedic Mathematics is a

general augmentation recipe similarly

connected to instances duplication.

REFERENCES

[1] N.Pokhriyal, H. Kaur, H. & D. N. R

Prakash,. 2013. Compressor BasedArea-

Efficient Low-Power 8x8 Vedic

Multiplier. Int. Journal of Engineering

research and Applications, 3(6), pp.

1469-1472.

[2] L. Ciminiera and A. Valenzano, "Low

cost serial multipliers for high-speed

specializedprocessors," Computers and

Digital Techniques, IEE Proc.vol. 135.5,

1988, pp. 259-265.

[3] A.D.Booth, “A Signed Binary

Multiplication Technique,” J. mech. and

appl. math, vol 4,no.2, pp. 236-240,

Oxford University Press, 1951.

[4] C. R. Baugh, B. A. Wooley, “A Two’s

Complement Parallel Array

MultiplicationAlgorithm,”, IEEE Trans.

Computers 22(12), pp. 1045–1047, 1973.

[5]Koren Israel, ”Computer Arithmetic

Algorithms,” 2ndEd, pp. 141-149,

Universities Press,2001.

[6] L. Sriraman, T.N. Prabakar, “Design and

Implementation of Two Variable

Multiplier UsingKCM and Vedic

Mathematics,” 1stInt.Conf.on Recent

Advances in Information

Technology,Dhanbad, India, 2012, IEEE

Proc., pp. 782-787.

Acknowledgements

The authors would like to acknowledge the

funding received from the Department of

Name of the

Module Power (nw) Area(nm) Timing(fs)

64 bit

floating

point Vedic

multiplier

11957.907

145917

9141



ISSN NO: 0042-9945

Page No:127

science Technology (DST), Government of

India, through the Research center,

Department of Electronics and

Communication Engineering, STJIT-

Ranebennur. We also wish to acknowledge

special support from Prof.shivalingappa,

Department of Chemistry Engineering,

STJIT-Ranebennur, India for providing

Analyte solution and for coatings of the

cantilever and facility to measure different

parameters.

Ms.Pooja Krishnamurthy Revankar received

her B.E. degree in Electronics and

Communication Engineering (VTU,

Belagavi) from G M Institute of Technology

(GMIT), Davangere. Currently, she is

pursuing her M.Tech in Digital

Communication and Networking from

STJIT, Ranebennur. Her interests are

Wireless Networking and MEMS/NEMS

applications.

Dr. Srinivasarao. Udara received his

M.TechPh.Dfrom VTU, Belgaum. In 2005,

2019, he joined the Department of

Electronics Engineering at STJIT where he

is currently a Assistant professor. From

2005, he is working as co Project

development officer at STJIT. His research

interests are SoC design, MEMS/NEMS,

VLSI, Image processing, Development of

instruments for biomedical applications.

Dr. H C Hadimani received his M.Tech

from VTU, Belgaum. In 2001, he joined the

Department of Electronics Engineering at

GMIT where he is currently a professor.

From 2017, he is working as co Project

development officer at GMIT. His research

interests are SoC design, MEMS/NEMS,

VLSI, Image processing, Development of

instruments for communication systems.



ISSN NO: 0042-9945

Page No:128

Documents

WAFFEN-UND KOSTUMKUNDE JOURNAL ISSN NO: 0042-9945 … · Vedic number juggling said on genetic Indian Vedas gives another enlargement figuring to finish fast increment. The Sutras