Walking Pads: Fast Power-Supply Pad-Placement Optimization

Ke Wang∗, Brett H. Meyer†, Runjie Zhang∗, Kevin Skadron∗, and Mircea Stan‡∗Dept. of Computer Science

University of VirginiaCharlottesville, VA, 22904, USAkewang, runjie@virginia.edu,

skadron@cs.virginia.edu

†Dept. of Elec. and Comp. EngineeringMcGill University

Montreal, Quebec, H3A 0E9, Canadabrett.meyer@mcgill.ca

‡Dept. of Elec. and Comp. EngineeringUniversity of Virginia

Charlottesville, VA, 22904, USAmircea@virginia.edu

Abstract— We propose a novel C4 pad placement optimizationframework for 2D power delivery grids: Walking Pads (WP). WPoptimizes pad locations by moving pads according to the “virtualforces” exerted on them by other pads and current sources in thesystem. WP algorithms achieve the same IR drop as state-of-the-art techniques, but are up to 634X faster. We further propose ananalytical model relating pad count and IR drop for determiningthe optimal pad count for a given IR drop budget.

I. INTRODUCTION

In modern system-on-chip design, supply-voltage-noise in-duced reliability issues are becoming increasingly challeng-ing due to increasing current density [1]. Among the varioussources of voltage noise, IR drop refers to the resistive dropacross metal wires in the power delivery network (PDN). Typ-ical design rules tolerate an IR drop ratio no more than 5% ofsupply voltage; violations can lead to timing errors.

In a flip-chip design, because the underlying silicon chip hasa non-uniform power dissipation, the number and locations ofcontrolled-collapse-chip-connection (C4) pads connecting tothe on-chip PDN have a large impact on IR drop. Thus opti-mizing both the number and location of power supply C4 padsbecomes critical to guarantee the desired IR drop target. More-over, given the fact that both power supply and signal I/O sharethe same physical interface—C4 pads—determining the mini-mum number of power pads required for a given chip designthrough such optimization can help a designer to determine theavailable I/O bandwidth, or even perform tradeoffs between I/Obandwidth and the IR drop target.

Previous works have addressed pad placement optimizationfor the purpose of minimizing IR drop [2, 3, 4]. However, theirapproaches have scalability limitations, and as a result are notsuitable for the large pad placement design space of modernsystems. Some other works provide analytical methods to es-timate max IR drop when pad number and pad locations aregiven [5, 6]. To the best of our knowledge, no existing work in-vestigates the minimum number of C4 pads required to satisfya target IR drop in a 2D PDN grid.

In this paper, we propose a fast method to obtain the mini-mum pad number for a target IR drop and corresponding op-timized pad locations. First, we introduce a new method ofpower pad placement optimization, Walking Pads (WP). Thekey idea behind WP is to convert a global optimization prob-lem, the placement of n pads given m candidate locations, into

a local balance problem, the placement of individual pads (cur-rent sources) with respect to various nearby current demands.Treating pads as “mobile positive charges” and the on-chipPDN grid as a 2D electrostatic voltage field, WP optimizes padlocation by letting pads “walk” in the direction of the total vir-tual force exerted upon them to achieve local force balance.

WP achieves significant speedup over existing methods inthe literature because it has two significant advantages:

1. WP leverages the underlying voltage gradients to quicklyidentify promising pad locations.

2. WP allows all pads to step toward their balanced posi-tions simultaneously, reducing algorithm complexity sig-nificantly as a function of target pad count.

Second, we derive an analytical formula to describe the rela-tionship between IR drop and pad number based on optimizedpad locations. While not a closed-form model, our analyticalformula only requires that three coefficients be fit to a curve,and can identify the optimal pad count to within two pads forsystems with 128-1024 pads. When combined with WP, ouranalytical formula can quickly and accurately predict the min-imum required pad count.

This paper makes two principal contributions:1. We propose WP and demonstrate that it achieves at least

100X speedup with respect to the classical simulated an-nealing (SA) methods in the literature, while sacrificingno more than 0.1% VDD in steady-state IR drop.

2. We propose an analytical formula that describes the re-lationship between the number of pads and the expectedmaximum IR drop assuming optimized pad locations.

Together, the analytical model and WP algorithm are posi-tioned to significantly accelerate the optimization of power padcount and placement, and therefore create new opportunitiesfor joint optimization.

II. RELATED WORK

Sato et al. proposed the Successive Pad Assignment (SPA)method of power pad location optimization for pad ring alloca-tion [3]. Zhao et al. provided a solution of mixed integer linearprogram (MILP) for pad ring allocation [2]. The computationalcomplexities of both SPA and MILP grow quickly as problemsize increases. As a result, they are not tractable for largescale 2D C4 arrays. Zhong and Wong proposed a fast powerpad placement optimization algorithm within the framework ofsimulated annealing (SA) [4]. This method localizes the ef-

fect of pad movement using a node-based iterative method andtherefore improves the performance of each SA iteration. How-ever, the localization is based on the hypothesis that the volt-ages of pad-PDN connection points cannot affect each other.This is not true when the package circuit and pad resistanceare considered. Furthermore, their approach sacrifices accu-racy when accelerating calculations [4], and cannot work withother efficient numerical methods like preconditioned Krylovsubspace methods [7].

Shakeri proposed a theoretical method of accurate IR dropestimation for uniform power consumption floorplans with uni-formly distributed pads [5]. Rius extended this work to aclosed-form expression for non-uniform power consumptionfloorplans with arbitrary pad counts and locations [6]. How-ever, Rius’ work is based on the assumption that power padsare uniformly distributed on a rectangular 2D array. As shownin Section VII, IR drop is systematically overestimated in thiscase relative to the expected IR drop of optimally placed pads.

Walking Pads and the analytical model we have developed,unlike any prior work, enable designers to efficiently determinethe relationship between pad count and IR drop, and thereforeoptimal pad allocation. Such an approach is critical for pre-RTL design, as the number of pads required for power deliveryaffects the number of pads available for I/O, and therefore hasimplications for system architecture and microarchitecture.

III. PROBLEM FORMULATION

A. Power Delivery Network Model

The typical regularity of the on-chip PDN’s physical struc-ture makes compact PDN modeling feasible. A well acceptedmethodology models the multi-layer metal stack as a 2D re-sistor mesh [8]. C4 pads are modeled as individual resistorsattached to on-chip grid nodes, and the relative locations ofthose connection points in the grid represent the actual loca-tions of the C4 pads on the silicon die. Ideal current sourcesare used to model the load (i.e. switching transistors). Off-chipcomponents like the package or printed circuit board (PCB) arelumped into single resistors. To the best of our knowledge,lumped package models are adopted in most current relatedwork. We adopt this methodology and build the model skele-ton as in Fig. 1 [9]. We assume the PCB represents an idealpower supply and simultaneously model lumped package re-sistors, pad resistors and on-chip 2D resistor mesh; the steadystate equations we solve therefore capture not only the on-chip2D resistor mesh, but the package and pad resistors as well,with the latter elements changing as pads move from one can-didate location to another.

To solve for voltage and current values in the model cir-cuit, we employ sparse LU decomposition with pivoting, us-ing SuperLU [10]. A direct solver with pivoting is generallyconsidered a numerically stable and accurate method, and pro-tects optimization quality from numerical errors. When imple-mented using advanced reordering techniques [11], sparse LUreduces memory usage significantly and achieves adequate per-formance for use in our experiments. It is worth noting that theproposed Walking Pad algorithm framework is a high level op-timization framework, is thus not restricted to a particular nu-

Package

PDN GridVDD Pads

Silicon Die

VDD Pad

Candidate Pad Location

Fig. 1. Model of 2D PDN.

merical method, and can therefore take advantage of ongoingadvances in numerical methods [7, 12].

B. Power Pad Location Optimization

Given the system floorplan, the number of power pads toplace, and system power trace, the objective of power pad loca-tion optimization is to identify grid locations at which to placepads in order to minimize the maximum observed IR drop.The size of C4 bumps restricts the locations where they maybe placed. We assume that power pads can be allocated on acoarse pad grid that depends on the ratio of pad pitch and metalpitch. Each possible allocation of power pad to grid locationsis called a configuration. The total number of configurationsis the binomial coefficient of the number of pad locations andnumber of pads, and is larger than 10200 in the case studies con-sidered in this paper (and larger than 101400 for a scaled systemin Section VI.B). In this context, effective and computationallyefficient search techniques are needed to rapidly identify padallocations that achieve near-optimal IR drop.

IV. WALKING PADS

The key idea behind WP is to convert a global optimiza-tion problem, the placement of n pads given m candidate loca-tions, into a local balance problem, the placement of individualpads (current sources) with respect to various nearby currentdemands. To find the proper virtual force for local balance,we first observe that there is a similarity between the 2D PDNon-chip voltage field and a 2D electrostatic voltage field. Thesteady state equation of a voltage field can be regarded as thefinite-difference version of the 2D Poisson equation [5, 13]:

∂2V

∂x2+∂2V

∂y2= IxyR, (1)

where V is the on-chip voltage field, Ixy is the workload cur-rent density at point (x, y) and R is the resistance per unitlength in the x and y directions. Gauss’s law of electrostaticsystems can be similarly described [14]:

∂2V

∂x2+∂2V

∂y2=ρxyεxy

, (2)

where V is the electrostatic field, and ρxy and εxy are thecharge density and permittivity at point (x, y). Note that inthis paper we only consider the case where R is the same in thex and y directions; WP algorithms are also suitable if on-chipresistance is anisotropic.

When viewing pad placement as a 2D electrostatic voltagefield problem, the current in the PDN is analogous to the elec-tric flux lines in an electrostatic system, which are proportionalto the voltage gradient. In this way, power pads can be re-garded as “positive point charges” that source currents, andthe underlying architectural blocks in the processor system canbe regarded as “negative surface charges” that sink currents.Like charges repel each other, while unlike charges attract eachother. We therefore define the voltage gradient at a pad locationas the virtual force to direct pad movement.

In this context, Walking Pads allows pads to move in reac-tion to the forces exerted on them by current sources and otherpads in the PDN; the pads “walk,” toward the locations wherethese forces balance. No matter where the pads are placed, thetotal current through all pads is invariant. However, when padsreach their balanced positions, the gradient of the voltage field(directly proportional to the current) in each direction is equal-ized and reduced. Therefore, IR drop (the integral of voltagegradients) is minimized.

WP also minimizes max on-chip current density and PDNmetal power dissipation at the same time. On-chip max cur-rent always occurs in those wires directly connected to a pad;max on-chip current density is therefore also minimized by WPbecause WP minimizes the current through these wires. PDNmetal power dissipation is an analogue to the total energy of theelectrostatic system. Therefore, the PDN metal power dissipa-tion is also reduced when pads move under virtual forces, andis minimized when all forces on surface charges are balanced.

A. Walking Pads Algorithm Framework

An iteration of a Walking Pads algorithm uses three steps toincrementally move all pads toward their balanced positions:

1. Solve steady state equations.2. Calculate virtual forces and decide the direction and dis-

tance of movement for each pad based on total forces.3. Move pads.

Grid voltage and current values are determined in step 1. Instep 2, current values are used to guide pad movement. Step 3moves all pads simultaneously. WP achieves a significant per-formance improvement over SA by employing a deterministicapproach to the selection of pad movement direction and dis-tance in step 2 and allowing all pads to move simultaneously instep 3. As more optimization is achieved with each iteration,fewer iterations are needed.

B. Efficient Total Force Calculation

Once steady state current and voltages have been calculatedfor each node in the PDN, WP must determine in which direc-tion to move each pad by computing virtual forces.

A intuitive way to determine the total virtual force on eachpad is to apply the law of superposition and sum the contribu-tions of virtual force from all other pads and current sourcestogether. Some previous work uses this approach [15]. How-ever, such methods are inherently inefficient due to their com-plexity. Using Gauss’s Law, the force on a pad in one directioncan be calculated from the voltage gradient in that direction.In the case of 2D PDN, one pad connects to four lines in the

east, north, west and south directions. The resultant force is thevector summation of these four currents.

C. Walking Pads Algorithm Variants

We propose three variants of Walking Pads. The first, Walk-ing Pads - Neighbor (WP-N), only allows the pads to move toneighboring locations based on a comparison of the strengthof vertical and horizontal forces: the stronger force determinesthe direction the pad moves, either up/down or left/right. Be-cause all pads move at the same time and traverse a con-stant distance—one pad candidate location in the direction ofmotion—this algorithm results in the oscillation of pad loca-tions around balanced positions. In practice, WP-N regardsoscillation as convergence: when oscillation is detected, the al-gorithm terminates. As a result, WP-N does not perform well,but remains useful for quick, but low-quality, optimization.

The second variant, Walking Pads - Freezing (WP-F), isshown in Algorithm 1. WP-F allows pads to move in an arbi-trary direction defined by the normalized virtual force ~F/

∥∥∥~F∥∥∥.Large move distances are also adopted in early iterations. Toforce pads to stop at approximately balanced positions, we in-troduce a freezing process which gradually decreases the movedistance of each pad. The distance a pad moves Di decreaseswith the constant freezing rate γ. WP-F terminates when padsno longer move. The large-step stage of WP-F helps pads tojump out of local minima, while the small-step stage helps padsgradually freeze in their balanced positions.

Set: initial move distance D0, freezing rate γrepeat

Solve steady state;foreach pad do

~F = (Inorth − Isouth, Ieast − Iwest)

~Disp = ~F/∥∥∥~F∥∥∥ ∗Di

endDi+1 = Di ∗ γ

until check converge() == True;

Algorithm 1: Walking Pads - Freezing (WP-F) algorithm.

Walking Pads - Refined (WP-R), is shown in Algorithm 2.The first two versions of WP take advantage of the simultane-ous movements of all pads. Simultaneous movements reducethe quality of the solution to some extent, however, because theforces on one pad may change when other pads move. To ad-dress this, WP-R performs a greedy search: it moves pads oneby one and only accepts movements that decreases the max IRdrop. For a 2D grid, we assume that moving pads near the loca-tion of max IR drop has greater effect than moving distant ones.To improve efficiency, WP-R sorts the pads by their distancesto the max IR drop location and lets nearby pads move first.When the location or the value of maximum IR drop changes,WP-R re-sorts the pads and continues. The algorithm termi-nates when no pad movement improves IR drop. Because ofits algorithm complexity, WP-R is used to supplement WP-For WP-N to further improve the results when high optimizationquality is required.

Set: D0 = PadPitch, initial maxIRDroprepeat

Sort pads by distance to max IR place→ PadList;foreach pad in PadList do

~F = (Inorth − Isouth, Ieast − Iwest)

~Disp = ~F/∥∥∥~F∥∥∥ ∗D0

Solve steady state and get new maxIRDrop;if new maxIRDrop < maxIRRrop then

accept the movement;maxIRRrop = new maxIRDrop; break;

elsereject the movement;

endend

until check converge() == True;

Algorithm 2: Walking Pads - Refine (WP-R) algorithm.

D. Algorithm Complexity Analysis

The worst-case complexity of WP algorithms occurs whena pad must move from an initial position in one corner of thechip (e.g., the left-top corner) to a balanced position in the op-posite corner (e.g., the right-bottom). In this case, WP-N re-quires #gridrow + #gridcolumn − 2 iterations to converge.For the practical cases of randomly initialized pad positions,the average number of iterations required is on the order ofB0(#gridrow + #gridcolumn− 2)/#pad. B0 is larger than 1for the case that a pad does not move directly from its initial tothe balanced position (i.e., it takes a detour).

For WP-F, the convergence speed is controlled by freezingrate γ. The approximate traveling distance of one pad beforebeing frozen is (D0− 0.5pad pitch)/(1− γ), where D0 is theinitial move distance. Again, to beat the worst case, D0 and γare chosen to make the travel distance of each pad larger thanthe diagonal length of the grid. In our experiments, startingfrom roughly uniform pad locations results in much faster con-vergence than this theoretical upper bound. Detours are alsopossible in WP-F. In practice, we add a safety coefficient C0 inthe range of 2.0 ∼ 4.0 to balance the effect of detours and thespeedup due to uniform initial positions and get:

D0 − 0.5pad pitch

1− γ= C0 ∗

√#grid2row + #grid2column.

(3)We choose an initial move distance D0 = 3 ∗ pad pitch andfreezing rate γ = 0.99 for our case studies; this results in 180WP-F iterations. The total number of iterations required is in-dependent of the number of pads to be placed.

V. EXPERIMENTAL SETUP

To evaluate our WP algorithms, we compare their conver-gence speed and solution quality with the simulated annealing(SA) algorithm proposed by Zhong and Wong [4]. For SA, weevaluate two cooling rates, 0.98 (practical cooling speed, SA-P) and 0.999 (very slow cooling speed, SA-S) for efficiencyand quality comparison respectively; we have observed that thecooling rate of 0.85 proposed by Zhong and Wong is too fastto produce high-quality results. In our SA implementation, wemaximize the square of the worst node voltage and implement

the movement window shrinking strategy proposed in the liter-ature [4]. The SA algorithm is considered converged when themovement window is too small for pads to move.

We begin by comparing SA with WP-N and WP-F, and com-pare SA with WP-F+WP-R then. To compare WP-R and SA,we need to terminate WP-R iteration to get results of similarquality as those from SA, and then compare the speedup. Tocompare with SA-P and SA-S respectively, WP-F+WP-R-T1,terminates after #pad/2 iterations of WP-R, and WP-F+WP-R-T2 terminates after #pad*8 iterations of WP-R. These cutoffswere determined heuristically to yield similar quality.

We select a 24-core, Intel Penryn-like multiprocessor at16nm technology as the platform to evaluate the above opti-mization algorithms. To estimate the power consumption foreach functional block, we use McPAT, an architecture-levelpower model [16]. To model the worst-case power dissipa-tion in the system, we assume that each architectural unit dis-sipates 85% of its max power [17]. We assume a supply volt-age of 0.7V; architectural floorplans were generated using anarchitecture-level tool, ArchFP [18]. We assume that the topmetal pitch is 30µm top layer metal pitch, and that wires in thislayer are 6µmwide and 4µm thick; this results in a PDN modelconsisting of a 236 by 296 resistor grid, where each resistor hasa resistance of 41mΩ. We assume that the C4 pad pitch is 285µm, resulting in a grid with 2880 pad candidate locations forour 24-core system. According to ITRS projections, C4 paddensity will be held constant in the foreseeable future [19]; weadopt the ITRS projection for pad density in our experiments.All our experiments are conducted on an Intel Xeon E5-16503.20 GHz CPU with 32 GB memory.

VI. RESULTS

A. WP Speedup and Result Quality

We first compare two basic WP algorithms, WP-N and WP-F, with SA-P; the results of this comparison are illustrated inFig. 2. Fig. 2 plots algorithm convergence and solution qualityfor WP-F (dotted line), WP-N (dashed line), and SA-P (solidline) with respect to IR drop, max current density and powerconsumed in PDN metal; iteration count is plotted on the xaxis. We use iteration counts alone to compare the efficiency ofeach approach because solving for steady state voltage and cur-rent values—required by, and equivalent in, each approach—requires over 99.9% of the total time to complete a single itera-tion in each case. SA, WP-N, WP-F and WP-R have about thesame runtime per iteration and memory usage (approximately0.3s and 220MB for the case of 512 pads on 24-core floorplan).

In Fig. 2, VDD pads are initially allocated uniformly to ev-ery fourth pad candidate location in the vertical and horizontaldirections, representing 180 pads among 2880 pad candidatelocations. We summarize the IR drop (IR), max on-chip currentdensity (J), metal power dissipation (P) and required iteration(Iter) for each pad allocation method in Table I.

We observe that uniform pad allocation does not producegood results: SA reduces IR drop by 45% with respect to thatfrom uniform pad location. Furthermore, we observe that allthree algorithms jointly optimize all three metrics, if at differ-ent rates, and with differing effectiveness. WP-N converges the

TABLE ICOMPARISON OF DIFFERENT ALLOCATION METHODS

Method IR (% VDD) J (1010A/m2) P (W) Iter

Uniform 12.5 2.246 10.11 –WP-N 10.2 1.903 8.752 36WP-F 7.5 1.543 8.365 180SA-P 6.9 1.530 8.571 28,261

1 1 0 1 0 0 1 0 0 0 1 0 0 0 07 . 08 . 09 . 0

1 0 . 01 1 . 01 2 . 01 3 . 0

1 1 0 1 0 0 1 0 0 0 1 0 0 0 01 . 51 . 61 . 71 . 81 . 92 . 02 . 12 . 22 . 3

1 1 0 1 0 0 1 0 0 0 1 0 0 0 08 . 28 . 48 . 68 . 89 . 09 . 29 . 49 . 69 . 81 0 . 01 0 . 2

S A - P W P - F W P - N

PDN M

etal P

ower

Diss.

(W)

Max C

urr. D

ens.

(1010

A/m2 )

Worst

IR dr

op %

I t e r a t i o n s

Fig. 2. WP-F (dotted), WP-N (dashed) and SA (solid) all jointly optimize IRdrop, max current density and power dissipated in on-chip PDN metal, but atdifferent rates and with different effectiveness. In practice, the techniquesabove do not monotonically improve each figure of merit; for clarity, we plotthe results for the best explored configuration so far at a given iteration count.

fastest, finishing in 20% of the time required for WP-F; how-ever, WP-N converges too quickly to get high-quality results,resulting in an IR drop 48% higher than that produced by SA.WP-F only sacrifices 0.6% VDD in IR drop, but obtains a 157Xspeedup when compared with SA.

We next evaluate the effect of combining WP-F and WP-R toachieve better optimization quality. Fig. 3 plots the IR drop gapand convergence efficiency of WP-F, WP-F+WP-R-T1 (termi-nates after #pad/2), and SA-P for varying pad counts, relativeto the results from SA-S. The pad allocations selected by SA-Sare considered the global optimal and are used to evaluate theresult quality of other methods. SA-S, which cools at a rate of0.999 instead of 0.98, needs 3176×#pad iterations to convergewhile SA-P needs 157×#pad to converge.

In Table II we summarize the quality and speedup on a 24-core floorplan with 128 to 1024 pads. Four different WP strate-gies (WP Str.) - WP-F, WP-F+WP-R-T1 (F+R-T1, WP-R-T1 terminates at #pad/2), WP-F+WP-R-T2 (F+R-T2, WP-R-T2 terminates at #pad ∗ 8), and WP-F+WP-R (F+R, noearly termination), are investigated. WP-F achieves up to 893Xspeedup with respect to SA-P, but sacrifices too much qual-ity (0.54 %VDD). When refined with WP-R, WP-F+WP-R-T1

01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 0

1 2 8 1 9 2 2 5 6 3 2 0 3 8 4 4 4 8 5 1 2 5 7 6 6 4 0 7 0 4 7 6 8 8 3 2 8 9 6 9 6 0 1 0 2 40 . 0

0 . 5

1 . 0

1 . 5

2 . 0

2 . 5

3 . 0

Worst

IR Dr

op G

ap Pe

rcenta

ge (%

)

P a d N u m b e r

W P - F I R d r o p g a p % W P - F + W P - R - T 1 I R d r o p g a p % S A - P I R d r o p g a p %

Spee

dup

W P - F s p e e d u p W P - F + W P - R - T 1 s p e e d u p

Fig. 3. Comparision of Walking Pads and simulated annealing: differences inworst IR drop and speedup. WP-R-T1 terminates after #pad/2 iterations.

TABLE IICOMPARISON OF DIFFERENT WALKING PADS ALGORITHMS

WP Str. Speedup (X) Max Gap in %VDD

vs SA-P vs SA-S vs SA-P vs SA-S

WP-F 112-893 – 0.54 0.81F+R-T1 82-232 – 0.09 0.25F+R-T2 – 337-388 – 0.12F+R – 20-220 – 0.10

achieves up to 232X speedup with respect to SA-P, but pro-duces results matching those from SA-P with a gap less than0.1% VDD. We therefore think WP-F+WP-R-T1 can replaceSA-P to obtain optimized pad locations with practical quality.In the case of 832 pads, WP-F+WP-R-T1 requires less thanfour minutes to achieve results of comparable quality to SA-Pafter 15 hours. For the same reason, we think WP-F+WP-R-T2 can replace SA-S to obtain intensively optimized pad loca-tions with a speedup in the range of 337-388X. We have notcompared WP-F and WP-R-T1 with SA-S and WP-R-T2 andWP-R with SA-P.

B. Synthetic and Scaled System Benchmarks

To demonstrate that WP performs well under a variety ofscenarios, we developed a series of benchmarks including (a)six synthetic floorplans (Fig. 4) and (b) three variants of the24-core system with 16, 32, and 48 cores. Our results are sum-marized in Table III. For each benchmark (Bench.), we reportthe number of pads allocated (# pads), the number of candidatelocations (# loc), and the corresponding speedup (Speedup) ofWP-F (F), WP-F+WP-R-T1 (R-T1) and the IR drop gap (%Gap) of WP-F (F), WP-F+WP-R-T1 (R-T1) and WP-F+WP-R(R), each relative to SA-P. The IR drop gap between SA-P andWP is calculated as (IRWP − IRSA-P )/V DD. A negativegap means WP outperforms SA-P.

For the synthetic benchmarks, we observe that WP-F and

(a) Uniform(S-Uni)

(b) Half-half(S-HH)

(c) Checked(S-CB)

(d) 3-Level 1(S-TL1)

(e) 3-Level 2(S-TL1)

(f) 3-Level 3(S-TL1)

Fig. 4. The floorplan of each synthetic model is 20 x 20 mm2. 512 pads areallocated to deliver a total of 150 W. In (b), the power density ratio of black towhite is 4:1. In (d), (e) and (f) the power density ratio of black, gray and whiteis 3:2:1.

TABLE IIIWP RESULTS FOR SYNTHETIC AND MULTI-CORE MODELS

Bench. # pads # loc Speedup % Gap

F R-T1 F R-T1 R

S-Uni 512 4900 498 206 0.18 -0.03 -0.11S-HH 512 4900 498 206 0.23 -0.03 -0.11S-CB 512 4900 498 206 0.20 -0.06 -0.12S-TL1 512 4900 498 206 0.15 -0.03 -0.10S-TL2 512 4900 498 206 0.24 0.01 -0.12S-TL3 512 4900 498 206 0.19 -0.03 -0.1116-Core 512 1914 375 155 0.42 0.16 -0.0724-Core 768 2880 670 277 0.33 0.071 -0.0432-Core 1024 3844 961 397 0.41 0.070 -0.0748-Core 1536 5776 1536 634 0.39 0.055 -0.09

WP-R-T1 achieve a speedup of 498 and 206X relative to SA-P.WP-F and WP-R-T1 further achieve IR drops within 0.25% and0.01% of SA-P. For the Penryn-like variants, the speedup ad-vantage of WP-F and WP-R-T1 increases as the chip grows, upto 634X, and the IR drop gap for WP-R-T1 shrinks marginally;the IR drop gap for WP-F is relatively constant across chipsizes.

VII. ANALYTICAL MODEL

While the above results show that WP efficiently places agiven number of pads, naively determining the appropriate padcount to meet a given IR drop budget requires many WP exe-cutions, one for each pad count. We therefore developed an an-alytical model capable of predicting the appropriate pad count,significantly reducing the number of required WP executions.

Fig. 5 illustrates the relationship between pad count, IR drop,max current density and PDN metal power when pad locationsare optimized with WP-R. As the pad count increases, each ofthe three metrics decreases in a similar way.

To model the relationship between pad count and IR drop,we begin with several simplifying assumptions:

2 . 0

4 . 0

6 . 0

8 . 0

1 0 . 0

1 2 . 0

1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 1 1 0 01 . 02 . 03 . 04 . 05 . 06 . 07 . 08 . 09 . 0

1 0 . 0

W o r s t I R D r o p - 2 4 - C o r e W o r s t I R D r o p - 1 6 - C o r e W o r s t I R D r o p - S - C B M a x c u r r e n t d e n s i t y - 2 4 - C o r e M a x c u r r e n t d e n s i t y - 1 6 - C o r e M a x c u r r e n t d e n s i t y - S - C B P D N m e t a l p o w e r d i s s i p a t i o n - 2 4 - C o r e P D N m e t a l p o w e r d i s s i p a t i o n - 1 6 - C o r e P D N m e t a l p o w e r d i s s i p a t i o n - S - C B

P a d n u m b e r

Worst

IR Dr

op (%

)

0 . 20 . 40 . 60 . 81 . 01 . 21 . 41 . 61 . 82 . 02 . 2

Max on-chip current density (10 10A/m2)

PDN m

etal p

ower

dissip

ation

(W)

Fig. 5. Pad number effect on IR drop, max current density and PDN metalpower dissipation based on optimized pad locations. Optimization usesWP-F+WP-R (no early termination) and starts from randomly allocated pads.Points are plotted at a interval of 8 pads in this figure.

1. The load current density ρ is uniform.2. All pad currents are equal.3. Each pad serves a circular area around it with radius r0.

From Gauss’s Law we have:

∂V

∂r=πr20ρ− πr2ρ

2πr∗R. (4)

Integrating V from (rε) to r0, the IR drop at r0 is:

V |r0 =ρRr20

2lnr0rε−ρR

4(r20−r2ε)+

I0RpNp

+Vpackagedrop. (5)

where rε is the effective radius of pad, and R is the resis-tance per unit length of on-chip resistor grid. Substitutingr0 =

√I0

πρNpand substituting for the constant coefficients with

a, b, and c, we have:

Vdrop = a1

Nplog(

1

Np) + b

1

Np+ c. (6)

To validate Eq. (6), we performed curve fitting against the IRdrop data in Fig. 5, and find thatR2 = 0.998 and 0.9998 for the16-core and 24-core models respectively. Furthermore, whenused to derive max on-chip current density and PDN metalpower, fitting Eq. (6) results in R2 = 0.998 and 0.9999 respec-tively for the 16-core model, and R2 = 0.9995 and 0.99997respectively for the 24-core model. Eq. (6) clearly is effectiveat predicting each metric as a function of pad count.

To explore the predictive power of our analytical model, weselect four different IR drop budgets for the 24-core system,use Eq. (6) to estimate the appropriate number of pads, andcompare this with the minimum pad count satisfying the bud-get. The parameters of Eq. (6) are fitted using three randomlyselected pad counts: 200, 520, and 840. The results of thisexperiment are summarized in Table IV. We observe that thepredicted pad count (Pred.) is within two of the optimal padcount (Optimal) in each case. It is worth noting that even if all

TABLE IVPREDICTED AND OPTIMAL PAD COUNT FOR 24-CORE MODEL

IR Drop Budget Pred. Optimal Actual IR Drop

5%, 35mV 240 238 34.63mV4%, 28mV 304 306 27.97mV3%, 21mV 416 418 20.77mV2%, 14mV 673 672 13.99mV

pad counts in 128, 136, ..., 1024 are used for curve fitting,the predicted number of pads does not change.

While validating our analytical model, we noticed that thereis a significant difference between the worst-case IR drop ex-perienced under uniform pad distribution and that experiencedwhen pad locations are optimized. For example, the worst IRdrops with uniform pads allocations on a rectangular 2D arrayare 12.0%, 7.0% and 3.3% for the cases of 180, 320 and 720VDD pads in our 24-core model. The corresponding worst IRdrops with WP-optimized pad allocations are 6.6%, 3.8% and1.9% respectively. This suggests that previous analytical mod-els based on uniform pad allocations (e.g., [6]) systematicallyoverestimate worst-case IR drop.

VIII. CONCLUSIONS AND FUTURE WORK

In this paper we describe a fast method for determining theminimum number of pads required to satisfy an IR drop con-straint and their corresponding optimized locations. We intro-duce a novel pad placement optimization framework for 2Dgrids: Walking Pads (WP). Three algorithms are proposed inthe WP framework to meet the conflicting requirements ofresults quality and optimization time. The experimental re-sults show that combining the Walking Pads - Freezing (WP-F)and Walking Pads - Refined (WP-R) algorithms achieves up to634X speedup when compared with simulated annealing (SA),without sacrificing more than 0.1% VDD in IR drop. Our scal-ability test also shows that speedup and result quality of WP in-crease as the chip grows. We also propose an analytical modelto describe the relationship between the number of allocated,optimized pads and resulting IR drop. This model matches WPresults well and leads to fast minimum-pad-number determina-tion when working with WP algorithms.

In this paper we take the first step of demonstrating the vi-ability of the WP paradigm. There are several directions forfuture research using the WP framework: (1) The joint op-timization of VDD and GND pad placement should be con-sidered to make further IR drop optimization across both theVDD and GND layers; (2) Spatial constraints in the 2D padcandidate location grid should be considered in WP for theplacement of signal pads; (3) WP could be used to support IR-drop-aware floorplanning, by moving ‘negative charges’ (func-tional units or standard cells) instead of ‘positive changes’(power pads); (4) WP algorithms could be simply extended forthrough-silicon via (TSV) placement in 3D IC; (5) WP algo-rithms can be easily extended to temperature-aware placementby replacing the voltage field with a temperature field.

ACKNOWLEDGMENTS

This work was supported in part by NSF grants CNS-0916908, CCF-0903471 and CCF-1116673, and C-FAR, oneof six centers of STARnet, a Semiconductor Research Corpo-ration program sponsored by MARCO and DARPA.

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