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Issue 17Second Quarter 1995
GENERALFawcett: The New Reality... ..................... 2Guest Editorial: Curt Wozniak ................. 3Financial Results ...................................... 4Customer Success Story ........................... 5New Product Literature ............................ 6Upcoming Events ..................................... 6Development Systems Chart .................... 7Alliance Program Chart ............................ 8Alliance Contact Chart ............................. 9Component Availability Chart .............. 10Programming Support Charts:
XC7200, XC7300, XC1700 ............ 11-13
PRODUCTSNew XC4000 Speed Grade ................... 14Military Compliant Serial PROMs ......... 14XC5000 Family Grows .......................... 15New, Low-Power Version of XC7336 ... 16
DEVELOPMENT SYSTEMSXACTstep, version 6 Preview ........... 17-18Floorplanner Overview .................... 19-20Cadence Interface Announced .............. 20Upgrading to NeoCAD FPGA Foundry . 21Solaris Support Status ............................ 21HW-130 Universal Programmer ........... 22XC7000 EPLD Support from ISDATA .... 22
HINTS & ISSUESDesigning with HDLs and Synthesis 23-25Measuring Speed and Temperature ...... 25Board-Level Simulation .................... 26-27Configuration Checklist ........................ 27Questions & Answers ....................... 28-29Technical Support Facilities .................. 29Manchester Decoder in 3 CLBs ............ 303.3V Programmable Logic Market
Fax Back Survey .......................... 30-312Q95 Fax Response Form ..................... 32
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
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XCELLGENERAL FEATURES
PRODUCT INFORMATIONNew XC5000 FamilyMembers IntroducedThe new 2,500-gate XC5202 and 4,000-gate XC5204 provide lower-density,feature-rich FPGA solutions...
See Page 15
Xilinx, NeoCAD MergeXilinx President and Chief OperatingOfficer Curt Wozniak discusses Xilinx’sfounding vision and the importance of theXilinx-NeoCAD merger ...
See Page 2
DESIGN TIPS & HINTS
Manchester DecoderA high-speed, efficient serial decoder usingXilinx FPGAs uses eight-times oversamplingto ensure fast and accurate interpretation ofManchester-encoded data...
See page 30
is Coming!Powerful new features such as theFloorplanner make the latest release of theXACT Development System a revolutionarycombination of power and ease-of-use...
See Page 17
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FROM THE FAWCETT
Total Cost and Time-to-Volume:The New Reality
By BRADLY FAWCETT ◆◆◆◆◆ Editor
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XCELLPlease direct all inquiries,comments and submissions to:
Editor: Bradly Fawcett
Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]
©1995 Xilinx Inc.All rights reserved.
XCELL is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, UIM, HardWire and XACT-Performance are trademarks; and“The Programmable Logic Company”is a service mark of Xilinx, Inc. Allother trademarks are the property oftheir respective owners.
2
Continued on page 4
❝...determiningthe true “total cost” of agiven technology in a
given application is notat all a simple matter❞
While designers value the flexibilityand convenience of a user-programmabledevice, the programmable elements andtheir associated control logic do exact a
price in terms of siliconarea. Thus, program-mable devices generallycost more, on a per-piece basis, than equiva-lent-density custom andsemi-custom ICs, such asmasked gate arrays(although this gap isclosing).
The choice betweena high-density programmable device (anEPLD or FPGA) and a gate array oftencomes down to simple economics —designers want to use whichever one ismost cost-effective for the application.However, determining the true “total cost”of a given technologyin a given applicationis not at all a simplematter. If such ananalysis includes onlya comparison of unitprices at a given vol-ume, the “break-even”point between FPGAsand gate arrays typi-cally will be only afew hundred to a fewthousand pieces — even if the extra NRE(non-recurring charges) associated withsemicustom devices are amortized into thegate array price. But such an analysis fallsfar short of revealing the true cost of therespective technologies.
Many other factors affect technologycosts. These include development tool
costs, inventory costs, quality, vendorservice, future component price reduc-tions, design/market risks (i.e., will thedesign need to be modified after produc-tion shipments begin), and the potentialfor extra engineering and NRE costs dueto design re-spins. Many of these costscan go unrecognized in a traditional costanalysis because they occur after the de-sign cycle, or cut across many functionalgroups.
However, out of all the factors in-volved (including component costs), thetwo factors that tend to most heavilyweight the programmable device vs. gatearray cost analysis are engineering costsand time-to-market. In a typical scenario,studies suggest that these factors canmove the “break-even point” betweenFPGAs and gate arrays to tens or evenhundreds of thousands of units.
These factors aredirectly related. En-gineering costs arehigher and designcycles longer due tothe extra steps re-quired in semicustomIC development,especially exhaustivesimulation and testvector generation.This, combined with
the significantly longer lead times requiredto produce prototypes and productionquantities of gate arrays, can significantlyincrease the time-to-market for that prod-uct, as compared to a programmablesolution. As many studies have shown, intoday’s environment, even a small delay intime-to-market can have a significant
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R
GUEST EDITORIAL
3
The Xilinx-Neocad Mergerby CURT WOZNIAK ◆◆◆◆◆ President and Chief Operating Officer
The continued growth of the high-density, high-performance programmablelogic market is increasingly dependent upon the capabilities of the developmentsoftware. While continuing our efforts to make programmable logic devicesfaster, denser and less expensive, we also realize that the design softwareneeds to be easier to use, must provide more powerful design and debugcapabilities, and should be supplied to users in advance of device availability.
To help in the continuing efforts to achieve these goals, Xilinx recentlyannounced the acquisition of NeoCAD, Inc., a developer of high-performancedesign software for FPGAs. Combining our strength in FPGA and EPLD pro-grammable logic devices and process technologies with NeoCAD’s advancedFPGA software technology, this merger will provide Xilinx users with access toeven more powerful FPGA software design solutions. It is clear that NeoCADcan provide innovative technology that will accelerate software and hardwaredevelopment efforts in order to keep pace with user demands. This increased capa-bility will allow us to significantly enhance our industry-leading FPGA and EPLDsolutions and bring new solutions to market more quickly.
We now face the challenge of combining the best of both the Xilinx and NeoCADdevelopment system technologies. The next development system release from Xilinxand NeoCAD, XACTstep, version 6, and NeoCAD Foundry V7.0, respectively, willship as planned. We will continue to support all Xilinx and NeoCAD users withactive software maintenance agreements. Migration paths to allow current NeoCADusers access to the XACT solution and XACT users access to the NeoCAD softwarewill soon be established. (See related article, page 21.)
NeoCAD software will continue to be supported out of Boulder, Colorado. Theformer NeoCAD research and development team will remain in Boulder and com-prise the nucleus of the Xilinx Boulder research and development site.
NeoCAD’s software technology will be merged into future XACT releases to pro-vide a flexible, technology-independent methodology that enables us to quicklysupport current and emerging architectures. Equally important, the NeoCAD FPGAtechnology evaluation capability, whereby users can perform “what if” scenarios andselect the optimum device based on their cost, speed and density requirements, willalso be incorporated within the XACTstep software system. The development teamin Boulder will develop software jointly with other Xilinx development teams world-wide; we will leverage this team’s expertise and experience, and anticipate that theywill take a leadership role in driving our overall software direction.
Programmable logic users demand a wide range of architectures and program-ming technologies to satisfy their product needs, and software is a key enabler inthis regard. This merger underscores our continued commitment to provide a di-verse suite of programmable logic solutions. Our vision of the Xilinx-NeoCADmerger is that we can combine the best aspects of our technologies and the talentsof our employees to achieve a design system for our users that is the absolute bestin the industry. This is the vision on which Xilinx was founded. ◆
4
FINANCIAL REPORT
Record Revenue in Fiscal Year 1995Xilinx again achieved record revenues in fiscal
year 1995 (April 1994-March 1995), reflecting thestrength of our product line and the continued expan-sion of the programmable logic market. Fiscal 1995revenues totaled $355.1 million, an increase of 38percent over fiscal 1994.
For the fourth quarter (ending March 31, 1995),revenues reached a record $109.2 million, an increaseof 45 percent from the same quarter one year earlierand up 20 percent from the immediately precedingquarter. This revenue growth was driven by contin-ued demand for the high-speed XC3100, XC3100A andrichly-featured XC4000 FPGA families, along withrecord revenues for custom HardWire devices. Inter-
national revenues increased 49 percent from the pre-ceding quarter, contributing more than 30 percent oftotal revenues.
“Xilinx is well-positioned as we enter fiscal 1996.We intend to double our number of architecture offer-ings and, with the NeoCAD union, we will be able toprovide more powerful software solutions,” notedBernie Vonderschmitt, Xilinx CEO. “Looking forward,we remain optimistic about the overall growth of thehigh-density programmable logic market and our posi-tion within this market.”
Xilinx stock is traded on the NASDAQ exchangeunder stock symbol XLNX. ◆
speeding time-to-market. In higher volume,they can be directly replaced by less-expen-sive, mask-programmed HardWire devices,with no redesign effort or risk; engineeringresources are free to move on to the develop-ment of the next product.
Improving time-to-volume is the majorthrust of the upcoming XACTstep, version 6development system release. The focus is onaccelerating all phases of the product devel-opment flow: design entry, design implemen-tation (for the programmable logic), printedcircuit board design, design debug, and prod-uct production. (See related article on pages17-18.) Special attention has been paid tothe often-overlooked design debug stage;surveys indicate that more than 50 percent ofa designer’s time is spent in design debug andchange. So look for improved floorplanningtools and re-entrant “guide” options in PPR —to help ease the absorption of design changeslate in the development cycle — and im-proved timing analysis and hardware debug-ging tools. Our goal is to provide the toolsand technologies that will boost your produc-tivity, reduce your total cost and shorten yourtime-to-volume. ◆
impact on the overall profitability of a prod-uct. A late project’s “total cost” will often besubstantially higher than that of a projectcompleted quickly.
Yet, it may be more accurate to think interms of time-to-volume, rather than just time-to-market. Time-to-volume is a new term thatreflects a product’s total life cycle needs. Thekey is not only to get the product to market,but to quickly and seamlessly achieve re-quired volume production price points. Thisis one of the key philosophies behind theXilinx HardWire product line. FPGA devicescan be used for development, debugging,prototyping, and initial production, thus
THE FAWCETT Continued from page 2
Xilinx ASIC Estimator Available for PCCalculate the total cost of your project using Xilinx FPGAs,
FPGAs and Xilinx HardWire gate arrays, or traditional mask-pro-grammed ASICs. The Xilinx ASIC Estimator operates on IBM-com-patible computers and allows you to enter your own specific costs.Download it via the Internet at ftp://www.xilinx.com/pub/
utilities . The directory contains a readme.est file and theexecutable estimate.exe . You may also contact your localXilinx sales representative for a floppy disk copy. ◆
CUSTOMER SUCCESS STORY
5
155 Mbit/s Codec Uses Xilinx FPGAsThe Satellite Communications Re-
search Centre (SCRC) of the University ofSouth Australia in Adelaide is a spaceindustry development center sponsored bythe Australian Space Office.
In May of 1992, the SCRC secured acontract from Intelsat to build a 155 Mbit/scodec in a worldwide competitive bid.Intelsat is the world’s largest commercialsatellite communications service provider,owned by 120 member nations. The 155Mbit/s codec was the first major high tech-nology research and development contractawarded to an Australian institution.
The task was to develop and prototypea forward error correcting codec thatwould allow transmission of the standard155.52 Mbit/s broadband ISDN data rateover a 72 MHz satellite transponder. Theuse of Xilinx FPGA technology was key tosuccessfully implementing the codec.
After getting the contract, a group of sixengineers, nicknamed Team 155 and ledby Dr. Steven S. Pietrobon, spent the next18 months simulating, designing, building,and testing the codec. The key to thecodec was the efficient implementation ofa multi-dimensional trellis code. The en-coder that added the information requiredto implement the code was incorporated inan XC4002A. The decoder that removeserrors induced by noise in the channel ismuch more complicated and required twoXC4010s. However, this is still much lesscomplex than other coding schemes thatrequire up to nine ASICs or ECL gate ar-rays and provide inferior performance.
SCRC’s previous experience withXC3000 technology and the new featuresprovided by the XC4000 architecture (espe-cially the fast carry logic and on-chip RAMfeatures) allowed Team 155 to put thedecoder on two XC4010s in the time avail-able. A standard Reed Solomon code alsowas used. An XC4003 and XC4005 wereused to interface to available ReedSolomon codec chips and provide theinterleaving, de-interleaving, and synchro-
UNIVERSITY OFSOUTH AUSTRALIA
Trellis decoder card uses 2XC4010 FPGAs
nization functions of the codec.Viewlogic’s WorkView and PowerView
systems were both used for schematiccapture and functional simulation of theFPGA designs; simulation was used ex-tensively to test and debug the designbefore implementation. The use ofX-BLOXTM and the reprogrammability ofthe Xilinx chips allowed design changesand improvements to be easily made andtested. Xilinx extended support to Team155 by providing XC4010-5 devices(the fastest at the time)and the latestsoftware up-grades as theybecame available.This was espe-cially importantduring the accep-tance tests when thecodec was being testedwith the modem for thefirst time. The codec wasinitially not quite fastenough, resulting in mar-ginal performance. Usingrecently-arrived software,another route was performed,and a few hours later Team 155had a faster and accepted codec.
The resulting high-speed codecis capable of transmitting 155.520Megabits per second over interna-tional communication satellites. Previ-ously, undersea fiber-optic cableswere the only means for transmittinginformation internationally at this highdata rate.
The codec is currently being licensedto EF Data in Tempe, Arizona, where it isbeing incorporated into their modems.After delivery of the modems later thisyear, Intelsat will test this modem/codecwith the satellites. The prototype mo-dem/codec has already been successfullytested using a ground-based version oftheir satellites. ◆
6
New Product LiteratureLearn about the newest Xilinx products and services through our extensive library of
product literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative. ◆
TITLE DESCRIPTION PART NUMBER
CORPORATEHigh-Performance Computing Packet Application notes & brochure none
FPGAsHi-Rel XC3000 Family Data Sheet Technical Data Sheet #0010244-01XC1765D Data Sheet Technical Data Sheet #0010212-02
EPLDsEPLD Application Guide Application note & data sheets #0010237-01HW-130 Overview Features & benefits #0010245-01
DEVELOPMENT SYSTEMSXACTstep, version 6 Overview Features & benefits #0010101-04Floorplanner Overview Features & benefits #0010246-01Synopsys Interface Overview Features & benefits #0010154-05Viewlogic ProSeries Interface Overview Features & benefits #0010166-03Mentor Graphics Interface Overview Features & benefits #0010067-05Cadence Interface Overview Features & benefits #0010247-01
UPCOMING EVENTS
Look for Xilinx technical papers and/or product exhibits at these upcomingindustry forums. For further informa-tion about any of these conferences,please contact Kathleen Pizzo (Tel:408-879-5377 FAX: 408-879-4676). ◆
3rd Canadian Workshop on Field-Programmable Devices (FPD ’95)May 29 - June 1Montreal, Quebec, Canada
Designing PersonalCommunications ProductsJune 8-9: Seoul, KoreaJune 12-13: Taipei, TaiwanJune 15-16: Beijing, China
Electronic Design Automation & TestConference (EDA & T Asia)Aug. 21-22: Beijing, ChinaAug. 24-25: Seoul, KoreaAug. 28-29: Hsinshu, Taiwan
5th International Workshop on FieldProgrammable Logic (FPL ‘95)Aug. 29 - Sept. 1Oxford, United Kingdom
8th Annual IEEE ASICConference (ASIC ‘95)Sept. 18 - 22Austin, Texas
European Design AutomationConference (EURO-DAC ’95)Sept. 18 - 22Brighton, United Kingdom
32nd Design AutomationConference (DAC)June 12-16San Francisco, California
2nd GI/ITG Workshop onField Programmable DevicesJune 22 - 23Karlsruhe, Germany
PLD Conference, JapanJuly 19-21Tokyo, Japan
IC Card ExpoJuly 24-26Santa Clara, CA
New Edition of Xilinx Data BookBy the time you receive this issue of XCELL, a new revision of the Xilinx Program-
mable Logic Data Book will be available. Labeled the third edition, this new version hasbeen updated to include new products, such as the XC3100A-1 FPGAs and the latestpackage options for the XC4000 family devices.
New, more complete information that helps users to manage heat dissipation moreeffectively was also added. (See related article on page 25).
7
XILINX RELEASED SOFTWARE STATUS - MAY 1995PREVIOUS CURRENT VERSION BY PLATFORM
PRODUCT PRODUCT PRODUCT XILINX PART VER. PC1 SN2 AP1 HP7 LASTCATEGORY DESCRIPTION FUNCTION NUMBER REL. 6.2 4.1.X 10.4 9.01 UPDATE
XILINX INDIVIDUAL PRODUCTSCORE FPGA XC2,3,4K SUPPORT CORE IMPLEMENTATION DS-502-XXX 5.02 5.10 5.10 5.10 5.10 01/95CORE EPLD XC7K SUPPORT CORE IMPLEMENTATION DS-550-XXX 5.02 5.10 5.10 5.10 01/95FLOORPLANNER4 HI-DENSITY DES. KIT CORE IMPLEMENTATION ES-HD4K-SN2 N/A 5.10 N/AMENTOR2 A.1-F I/F AND LIBRARIES DS-344-XXX 5.02 5.11 1.10 5.11 05/95ORCAD2 I/F AND LIBRARIES DS-35-XXX 5.00 5.10 01/95SYNOPSYS2 I/F AND LIBRARIES DS-401-XXX 3.01B 3.20 3.01B 3.20 01/95VIEWLOGIC2 PROCAPTURE I/F AND LIBRARIES DS-390-XXX 5.02 5.11 05/95VIEWLOGIC2 PROSIM I/F AND LIBRARIES DS-290-XXX 5.02 5.11 05/95VIEWLOGIC2 I/F AND LIBRARIES DS-391-XXX 5.10 5.11 5.11 5.11 01/95XABEL2 ENTRY, SIM, LIB, OPT. DS-371-XXX 5.00 5.10 5.10 01/95X-BLOX1 MODULE GENERATION & OPT. DS-380-XXX 5.00 5.10 5.10 5.10 01/95VERILOG4 2K, 3K, 4K, 7K LIB. MODELS & XNF TRANS. ES-VERILOG-XXX 1.00 1.00 N/A
XILINX PACKAGESMENTOR 8 STANDARD DS-MN8-STD-XXX 5.02 5.10 1.10 5.10 01/95ORCAD BASE DS-OR-BAS-XXX 5.02 5.10 01/95ORCAD STANDARD DS-OR-STD-XXX 5.02 5.10 01/95SYNOPSYS STANDARD DS-SY-STD-XXX 2.00 5.10 2.00 5.10 01/95VIEWLOGIC BASE DS-VL-BAS-XXX 5.02 5.11 05/95VIEWLOGIC STANDARD DS-VL-STD-XXX 5.02 5.11 5.10 5.10 05/95VIEWLOGIC/S BASE DS-VLS-BAS-XXX 5.02 5.11 05/95VIEWLOGIC/S STANDARD DS-VLS-STD-XXX 5.02 5.11 05/95VIEWLOGIC/S EXTENDED3 DS-VLS-EXT-XXX 5.02 5.11 05/95XC5000 PRE-RLS.4 STANDARD CORE + VL LIBRARIES PR-VL-STD-XXX-5K N/A 1.00 1.00 N/A3RD PARTY STANDARD FPGA/EPLD CORE DS-3PA-STD-XXX N/A 5.10 5.10 5.10 N/A
XILINX HARDWARE
DEVICE PGMR. PROM/EPLD/XC8100 PGMR. HW-130 NEW 1.0 3Q95 - 3Q95 NEW
THIRD PARTY PRODUCTION SOFTWARE VERSIONSCADENCE COMPOSER SCHEMATIC ENTRY N/A 4.3 4.3.3 4.3.3 N/ACADENCE VERILOG SIMULATION N/A 2.1 2.1.2 2.1.2 N/ACADENCE (VALID) CONCEPT SCHEMATIC ENTRY N/A 1.7 1.7-P4 1.7-P4 N/ACADENCE (VALID) RAPIDSIM SIMULATION N/A 4.10 4.2 4.2 N/AMENTOR DESIGN ARCHITECT SCHEMATIC ENTRY N/A 8.2_5 A.1-F A.1-F A.1-F N/AMENTOR QUICKSIM II SIMULATION N/A 8.2_5 A.1-F A.1-F A.1-F N/AORCAD SDT 386+ SCHEMATIC ENTRY N/A 1.10 1.20 N/AORCAD VST 386+ SIMULATION N/A 1.10 1.20 N/ASYNOPSYS FPGA/DESIGN COMP. SYNTHESIS N/A 3.2a 3.2b 3.2b 3.2b N/AVIEWLOGIC PROCAPTURE SCHEMATIC ENTRY N/A 5.0 5.3 5.3 N/AVIEWLOGIC PROSIM SIMULATION N/A 5.0 5.3 5.3 N/ADATA I/O ABEL COMPILER ENTRY AND SIMULATION N/A 6.0 6.0 N/ADATA I/O SYNARIO ENTRY AND SIMULATION N/A 2.0 N/A
NOTE: 1FPGA Only 2FPGA and EPLD 3Includes ViewSynthesis v2.3.14Engineering software by request only
8
FPGA EPLD X-BLOXCOMPANY PRODUCT NAME VERSION FUNCTION DESIGN KIT SUPPORT SUPPORT SUPPORT
Acugen Sharpen 2.55 Automatic Test Generation AALCA interface ✓Sharpeye 2.55 Testability Analysis AALCA interface ✓
ALDEC/Susie-CAD Susie-Xilinx 2.0 Schematic Entry/Simulation Xilinx Design Kit ✓ ✓ ✓Active-Xilinx Schematic Entry/Simulation Xilinx Design Kit ✓ ✓ ✓
Aptix System Explorer 2.0 System Emulation Axess 2.0 ✓ASIC Explorer 2.0 ASIC Emulation Axess 2.0 ✓
Cadence (Valid) Concept 1.7-P4 Schematic Entry Xilinx Front End ✓ ✓Rapidsim 4.2 Simulation Xilinx Front End ✓ ✓Composer 4.3.3 Schematic Entry Xilinx Front End ✓ ✓Verilog 2.1.2 Simulation Xilinx Front End ✓ ✓FPGA Designer 3.3 Synthesis FPGA Synthesis ✓ ✓
Capilano DesignWorks 3.1 Schematic Entry/Simulation XD-1 ✓
Compass Asic Navigator Schematic Entry Xilinx Design Kit ✓QSim Simulation ✓X-Syn Synthesis ✓ ✓
CV (Prime) Design Entry 2.0 Schematic Entry Xilinx Kit ✓
Data I/O ABEL 6.0 Synthesis Xilinx Fitter ✓ ✓Synario 2.0 Schematic Entry, Synthe- Xilinx Fitter ✓ ✓ ✓
sis and SimulationEPS SIMETRI 2.0 Simulation XNF2SIM ✓
Escalade Design Book Design Entry ✓
Exemplar Logic CORE 2.2 Synthesis CORE ✓ ✓ ✓CORE/V-system 2.2 Simulation CORE/V-system ✓ ✓
Flynn Systems FS-ATG 2.6 Automatic Test Generation FS-High Density ✓
IBM-EDA Boole-Dozer Synthesis ✓
IK Technology G-DRAW 5.0 Schematic Entry GDL2XNF ✓G-LOG 4.03 Simulation XNF2GDL ✓
Ikos 2800/2900 5.16 Simulation Xilinx Tool Kit ✓Voyager 1.41 Simulation Xilinx Tool Kit ✓
Intergraph ACE Plus 12.2 Schematic Entry Xilinx FPGA Design Kit ✓ ✓AdvanSIM-1076 12.0 Simulation Xilinx FPGA Design Kit ✓ ✓VeriBest Sim 12.2 Simulation Xilinx FPGA Design Kit ✓ ✓EDM/DMM 12.3 Design Flow Manager Xilinx FPGA Design Kit ✓ ✓VeriBest Syn 12.2 Synthesis Xilinx FPGA Design Kit ✓Synovation 12.1 Synthesis SynLib ✓PLDSyn 12.0 Design entry, synthesis sim. included ✓ ✓
ISDATA LOG/iC2 4.1 Entry Xilinx Fitter ✓ ✓ ✓LOG/iC Classic 4.1 Synthesis, simulation ODC ✓
IST (Alpine Design) ASYL+ 3.0 Synthesis XNF interface ✓ ✓
ITS XNF2LAS 1a Lasar model gen. XNF2LAS ✓
Logic Modeling Smart Model Simulation Models In Smart Model Library ✓ ✓(Synopsys Division) LM1200 Hardware Modeler Xilinx Logic Module ✓ ✓
Logical Devices CUPL 4.5 Synthesis Xilinx Fitter ✓ ✓
Mentor Graphics QuickSim II 8.4 (A.x_F) Simulation Call Xilinx ✓ ✓ ✓Design Architect 8.4 (A.x_F) Schematic Entry Call Xilinx ✓ ✓ ✓Autologic 8.4 (A.x_F) Synthesis Xilinx Synthesis Library ✓ ✓ ✓
MINC PLDesigner-XL 3.3 Synthesis Xilinx Design Module ✓
Minelec Ulticap 1.32 Schematic Entry Xilinx Interface 2K,3KOrCAD SDT 386+ 1.2 Schematic Entry Call Xilinx ✓ ✓ ✓
VST 386+ 1.2 Simulation Call Xilinx ✓ ✓ ✓PLD 386+ 2.0 Synthesis Call OrCAD ✓
Protel Advanced Schematic 2.2 Schematic Entry Xilinx interface ✓ ✓
Quad Design Motive 4.0 Timing Analysis XNF2MTV ✓
Simucad Silos III 92.115 Simulation Included ✓
Sophia Systems Vanguard 5.31 Schematic Entry Xilinx I/F Kit ✓ ✓ ✓
Synopsys FPGA Compiler 3.2 Synthesis Call Xilinx 3K,4K ✓ ✓Design Compiler 3.2 Synthesis Call Xilinx ✓ ✓ ✓VSS 3.2 Simulation Call Xilinx ✓ ✓ ✓
ALLIANCE PROGRAM - COMPANIES & PRODUCTS - MAY 1995
Continued
9
FPGA EPLD X-BLOXCOMPANY PRODUCT NAME VERSION FUNCTION DESIGN KIT SUPPORT SUPPORT SUPPORT
ALLIANCE PROGRAM - COMPANIES & PRODUCTS - MAY 1995 (con’t)
Synplicity Synplify 2.5 Synthesis Synplify ✓ ✓
Teradyne Lasar 6 Simulation Xilinx I/F Kit ✓
Tokyo Electron ViewCAD 5.0502a FLDL to XNF XNFGEN ✓
Topdown Design V-BAK 1.1 XNF to VHDL translator XNF interface ✓
transEDA TransPRO 1.2 Synthesis Xilinx LIbrary ✓
VEDA Vulcan 4.5 Simulation Xilinx Tool Kit ✓
Viewlogic PROCapture 5.0 Schematic Entry Call Xilinx ✓ ✓ ✓PROSim 5.0 Simulation Call Xilinx ✓ ✓PROSynthesis 5.0 Synthesis Call Xilinx ✓ ✓ ✓
Viewpoint VitalBridge 1.0 Vital VHDL VHDL I/F kit ✓VeriLink 1.0 Verilog lib. back-annotation Verilog I/F kit ✓
Visual Software Solutions StateCAD 2.4 State diagram Xilinx fitter ✓
Zycad Paradigm XP Gate-level simulation ✓Paradigm RP Rapid prototyping ✓
PLATFORMCOMPANY CONTACT NAME PC SUN RS6000 HP7 PHONE NUMBER
Acugen Peter de Bruyn Kops ✓ ✓ ✓ 603-881-8821Aldec/Susie-CAD David Rinehart ✓ 702-293-2271Aptix Corporation Wolfgang Hoeflich ✓ ✓ 408-428-6200Cadence Itzhak Shapira Jr. ✓ ✓ ✓ 408-428-5739Capilano Computing Chris Dewhurst ✓ Macintosh 604-522-6200Compass Design Mahendra Jain ✓ 408-434-7950CV (Prime) Kevin O’Leary ✓ 617-275-1800Data I/O Dave Kohlmeier ✓ ✓ 206-881-6444EPS Michael Massa ✓ ✓ 617-487-9959Escalade Jerry Rau ✓ 408-481-1308Exemplar Logic Stan Ng ✓ ✓ ✓ 510-337-3700Flynn Systems Mike Jingozian ✓ 603-891-1111IBM-EDA John Orfitelli ✓ 914-433-9073IK Technology Hiroyuki Kataoka ✓ +81-3-3464-5551Ikos Brad Roberts ✓ ✓ 408-255-4567Intergraph Electronics Greg Akimoff ✓ ✓ ✓ 415-691-6541ISDATA Ralph Remme ✓ ✓ ✓ +49-721-751087IST Gabriele Saucier ✓ ✓ ✓ +33-76-70-51-00ITS Frank Meunier ✓ ✓ 508-897-0028Logic Modeling Laura Horsey ✓ ✓ 503-531-2271Logical Devices David Mot ✓ 303-279-6868Mentor Graphics Sam Picken ✓ ✓ ✓ 503-685-1298MINC Lynne Dolan ✓ ✓ ✓ 719-590-1155Minelec ✓ +32-02-4603175OrCAD Troy Scott ✓ 503-671-9500Protel Technology Matthew Schwaiger ✓ 408-243-8143Quad Design Tech. Vern Potter ✓ ✓ 805-988-8250Simucad Richard Jones ✓ 510-487-9700Sophia Systems Terry Wilfley ✓ ✓ ✓ 408-943-9300Synopsys Lynn Fiance ✓ ✓ ✓ 415-694-4102Synplicity Alisa Yaffa ✓ ✓ ✓ 415-961-4962Teradyne Mike Jew ✓ ✓ 617-422-3753Tokyo Electron Shige Ohtani +81-3-5561-7212TopDown Art Pisani ✓ ✓ ✓ 603-888-8811transEDA James Douglas ✓ ✓ +44-1703-255118VEDA George Sher ✓ ✓ 408-496-4516ViewLogic Preet Virk ✓ ✓ ✓ ✓ 508-480-0881Viewpoint International Ramesh Bhimarao ✓ ✓ ✓ 408-954-7370Visual Software Ricky Escoto 305-346-8890Zycad David Allenbaugh ✓ ✓ 510-623-4451
ALLIANCE PROGRAM - PLATFORMS & CONTACTS
10X
C20
18X
C20
64L
XC
2018
LX
C30
20X
C30
30X
C30
42X
C30
64X
C30
90X
C30
20A
XC
3030
AX
C30
42A
XC
3064
AX
C30
90A
XC
3020
LX
C30
30L
XC
3042
LX
C30
64L
XC
3090
LX
C31
20A
XC
3130
AX
C31
42A
XC
3164
AX
C31
90A
XC
3195
AX
C40
05X
C40
06X
C40
08X
C40
10X
C40
13X
C40
25X
C40
02A
XC
4003
AX
C40
04A
XC
4005
AX
C40
03H
XC
5210
XC
7236
A
XC
7354
XC
7372
TYPE
PIN
S
44
48
64
68
84
100
120
132
144
156
160
164
175
176
184
191
196
208
223
225
228
240
299
304
CO
DE
XC
4003
XC
7310
8
PLASTIC LCC PC44
PLASTIC QFP PQ44
CERAMIC LCC WC44
PLASTIC DIP PD48
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
CERAMIC PGA PG68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
CERAMIC QFP CQ100
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
CERAMIC QFP CQ164
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG184
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
METAL MQFP MQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
WINDOWED BGA WB225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
METAL MQFP MQ240
CERAMIC PGA PG299
HI-PERF. QFP HQ304
XC
2064
XC
4010
D
XC
4005
H
XC
7318
XC
7336
COMPONENT AVAILABILITY CHART - MAY 1995
◆◆ ◆ ◆ ◆ ◆ ◆◆ N ◆
◆◆ N
◆ ◆ N ◆
◆
◆◆◆ ◆
◆◆◆ ◆◆ ◆◆ ◆◆ ◆ ◆◆
◆ ◆◆
◆
◆ ◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆ ◆◆◆◆◆ ◆◆◆◆ ◆◆ ◆ ◆◆
◆ ◆◆
◆ ◆◆◆ ◆◆◆ ◆◆◆ ◆
◆ ◆
◆◆◆ ◆◆◆ ◆◆◆ ◆ ◆ ◆◆ N ◆◆
◆ ◆◆ ◆◆
◆ ◆◆ ◆◆ ◆◆ ◆◆
◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆◆◆
◆◆ ◆◆ ◆◆
◆◆ ◆◆ ◆◆
◆◆ ◆◆ ◆◆ ◆◆ N N
◆
◆◆ ◆
◆◆ ◆◆ ◆◆◆ ◆◆◆◆◆◆◆ ◆◆ ◆◆ ◆◆
◆
◆ ◆ ◆◆ ◆
◆ ◆ ◆◆
◆ ◆ ◆◆
◆ ◆ ◆
◆◆ ◆ ◆
◆
◆ ◆ ◆◆ ◆◆◆◆◆◆◆ ◆◆ ◆◆
◆◆ ◆
◆ ◆ ◆
◆◆◆◆ ◆◆
◆◆
◆ ◆ ◆
◆
◆ ◆
XC
7272
A
XC
4013
D
XC
7314
4
◆
◆ ◆
◆ ◆
XC
5206
◆
XC
7336
Q
N
◆ = Product currently shipping or planned N = New since last XCELL
11
PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL PROMS — MAY 19951736A/ 1736D/ 1716L/
MANUFACTURER MODEL 1765 17128 1765D 1765L 17128D 17256D DIP8 PC20 SO8ADVANTECH PC-UPROG V2.1 V2.0 V2.0 V2.1 V2.1 X
LABTOOL-48 V1.0 V1.0 V1.0 V1.0 V1.0 X PLCC2020-01ADVIN PILOT-U24 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8
PILOT-U28 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U32 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U40 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U84 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-142 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-143 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-144 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-145 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8
AVAL PECKER-50 C C XPKW5100 C C X
B&C MICROSYSTEMS INC. Proteus-UP40 V3.4e V3.4e V3.5f V3.7f V3.7l V3.7l X AMUPLC84BP MICROSYSTEMS CP-1128 C V2.17* V2.21c* V2.34* V3.06 V3.06 FH28A FH28A + 3rd Party FH28A + 3rd Party
EP-1140 C V2.17 V2.21c V2.34 V3.06 V3.06 FH40A FH40A + 3rd Party FH40A + 3rd PartyBP-1200 C V2.17 V2.21c V2.34 V3.06 V3.06 SM48D SM20P or SM84UP 3rd Party
BYTEK 135H-FT/U V42 V51 V51 V51 TC-824DMTK-1000 V42 V51 V51 V51 TC-824DMTK-2000 V42 V51 V51 V51 TC-824DMTK-4000 V42 V51 V51 V51 TC-824D
DATA I/O UniSite/Site 40/48 V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOICUniSite/ChipSite V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOICUniSite/PinSite V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOIC2900 V2.1 V2.2 V2.2 V3.4 V3.6 V3.6 X 2900-PLCC 2900-SOIC3900 V1.5 V1.6 V1.6 V2.4 V2.6 V2.6 0101 3900-PLCC 3900-SOICAutoSite V1.5 V1.6 V1.6 V2.4 V2.6 V2.6 DIP-300-1 PLCC-20-2UniPak 2B V24 351B120ChipLab V1.1 V1.0 V1.0 V1.1 V2.0 V2.0 X 080801S300
DEUS EX MACHINA XPGM V1.00 V1.00 V1.00 V1.10 V1.10 0 3rd Party 3rd PartyELECTRONIC ENGIN- ALLMAX/ALLMAX+ V1.3 V1.5 V1.5 V1.5 P 3Q/95 P 3Q/95 XEERING TOOLS PROMAX V2.34 V2.34 V2.34 V2.34 V2.34 V2.34 X Module #4ELAN DIGITAL SYSTEMS 3000-145 C C A116
5000-145 C C A1166000 APS K2.01 K2.02 K2.01 K2.10 K2.14 K2.14 X PDi84UPLC PDi16USOI
HI-LO SYSTEMS All-03A V3.30 V3.30 V3.30 V3.30 V3.50 V3.50 X CNV-PLCC-XC1736 CVN-SOP-NDIP16RESEARCH All-07 V3.30 V3.30 V3.30 V3.30 V3.47 V3.47 PAC-DIP40 PAC-PLCC44ICE TECHNOLOGY LTD Micromaster 1000/1000E V1.1 V3.00 V3.00 V3.00 V3.00 X AD-1736/65-PLCC
Speedmaster 1000/1000E V1.1 V3.00 V3.00 V3.00 V3.00 X AD-1736/65-PLCCMicromaster LV V3.00 V3.00 V3.00 V3.00 V3.00 XLV40 Portable P 2Q95 P 2Q95 P 2Q95 P 2Q95 P 2Q95 XSpeedmaster LV V3.00 V3.00 V3.00 V3.00 V3.00 X
LINK COMPUTER GPHX CLK-3100 V5.08 V5.08 V5.08 X17XXB PLCC-17XX SOIC-16LOGICAL DEVICES ALLPRO-40 V2.2 X OPTPLC-208 OPTSOI-080
ALLPRO-88 V2.2 V2.3 V2.3 V2.5 V2.5 X OPTSOI-080ALLPRO-88XR V1.1 V2.3 V1.3 V2.3 V2.3 X OPTSOI-080CHIPMASTER 3000 V2.0 V2.1 V2.0 V2.3 X OPTPLC-208 OPTSOI-080CHIPMASTER 5000 V1.15 X OPTPLC-208 OPTSOI-080XPRO-1 V1.01 V1.01 V1.01 V1.01 MODXLN-173 MODXLN-173 MODXLN-173
MQP ELECTRONICS MODEL 200 C 6.45 6.45 6.45 6.46 6.46 AD13A-16SYSTEM 2600 P 2Q95 P 2Q95 P 2Q95 P 2Q95 P 2Q95 MP6PINMASTER 48 P 2Q95 P 2Q95 P 2Q95 P 2Q95 P 2Q95 X
MICRO PROSS ROM 5000 B C V1.70 V1.70 Mu 40ROM 3000 U C V3.60 V3.60
NEEDHAM’S ELECTRONICS EMP20 V1.5 V1.5 V2.37 V2.37 V2.37 V2.37 04BRED SQUARE IQ-180 C V8.2
IQ-280 C V8.2Uniwriter 40 C V8.2Chipmaster 5000 C V8.2
RETNEL SYSTEMS ZAP-A-PAL C V3.8J Module #36 SMS Expert B/93 A/94 A/94 A1/94 Cx/94 Cx/94 TOP40DIP TOP1PLC or
Optima B/93 A/94 A/94 A1/94 Cx/94 Cx/94 “ TOP3PLC/TOP3PLCMultisyte A/94 Cx/94 Cx/94 “ “Plus48 B/93 A/94 A/94 A1/94Sprint Plus B/93 A/94
STAG Eclipse 4.4 V2.2 V4.3 V4.10.31 V4.10.31 EPU48D EPU84PQuasar 10.76C 10.76C V10.76C V10.76C V10.78B V10.78B X AMPLCC20
SUNRISE T-10 UDP V3.31 V3.31 V3.31 V3.31 V3.31 V3.31 X X XT-10 ULC V3.31 V3.31 V3.31 V3.31 V3.31 V3.31 X X X
SUNSHINE POWER-100 V8.18 V8.18 V8.18 V8.18 V8.18 V8.18 XEXPRO-60/80 V8.18 V8.18 V8.18 V8.18 V8.18 V8.18 X
SYSTEM GENERAL TURPRO-1 V2.21F V2.21F V2.21F V2.21F V2.21F V2.21F DIP-Adapter P20-AdapterTurpro-1 F\X V2.21F V2.21F V2.21F V2.21F V2.21F V2.21F DIP-Adapter P20-AdapterAPRO C V2.14 V2.01 V2.12 S 2Q95 S 2Q95 X X
TRIBAL MICROSYSTEMS TUP-300 C V3.31 V3.31 V3.37C V3.47 V3.47 X CNV-PLCC-XC1736TUP-400 C V3.31 V3.31 V3.37C V3.50 V3.50 X “FLEX-700 C V3.31 V3.31 V3.37C V3.47 V3.47 X “
XELTEK SuperPRO 1.5B 1.7C 1.7D 1.8 2.2A 2.2A X* 20-PL/8-D-ZL-XC1736 16SO15/D6-ZLSuperPRO II 1.5B 1.7C 1.7D 1.8 2.2A 2.2A X* 20-PL/8-D-ZL-XC1736 16SO15/D6-ZL
XILINX HW-112 C V3.11 V3.31 V3.31 V5.0.0 V5.0.0 X HW-112-PC20 HW-112-SO8HW-120 V5.00 V5.00 V5.00 V5.00 P 6/95 P 6/95 HW-120-PRM HW-120-PRM HW-120-PRMHW-130 V1.00 V1.00 V1.00 V1.00 V1.00 HW-137-DIP8 S 5/95 S 5/95
C = Currently Supported, P = Planned, S = Scheduled Release Date, X=Package Supported
12
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PRODUCT INFORMATION — COMPONENTS
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MIL-STD-883B Compliant Serial PROMsThe XC1765D and XC17256D
Serial Configuration PROMs are nowavailable in full MIL-STD-883B compli-ant versions. These devices typicallyare used to store configuration data forXilinx SRAM-based FPGAs, and areoptimized for easy use with theFPGAs. As part of our commitment tothe Hi-Rel (military, defense, and aero-space) market, Xilinx has long offeredmilitary temperature range versions,but in addition now provides fullycompliant devices.
The XC1765D device holds 65,536bits of data and can completely config-
ure Xilinx FPGAs up to the density ofthe XC3090, while the XC17256Dholds 262,144 bits of data and cancompletely configure any Xilinx FPGAup to the density of the XC4013. Mul-tiple devices can be easily cascaded tosupport multiple FPGAs and/or mul-tiple configurations.
Both devices are available in the8-pin DIP package, and DESC SMDs(Standard Military Drawings) havebeen released. These devices aresupported by a wide range of pro-grammers available from Xilinx andleading third-party vendors. ◆
New XC4000 Family Speed GradeOffers Higher Performance
The XC4000 FPGA family will reachnew performance levels with the introduc-tion of the -3 speed grade this July. Thisspeed improvement, along with up-coming architectural improve-ments, will expand therange of applicationsthat can be addressed bythis high-performance,full-featured FPGA family.The improved performance ofthe -3 devices also al-lows the XC4000 familyto be fully PCI compliant.
In the typical applica-tion, the new -3 speed gradeoffers a 25 percent perfor-mance improvement over theprevious XC4000 device speedrecord. System clock speeds of 70
MHz and higher will be achievable.Digital signal processing is among the
many high-performance applica-tions that can be addressed by
this high-speed FPGA technol-ogy. Video processors that
previously required mul-tiple DSP processors or
large ASICs can beimplemented in a singleFPGA device. (An ap-
plication note about FIRfilter implementations in
XC4000 FPGAs wasrecently released, andmore DSP design
support material is beingprepared.). For more information,
send E-mail inquiries to [email protected] ◆
15
XC5200 FPGA Family GrowsThe XC5200 FPGA family has been
expanded to include the 2,500-gateXC5202 and the 4,000-gate XC5204. TheXC5200 family now includes flexible,high-density FPGA devices ranging from2,500 to 18,000 gates.
For lower-density designs that do not
require the use of on-chip user RAM, thenew XC5202 and XC5204 FPGAs providea feature-rich solution. Like all membersof the XC5200 FPGA family, these newdevices include JTAG boundary-scan logicfor enhanced testability, carry logic sup-porting fast arithmetic operations, andinternal 3-state buffers for efficient on-chip busing capability.
All XC5200 devices offered in a com-mon package (see table) are completelyfootprint compatible, allowing the easymigration to smaller or larger deviceswithout changes to the PCB layout. Theflexible VersaRingTM I/O interface deliversthe industry’s best pin locking capabilityfor a high-density FPGA.
Please contact your local Xilinx salesrepresentative for further informationregarding software and componentavailability. ◆
NEW NEWDEVICE XC5202 XC5204 XC5206 XC5210 XC5215
Usable gates 2,200- 3,900- 6,000- 10,000- 14,000-2,700 4,800 7,500 12,000 18,000
VersaBlock matrix 8 x 8 10 x 12 14 x 14 18 x 18 22 x 22
Total CLBs 64 120 196 324 484
Total Flip-Flops 256 480 784 1,296 1,936
Total IOBs 84 124 148 196 244
10K Unit Pricing $9 $15 $25 $38 $68(-6 speed grade, PC84) (PQ208)
Availability 3Q95 3Q95 NOW NOW 3Q95
Packages PC84 PC84 PC84 PC84PQ100 PQ100 PQ100VQ100 VQ100TQ144 TQ144 TQ144 TQ144
PQ160 PQ160 PQ160PQ208 PQ208 PQ208
PQ240 PQ240HQ304
PG156 PG156 PG191 PG223 PG299
16
Introducing The New,Low-Power XC7336Q EPLDThe latest addition to the fast-growing
XC7300 EPLD family is a low-power ver-sion of the XC7336 called the XC7336Q.
The XC7336Qoffers all of the ben-efits of the advancedXC7300 architecture,including 100 percentrouting with 100percent utilization,SMARTswitch, 24mAoutput drive and3.3V/5V level translation. Furthermore,like the other XC7300 family members, theXC7336Q-10 is 100 percent PCI compliant.
The XC7336Q differs from the standardXC7336 in terms of power consumption —the Q version consumes 60 percent lesspower. Also, the XC7336Q is availableonly in -10, -12 and -15 speed grades.
PAL and GAL users are already familiarwith the Q nomenclature — in the
PAL/GAL world, a Q (forQuarter power)
CMOS PALtypically
functions atone-fourth the
ICC of theequivalent PAL.
Power-consciousPAL users will find
the XC7336Q to beextremely appealing,
as the XC7336Q willintegrate three 22V10s
while consuming onlyone sixth the power of
those devices.The XC7336Q EPLD is ideal for space-
constrained electronic systems, including
computing, peripherals and consumerapplications. Board space and airflow limi-tations tend to make such applicationshighly sensitive to power consumption andsystem noise. Low ICC specifications com-bined with low-profile packaging optionsmake the XC7336Q a high integration PAL-like solution that fits small form factor andpower constraints and enhances a design’soverall reliability and noise immunity.
Above is a selection guide to helpchoose the best XC7336 product for yourneeds. Note that there are instances wherethe standard XC7336 is a better choice thanthe XC7336Q.
The XC7336Q will be fully supported(explicitly) in DS-550 Rev. 6.0. However,users can begin designs immediately withDS-550 v5.1 by using the standard XC7336as the target device. Programming supporton the HW-130 programmer will be avail-able by the end of May, and all major thirdparty programmers will be on-line in July.
Engineering samples of the XC7336Qwill be available by the end of May, withvolume shipments by the end of June. ◆
LOWEST LOWESTDEVICE SPEED COST POWER PACKAGES
XC7336 PC44. WC44.- 5,7,10,12,15 ✔ ✔ PQ44
XC7336Q PC44, WC44,- 10,12,15 ✔ PQ44, VQ44
17
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The newest version of the Xilinxdevelopment system—named XACTstep,version 6—combines power and ease-of-use to provide the highest-productivitytool set in the programmable logic indus-try. Targeted for shipment in August,1995, XACTstep runs under MicrosoftWindows 3.1 on the PC and Motif onworkstations.
XACTstep, version 6 features six power-ful, easy-to-use tools intended for a widerange of programmable logic designs. Onone end of the spectrum, simple PALreplacements can be implemented inEPLDs using fully automatic techniques.At the other end of the spectrum, large,complex FPGA designs can be fine-tunedusing a configurable flow engine and theprogrammable logic industry’s first graphi-cally-based, hierarchical floorplanner.
The new graphical user interface (GUI)in XACTstep includes many features thatshorten the learning curve and simplifydesign implementation and debug. Withthis GUI, programs are executed andoptions are set using tool bars and icons.Tool tips give instant descriptions of com-mands and on-line help provides more in-depth information. New report browsersdisplay message files with “plain English”titles and allow the simultaneous viewingof multiple documents.
The results are faster implementationand debug cycles, a shorter learning curveand a dramatic boost in engineering pro-ductivity.
Six Powerful New ToolsXACTstep contains six powerful new
tools that accelerate design implementa-tion, verification and debug cycles.• The new Design Manager provides a
complete project management environ-ment for the XC2000, XC3000, XC3100,
XC4000, XC5000 and XC7000 families.It supports unlimited version controland manages all the underlying files foreach design revision.
• The configurable Flow Engine lets userschoose the desired amount of controlover the implementation process. Us-ers can choose a fully automatic flowor set break points that allow the analy-sis and optimization of results beforeproceeding to the next step.
For each step in the implementationprocess, the automatic tools can be easily
directed to achieve the desired result. Forexample, the automatic placement androuting tools can be set to optimize thedesign or minimize run time; the selectionis made using a slide bar that appears in apop-up menu.
The entire collection of settings can bestored in a template for later use. Newusers can choose from standard templatesprovided with the system. Experiencedusers can create an unlimited number ofcustom templates and distribute these toother members of their group.
For users who don’t want to take ad-vantage of the new, easy-to-use interface,
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PRODUCT INFORMATION — DEVELOPMENT SYSTEMS
V E R S I O N 6
A Revolutionary Combinationof Power and Ease-of-Use
18
specific path or group of paths, such asall the paths of a certain type or thoseassociated with specific clock signals.In addition, the Timing Analyzer canautomatically compare the implementeddesign’s actual performance to the goalsentered using XACT-PerformanceTM, andshow the estimated maximum frequencyfor each clock in the design.
• The new Hardware Debugger providesfor the verification of configuration dataand the viewing of internal signal activityduring system debug and test. It takesadvantage of the re-programmable,SRAM-based devices by configuring theFPGA in-circuit using a cable connectedto a host PC or workstation. After con-figuring the device, bitstream data is readback through the cable for automaticverification.
While the device is running, an unlim-ited number of internal nodes can beviewed, with the results displayed in awave-form window. By giving the hard-ware debugger control of the systemclock, designers can easily step throughstate machines and other synchronouscircuits to verify functionality.
• The new graphics-based PROM Formatterin XACTstep creates PROM programmingfiles. It chooses the best PROM size forthe design, and automatically splits thedata into multiple files if smaller PROMSare being used. Serial and byte-widePROMS in four different formats aresupported. If the target system includesa daisy chain of FPGAs, the PROMformatter graphically creates the loadorder and verifies the load sequence.
Free To Users On MaintenanceRegistered Xilinx development system
owners with an active software maintenanceagreement will receive the XACTstep, ver-sion 6 update automatically. To check onthe status of your maintenance agreement,call Xilinx customer service at408-559-7778, or contact your localXilinx sales office. ◆
all program options from XACT 5.0 can beentered using the old command line syntax.
• XACTstep contains a new graphics-based, hierarchical floorplanner. WithXACT-FloorplannerTM, users can easilyachieve “hand-crafted” levels of perfor-mance and density in FPGA designs.(See related article on page 19).
Floorplanning is valuable for anydesign that has a high degree of struc-ture or a large number of gates. Withjust a few minutes of basic floor-planning, designers can quickly place
critically-timed logic and graphicallyplan the data flow. Placement is per-formed at a high level using the designs’hierarchy and a floorplan of the targetdevice. Floorplanning also allows opti-mal use of specialized FPGA architec-tural structures like high-speed distrib-uted RAM and internal three-statebuffers. Users needing to maximizeperformance can easily implement adetailed floorplan employing provenoptimization techniques like bus inter-leaving, register grouping and I/O pinalignment.
• The interactive Timing Analyzer makesit easy to analyze the designs’ perfor-mance with custom timing reports. Us-ing pop-up menus, the tool can generatereports that show the delay along any
Continued from previous page
19
Full-Featured FloorplannerBoosts FPGA Performance
The new XACTstep, version 6 releasecontains the industry’s first graphics-basedhierarchical floorplanner. Use of XACT-Floorplanner can result in dramatic im-provement to FPGA performance, allow-ing designs to run at higher speed, orproviding cost-savings by allowing the useof a slower speed grade device.
Floorplanning is particularly effectivefor designs that have a high degree ofstructure or a large gate density.Floorplanning can help optimize the useof special FPGA features such as the high-speed distributed RAM capability of theXC4000 FPGA family.
The Floorplanner features a “drag-and-drop” methodology that makes it easy tolearn and use. A basic floorplan is createdby dragging logic elements from the de-sign and dropping them into locations ona picture of the die. Critically-timed logiccan be pre-placed, and overall data flowcan be planned. More-detailed floorplansallow the use of proven optimizationtechniques such as bus interleaving, regis-ter grouping and I/O pin alignment.
Many powerful features aid the de-signer. Users start with a graphical viewof the designs’ hierarchy. Each level ofhierarchy is labeled with the original sym-bol from the schematic or hardware de-scription language description, and ismarked with the exact number of requiredFPGA resources. This view of the hierar-chy can be enlarged or reduced to viewany level of the design. A search and findutility makes it easy to locate specificlogic elements.
When a logic element is “dropped”onto the die, the Floorplanner creates a“ratsnest” view of all its interconnectionsto previously-placed elements. Logicelements can be assigned to an area of thedevice so that the automatic “place and
route” tools can then find an optimalplacement of that logic within that area.For elements encompassing multipleFPGA resources, the Floorplanner can bedirected easily to distribute the elementshorizontally or vertically. Thus, logicstructures can be aligned to use long linerouting and internal three-state buffersefficiently.
For more-detailed floorplans, powerfulcommands make it easy to align or inter-
leave busses or structured logic elements.Users re-order bits by simply changing thesort order. Complex alignments can becarried out by placing each bit separately.
Once the floorplanner finds the opti-mal placement for a given logic structure,it can be captured to a Placement Mapand imposed on similar structures in thedesign — making it easy to “tile” repeatedlogic, or re-use portions of a design infuture projects.
After completing the floorplan, com-mands are available to help analyze itsefficiency. These commands also can beused to analyze a layout created by theautomatic tools.
Continued on next page
20
Cadence Interface Now Available from XilinxThe interface software for linking the
Cadence design tools to the Xilinx XACT-DevelopmentTM system, including Veriloglibraries, can now be purchased directlyfrom Xilinx. Support contracts also areavailable. This reflects our continuingcommitment to make top-down designmethodologies more accessible to Xilinxusers. These interfaces and libraries aredeveloped by Cadence and requireCadence licenses (except for ES-Verilog).There are several product configurations,as described below:
ES-Verilog (No Charge)This package includes the Verilog
simulation models and XNF2Verilogtranslator. Interested users who havean in-warranty DS-502 or any “standardpackage” on workstations can requestES-Verilog directly through Xilinx cus-tomer service.
DS-381-SN2 (or HP7)-CThis product includes:• Concept and Composer schematic
symbols• Verilog-XL and RapidSIM simulation
models• Netlist translators for these Cadence
schematic editors and simulatorsThe software and documentation for
the DS-381 package is already included onthe Cadence compact disk that holds theother Cadence products (CD “9404” or
later). Therefore, immediate access toDS-381 is available upon purchasing thelicense to enable it — nothing is shippedto the purchaser. Please contact your localXilinx sales representative for more infor-mation on how to order this license.
DS-CDN-STD-SN2 (or HP7)-CThis product includes:• DS-381 package (as described above)• Xilinx 3PA package (the core imple-
mentation tools for Xilinx FPGAs andEPLDs, including X-BLOX)Because users already have the DS-381
software and on-line documentation ontheir Cadence CD, only the 3PA packagewill be shipped after purchase. Pleasecontact your local Xilinx representative forinformation on how to order this package.
DS-381 Product EvaluationAny Cadence user with a “9404” or
later CD can evaluate Xilinx software for90 days by requesting a 90 day temporarylicense from your local Xilinx sales office.
Maintenance ContractsCadence customers can now move
their support contract for the Cadenceinterface software to Xilinx by purchasingthe SC-381 or SC-CDN-STD support pack-ages. However, no updates are planneduntil the next release of the XACT® tools(XACTstep, version 6); it is recommendedthat users maintain their Cadence mainte-nance contract until then. ◆
navigate to the problem spot with a singleclick of the mouse. For more-detailedanalysis, ratsnest views can be generatedfor any resource, along with routing con-gestion maps for any CLB(s).
Whether the design requires a fewminutes of basic floorplanning or a de-tailed analysis and optimization, theFloorplanner can provide a tremendousboost in designer productivity and signifi-
FloorplannerContinued from previous page
The Check Floorplancommand verifies re-source allocation, three-state buffer alignment andCLB packing. If errors orwarnings are found, adialog box is used to
cant improvements in FPGA perfor-mance and density.
The Floorplanner can be used forXC3000A, XC3100A, XC4000, andXC5000 FPGA designs. RegisteredXACT development system owners withactive software maintenance agreementswill receive the Floorplanner in theXACTstep, version 6 update targeted forAugust shipment. ◆
❝Thisreflects our
continuing
commitment to
make top-down
design
methodologies
more accessible
to Xilinx users.❞
21
Solaris Support StatusAccording to Sun, all programs
compiled for SunOS 4.1x shouldwork under Solaris 2.3 (and higher)in emulation mode. XACT software,for the most part, fits this category.Even though Xilinx has performedno formal testing with the Solarisoperating system, some users aredesigning successfully with XACT-SN2 products under Solaris.
However, there are a few knownproblems when running underSolaris 2.3:
• FLEXLM License Manager: Run-ning XACT under Solaris, requiresa special version of the HighlandLicense Manager program, flexlm,compiled for Solaris. This soft-ware can be requested from theXilinx Hotline and e-mailed di-rectly to the user.
• Mentor Interface: The gen_sch8and xblxgs programs do notwork under Solaris.
• XChecker: XChecker bitstreamdownload and debugging are not
expected to work with Solaris.Therefore, this program must beused on a SunOS machine or ona different platform (e.g., a PC).
FPGA Foundry from NeoCADsupports Solaris and is available nowas an option for Xilinx users thatrequire immediate Solaris support.
With the recent merger of Xilinxand NeoCAD, plans are being devel-oped to support Solaris with a futurecombined product. ◆
Upgrading to NeoCAD FPGA FoundryBoth the XACT DevelopmentTM Sys-
tem and NeoCAD’s FPGA FoundryTM areavailable for implementing designs in theXC3000 and XC4000 FPGA families. Eachhas its respective strengths; for somehigh-density designs, the XACT systemproduces a better implementation; forothers, the NeoCAD system generatesa better solution.
It will take some time for the combinedcompanies to integrate these products intoa single development system. In themeantime, some current XACT users maybe interested in adding the FPGA Foundryto their tool suite — particularly thoseusers implementing very high-densityFPGA designs.
For users with in-warranty XACT sys-tems, special upgrade pricing has beenestablished in order to allow add-on pur-chases of the FPGA Foundry software.Upgrade prices range from $2,700 to$3,000 (U.S.), dependent on the platform(PC or workstation). For users purchasingnew systems, an “Advanced” system that
contains both the XACT and FPGAFoundry software is available. Pleasecontact your local Xilinx sales represen-tative for ordering codes and pricing forboth new packages and upgrades.
Designers purchasing such an up-grade should be aware that these aretwo different development system suites,with their own licenses, user interfaces,documentation, and packaging. Bothsupport X-BLOXTM, the Unified Libraries,and XNF file formats, but FPGA Foundrydoes not support XACT-Performance orthe upcoming XACT-FloorplannerTM.The FPGA Foundry system supportsonly the XC3000 (and its deriviatives —XC3000A, XC3100, XC3100A) andXC4000 FPGA families. It is availablefor the Windows, HP, SunOS and Solarisoperating systems.
Users should review their needs withtheir local Xilinx Field Application Engi-neer before purchasing the upgrade toFPGA Foundry or the Advancedpackages. ◆
22
HW-130 Xilinx Universal Programmer Now AvailableThe new HW-130 universal Xilinx
device programmer is now available forXilinx EPLD and serial PROM users. The
HW-130 supports the programming ofall Xilinx EPLD and serial
PROM products, and willsupport the XC8100 FPGA
family when it becomesavailable. This new product
replaces the HW-112 serialPROM programmer and HW-120
EPLD programmer. The HW-130 isless expensive, smaller and faster than
either the HW-120 or HW-112.The HW-130 programmer comes with
an “international” power supply, allowingit to be used anywhere in the world. Fourversions are available (see chart); varyingonly in the power cord supplied. The
programmer comes complete with the cablethat connects the HW-130 to its host PC. Afull range of package adaptors is available,although the HW-130 can use most of theexisting HW-120 adaptors. ◆
ORDERING PRODUCT SUPPORTEDPART NUMBER FAMILY PACKAGEHW-130-PC1-01 U.S., AsiaHW-130-PC1-02 EuropeHW-130-PC1-03 U.K.HW-130-PC1-04 JapanHW-130-CAL CalibrationHW-132-PC44 XC7200 PC44HW-133-PC44 XC7300 PC44HW-133-PQ44 XC7300 PQ44HW-132-PC68 XC7200 PC68HW-133-PC68 XC7300 PC68HW-132-PC84 XC7200 PC84HW-133-PC84 XC7300 PC84HW-133-PQ100 XC7300 PQ100HW-133-PQ160 XC7300 PQ160HW-137-DIP8 XC1700 DD8/PD8HW-137-PC20/SO8 XC1700 PC20/SO8
Full XC7000 EPLD Support Available from ISDATAThe leading European PLD
compiler, ISDATA, has completelyintegrated an XC7000 fitter into itslatest software, LOG/iC2. Thisdesign path provides designerswith a seamless, easy-to-use, effi-cient and cost effective designenvironment for XC7000 EPLDs.
The LOG/iC2 development tooloffers design entry, logic synthesisand simulation using the LOG/iC-HDL, schematic capture and/orVHDL in a hierarchical, graphicalenvironment. The design can betargeted to any XC7000 device using the Xilinx-devel-oped fitter. This flow is illustrated in the figure above.
Industry’s Best “Pin Fixing” EPLDsThe XC7000 family of EPLDs offer the industry’s
fastest speeds (tPD = 5ns) with the architectural benefit of100 percent routability with 100 percent utilization.With this new fitter now embedded within the ISDATAtool, designers can quickly and easily implement designswith these high performance devices.
Ordering InformationThe XC7000 fitter is included in
the ISDATA Open Design Converter(ODC) package, and can be usedwith both the LOG/iC Classic andLOG/iC2 development systems. Therequired software for LOG/iC2 usersis shown in Table 1 and can beordered by calling ISDATA GmbH inGermany (49-721-751088) or ISDATAInc. in the U.S. (510-531-8553).Existing LOG/iC Classic owners canupgrade their software and obtainthe XC7000 fitter by ordering the
upgrades shown in Table 2. ◆
Table 1. LOG/iC2 Software for XC7000 SupportLOG/iC2 Base: ............................................................. Part # 70100LOG/iC2 PLD Kernal: .................................................. Part # 72000LOG/iC2 Open Design Converter: ............................... Part # 72100
Table 2. Software Upgrades for LOG/iC ClassicLOG/iC Plus ................................................................. Part # 10200 orLOG/iC Perfect ............................................................. Part # 12200LOG/iC Open Design Converter .................................. Part # 12500
Figure: Xilinx XC7000 Design with LOG/iC2
23
DESIGN HINTS AND ISSUES
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As the size and complexity of FPGA-based designs continue to grow, someusers are turning to hardware design lan-guages (HDLs) and logic synthesis tools toenter their designs.
To effectively use an HDL, users mustunderstand the language syntax as well asthe potential and limitations of this designentry method, especially when creatinggeneric code intended for different devices.
To aid in this process, Xilinx is prepar-ing a comprehensive HDL Synthesis DesignGuide for FPGAs which will be available tousers around mid-year. It will describedesign methodologies and illustrate themwith design examples. The guide is in-tended to help HDL users produce success-ful FPGA designs.
This article gives a brief description ofsome of the advantages of HDL-baseddesign, and then briefly reviews some ofthe material included in the forthcomingdesign guide.
HDL AdvantagesHDLs and synthesis tools allow the logic
designer to enter designs at a higher levelof abstraction, much like the softwareengineer who programs in ‘C’ instead ofassembly language. The designer specifiesthe needed system-level functions, where-upon error-free gate level implementationsare generated by the synthesis tool, freeingthe designer for more creative tasks.
Users look to high-level languages andlogic synthesis to provide an efficientmeans of migrating designs between tech-nologies — the design’s high-level descrip-tion is not necessarily bound to a givendevice architecture or process technology.Like schematics, HDL-based designs also
Designing FPGAs withHDLs and Synthesis Tools
are self-documenting since the HDL file isthe functional description of the design.
Logic synthesis tools and FPGAscomplement each other in providing aflexible design environment. With HDLs,decisions can be tested early in the designcycle through functional simulation of theHDL description. Design changes aremade easily, allowing experimentationand the exploration of architectural trade-offs. Synthesis tools then convert theHDL description to a gate-level implemen-tation for the target FPGA architecture.
FPGAs further enhance this designflexibility by allowing the user to imple-ment and test the design at the work-bench. Typically, the synthesis compila-tion time is short enough to allow forexploration of design trade-offs at theirgate-level implementation. SRAM-basedFPGAs can be reprogrammed an unlimitednumber of times, so mul-tiple iterations of the de-sign can be implementedwith no additional hard-ware cost.
FPGA-OptimizedSynthesis Tools
For a top-down, HDL-based design methodologyto be useful, the synthesistools must be effective inproducing a gate-leveldesign for the target tech-nology. Synthesis algo-rithms for FPGAs can bedramatically different fromthose used for gate arrays. Fortunately,many synthesis tools have special optimi-
❝HDLs andsynthesis tools allow the
logic designer to enter
designs at a higher level of
abstraction, much like the
software engineer who
programs in ‘C’ instead of
assembly language.❞
Continued on next page
24
zation algorithms for Xilinx FPGAs.For example, in the Synopsys FPGA
Compiler, logic is synthesized into thebuilding blocks of the FPGA: functiongenerators (look-up tables) and registers.The FPGA Compiler reports the area utili-zation and critical path delays in terms ofCLBs, not gates. This guarantees a highlevel of correlation between the reportedarea/speed numbers and the actual resultsafter implementation by the place androute tools.
To address the demand for effectivesynthesis tools, Xilinx initiated its Synthe-sis Syndicate Program about two yearsago, a program to assist and encouragethird-party EDA vendors in developingsynthesis tools for Xilinx components.
ASIC vs. FPGA DesignThe methods and techniques used in
ASIC design are not always best forFPGAs. ASICs typically have more gatesand routing resources than FPGAs. SinceASICs have a large number of availablelogic resources, inefficient code that re-sults in a larger-than-necessary number ofgates often can be tolerated. When de-
signing FPGAs, the resultsof inefficient coding willbe magnified.
Language IssuesNot all the constructs
available in an HDL maybe applicable to FPGAdesign. For example,VHDL, which was origi-nally developed as asimulation language andlater adopted for IC de-sign, includes a “wait”statement instructing a
VHDL simulator to wait for a specifiedtime before a condition is executed. Thisstatement does not synthesize to anycomponents. In a design that includesthis statement, the functionality of thesimulated design may not match the func-tionality of the synthesized design.
Various synthesis tools may also usedifferent subsets of the VHDL language.Furthermore, constraints and compilingoptions can perform differently, depend-ing on the target device.
Using FPGA System FeaturesDevice performance and area utiliza-
tion can be optimized by creating HDLcode that takes advantage of special FPGAarchitectural features such as global resets,wide decoders, on-chip memory and carrylogic — common knowledge for experi-enced FPGA users. However, users mustlearn how to access these features in anHDL-based design. Some must be “instan-tiated” into the code (that is, the user mustexplicitly specify that these resources areto be used by embedding directives withinthe HDL code). The user must thereforebe familiar with the target FPGA architec-ture. The code is architecture-specific andnot easily transferred to other devices.
Hierarchical DesignHierarchical design is important in the
implementation of an FPGA, particularlyduring floorplanning and debugging, orwhen using incremental design tech-niques. Large designs (greater than 5,000gates) should be partitioned into smallermodules. The size and the contents of themodules can affect synthesis and imple-mentation results.
HDL Design FlowThe design flow for FPGAs when using
HDLs is very similar to that of ASICs. Thebasic steps are listed below:
1. Entry of the HDL code; the designshould be evaluated for inefficientcoding styles and for possible usageof FPGA system features.
2. Functional simulation with a VHDLor Verilog simulator. Xilinx providesVITAL compliant simulation modulesthat can be used with the SynopsysVSS simulator.
HDLs andSynthesis Tools
Continued from previous page
❝Device performance
and area utilization can be
optimized by creating HDL
code that takes advantage
of special FPGA
architectural features.❞
CONTINUED
25
7. Implementation of the design withthe automated “place & route” tools.
8. Timing simulation with a gate-levelsimulator.
In summary, an increasing number ofFPGA users are adopting top-downdesign methodologies using HDLs andlogic synthesis. While still not a pana-cea, synthesis technology is starting tolive up to its promise of enabling effi-cient, high-level FPGA design. ◆
3. Synthesis of the design’s modules intoXNF or EDIF netlists. The area andspeed requirements should be speci-fied before the design is synthesized.
4. Translation of the XNF file or EDIF fileinto a Xilinx Unified Library XNF file.
5. Functional simulation with a gate-levelsimulator (optional).
6. Floorplanning of structured designelements such as RPMs and on-chipmemory blocks to improve routabilityand performance (optional).
Measuring Speed and TemperatureAll CMOS circuits experience increased signal delay
with increasing chip temperature, typically about a onepercent speed degradation for every three degrees centi-grade temperature increase. This is a basic phenom-enon, and cannot be changed by any manufacturer.
A chip’s temperature is affected by ambient tempera-ture and device power dissipation. More specifically:
Tj = TA + PD * θJA
That is, the silicon junction temperature exceeds theambient temperature by the product of the dissipatedpower multiplied by the thermal resistance of the pack-age. This thermal resistance is primarily a function ofpackage size, package material, internal package struc-ture and air velocity.
SRAM-based FPGAs have no significant static powerconsumption. Practically all internal power dissipationis due to the dynamic charging and discharging ofcapacitive nodes. This makes it impossible to generalizethe device power consumption of Xilinx FPGAs; it canvary by orders of magnitude, depending on the applica-tion. Years ago, the power consumption was alwaysrelatively low because FPGAs were limited to less than5,000 gate density, were often not used fully and em-ployed clocks of 20 to 30 MHz. Today, capacity hasincreased beyond 20,000 gates, better software allows
utilization of up to 100 percent, and clock rates can gowell beyond 50 MHz. As a result, power dissipationcan be several watts for the largest FPGA devices run-ning at full speed.
This has rendered the traditional 70°C specificationunsatisfactory for most demanding applications.
Xilinx has responded to this problem. We are nowtesting commercial devices at 85°C and industrial de-vices at 100°C. The new edition of the 1994 DataBook (3rd edition) provides derating factors for higherjunction temperatures (0.35 percent per °C for XC4000devices, 0.30 percent per °C for XC3000 and XC2000devices). The thermal resistance for the various de-vice/package combinations, with derating values forairflow, are listed in this new edition as well.
The change to the higher test temperatures wasimplemented in April. All devices with date codes 9512or later are tested in this new manner.
SRAM-based or antifuse-based FPGA performanceparameters cannot be guaranteed at a specified ambi-ent temperature, independent of power consumptionand package type. Depending on the design, the clockrate and the package, the device junction temperaturemight vary by more than 50°C.
It is our goal to provide clearly-defined deviceparameters that are meaninful for the user. ◆
26
Board Level Simulation withBoard-level simulation capability has
been added to the OrCAD VST simulator inthe latest release, OrCAD VST 386+ v1.20.Users can now simulate a board-leveldesign containing multiple Xilinx FPGAsand EPLDs.
For board-level simulation, create eachXilinx design in its own directory. Withineach directory, route, back-annotate andsimulate the design at the chip level. Aftereach design has been verified, create aseparate board-level directory and enter theboard-level design. Copy the simulationfiles (.VST, .DBA) for the individual devicesinto the board-level directory. A board-level simulation can then be performed inthe board directory. The procedures areas follows:
Create the Simulation Model LibraryIn order to simulate designs in VST
v1.20, each device source file (.DSF) mustbe compiled in the VST v1.20 format. If youplan to simulate designs from differentXilinx families together or include compo-nents from other vendors on a single boarddesign, add those DSFs to the simulationmodel library using OrCAD VST’s Add
Device Model command for each file.The DSFs for Xilinx are available onthe Xilinx BBS as ORCSRC.ZIP. Thesource files are also available on theXACT 5.1 CD underXBBS\SWHELP\ORCSRC.ZIP.
Prepare Individual Chip DesignsEach FPGA/EPLD design should
be captured in OrCAD SDT 386+using normal procedures. Whenlabeling the signals connected to theI/O pads, use easy-to-identify, intui-tive names to facilitate the process ofcreating a chip symbol to representthe FPGA/EPLD. For board-level
simulation, these signal names provide thepoints of connectivity to the board-levelwires. Create names of 14 characters or
fewer to prevent the software from creatingshorter, random aliases.
After a design has been completed, use thefollowing commands to generate the simula-tion files:
1: xmake <design>(for EPLD designs, replace xmake withxemake)
2: xsimmake -f oft <design>(for EPLD designs, replace OFT with OET)
Once the simulation files are created andthe design verified, copy the simulation files(<design>.VST, <design>.DBA) to the boarddirectory.
Create a Library of Chip SymbolsBefore preparing the board level schematic,
create a library of symbols to represent eachdevice on the board (the procedure is de-scribed on pages 3-8 through 3-10 of the XACTOrCAD Interface User Guide, April 1994). Makecertain that the symbol’s pin names match theunderlying I/O signal names. In addition to theuser I/O signals, pins for the global signalsmust be added. The names of the global sig-nals are:• For the XC2000 and XC3000 FPGA devices,
the global reset signal is GR.• For the XC4000 FPGA devices, global set/
reset is GSR, and global tristate is GTS (ifSTARTUP is used, GSR and/or GTS are re-placed with user signals).
• For the XC7000 EPLD devices, global set/reset is PRLD.
Prepare the Board Level DesignOnce the custom symbol library is in place,
the board level schematic can be created usingthe normal OrCAD SDT procedures. In addi-tion to the user-created library, the board de-sign may also use libraries from other vendorsif their DSF files have been included. Oncethe board design has been captured, run AN-NOTATE on the schematic to update the refer-ence designators for the symbols in the sche-matic. Then, from within SDT, edit the
❝Once thecustom symbol
library is in place,the board level
schematic can becreated using the
normal OrCAD SDTprocedures.❞
CONTINUED
27
OrCAD VSTSHEETPART NAME for each Xilinx devicesymbol to add the following:
EXTERNALVIEW=<design>.SCH
where <design> is the root schematicworksheet for that particular chip. Afteradding the ‘externalview’ to all Xilinxdevices, save the schematic, and then runINET on the board schematic to create theboard-level INF simulation netlist.
Simulate the Board Level DesignPrior to simulating the board-level
design, set the SIMULATE local configura-
tion to Use all delay annotation files (includeseparate dba files). Verify that the libraryprefix for the digital simulation tools points tothe simulation model library created in theCreate the Simulation Model Library sectionabove. Simulate the board-level design using<board>.INF as the connectivity database.
A detailed application note with sampledesign files is available on the Xilinx BBS(Bulletin Board System) under the filename:VSTBSIM.ZIP. The application note is alsoavailable via the Xilinx XDOCS system ([email protected], document key 23012). ◆
A new, preliminary application note discussingFPGA configuration issues is now available on boththe XFACTS and XDOCS technical support systems.The application note is intended to help determineif you have a configuration problem and, if so,suggest likely solutions. (It complements the al-ready-exisiting application note, “FPGA Configura-tion Guidelines,” document #0010229-01).
To get the current revision of this new documentvia Fax from XFACTS, please call 408-879-4400 froma touch-tone telephone and press “1” to get moreinformation; this document is number 23021. If youare using the XDOCS E-mail system, this documentcan be ordered by sending the command “SEND23021” as the subject line or in the body of a mes-sage addressed to [email protected]. (To learn thebasics of XDOCS, please mail [email protected] the word help in the subject line.)
This application note navigates you through anumber of questions. Initially, you must determineif the problem is related to the configuration pro-cess or the functionality of the configured FPGA(Is there a problem with the functionality of a cor-rectly-configured device, or has the configurationactually failed?)
There are several clues as to whether or not theFPGA has been successfully configured:
Configuration Checklist Available1. INIT — If configuring from power-up, does INIT go
through a single positive transition from Low to High? Ifthe FPGA is not working after it is reprogrammed, is therea single negative transition (High to Low) on INIT, fol-lowed by a single positive-going transition?
2. DONE — Does DONE go High?.
3. I/Os —Are your I/Os at their active post-configurationlevels? HDC is High during configuration, and LDCshould be Low during configuration. Most other pinshave weak pullups during configuration. If you configurethe device to pass a clock signal in through an input andout through an output pad, does the output pin toggle atthe end of configuration? If you configure one user I/Oto drive Low at the end of configuration, and another todrive High, are both I/Os driving the proper logic levels atthe end of configuration?
4. Flip-Flops — Are your flip-flops toggling?
If you can answer YES to these questions, you can befairly certain that your FPGA has been configured properly,and that the problem involves the functionality of your de-sign, not the configuration method.
Please note that this document is preliminary and feed-back is very much appreciated; feedback can be sent byE-mail to [email protected] or by FAX to 408-879-4442. ◆
28
TECHNICAL QUESTIONS AND ANSWERS
GeneralQ: The Technical Support Hotline
hours are Monday through Friday,8:00AM - 5:00PM Pacific time. Isthere any way to get technical helpoutside of these hours?
A: Xilinx has implemented a fax-backsystem and an automated email server,both of which operate 24 hours a day.These systems will give you access tothe same database used by the Techni-cal Support Engineers.
The XFACTS automated fax-backsystem can send solution records andapplication notes directly to your faxmachine. Using a touch-tone phone,call 1-408-879-4400 and press “1” to getmore information.
The XDOCS email server can sendthe same information via the internet.For more information on this system,send an email to [email protected],with the word help in the subject line.
Q: When I try to install the software onmy PC, I get the message “Cor-rupted file on your media. DSxxxcannot be completely installed.”What should I do?
A: The Install program will give this errormessage if it cannot write a file or if itcannot verify a file that it has just triedto write. There are three possiblecauses of this message:
1) You don’t have write privileges tothe target directory.Not having write privileges preventsthe program from being able to open anew directory or overwrite existingDOS files, so check to make sure noneof the file attributes have been set toread-only. If you are installing on anetwork drive, make sure you arelogged in as someone whocan write to the destination area.
2) The PC has run out of memorybelow 640KB.In addition to being able to start theInstall program itself, PCs must haveenough memory to decompress thedata files stored on the CD or disks.Remove some drivers from theCONFIG.SYS and AUTOEXEC.BAT files,reboot the PC, and try the installationagain. If the Install program gets fur-ther but still fails, remove more driversand try again.
3) Problems exist with the setup of theCD-ROM drive.We have seen multiple cases, especiallywith the MSCDEX drivers, where theCD-ROM drive software has not beeninstalled correctly. Check to be surethat the proper parameters are set forthe driver. If all else fails, call the Tech-nical Support Hotline at 1-800-255-7778for more assistance.
XABELQ: While running AHDL2X v5.0 on a
Pentium 90 MHz PC, I receive amessage indicating that my keyis not authorized to run XABEL.What could be the cause of thisproblem?(Note: This question appeared inXCELL #16 with an incorrect de-scription of the solution.)
A: The XABEL 5.0 package includesexecutables supplied to Xilinx by Data I/O.Unfortunately, these programs were com-piled with an older version of the Rainbowkey software and will not run on somefaster machines, like the Pentium-90MHzand IBM PS/2 platforms. These programshave been re-compiled and updated in theXACT 5.1 release. They also are availableon the Xilinx BBS as XABEL.ZIP.
29
/* EXAMPLE FPGA COMPILER STARTUP FILE - .synopsys_dc.setup *//* FOR XC4000/A/H/D PARTYPES */search_path = { . \ <DS401-XACT-Directory>/synopsys/libraries/syn \ <SYNOPSYS_Directory>/libraries/syn}link_library = {xprim_4005-5.db xprim_4000-5.db xgen_4000.db \ xio_4000-5.db xfpga_4000-5.db}target_library = {xprim_4005-5.db xprim_4000-5.db xgen_4000.db \ xio_4000-5.db xfpga_4000-5.db}symbol_library = xc4000.sdbdefine_design_lib WORK -path ./WORKdefine_design_lib xblox_4000 -path \ <DS401-XACT-Directory>/synopsys/libraries/dw/lib/fpgasynthetic_library = {xblox_4000.sldb standard.sldb}compile_fix_multiple_port_nets = truexlnx_hier_blknm = 1xnfout_library_version = “2.0.0”bus_naming_style = “ percents< percentd>”bus_dimension_separator_style = “><“bus_inference_style = “ percents< percentd>”
OVERVIEW OF TECHNICAL SUPPORT FACILITIES
Automated Support SystemsTo provide timely support for new, high-growth mar-
kets, Xilinx Applications has established a series of E-mailaddresses to direct technical inquiries or to request infor-mation packets.Currently, these E-mail addresses include:Digital Signal Processing applications ...................... [email protected] applications .................................................. [email protected] and Play ISA applications ................................ [email protected] Transfer Mode applications ............... [email protected] questions should still be routed to ........ [email protected] card applications .................................. [email protected] logic/computing applications ... [email protected]
Other Xilinx interactive services include the XDOCSautomated document server, the XFACTS fax server, andthe Xilinx World Wide Web home page.
To access the XDOCS E-mail document server, send anE-mail to [email protected] with “help” as the only itemin the subject header. You will automatically receive fullinstructions via E-mail. The Xilinx home page is availableat http://www.xilinx.com. The XFACTS fax server isavailable by calling 1-408-879-4400.
Hotline Support, United StatesCustomer Support Hotline: ........................................ 800-255-7778
Hrs: 8:00 a.m. - 5:00 p.m. Pacific timeCustomer Support Fax Number: ................................ 408-879-4442
Avail: 24 hrs/day-7 days/weekElectronic Technical Bulletin Board: ......................... 408-559-9327
Avail: 24 hrs/day-7 days/weekCustomer Service: ............ 408-559-7778, ask for customer serviceFor software updates, authorization codes, documentation updates, etc.
Hotline Support, EuropeUK , LONDON OFFICE
telephone: (44) 1932 349402fax: (44) 1932 333530Bulletin Board Service: (44) 1932 333540e-mail: [email protected]
FRANCE, PARIS OFFICEtelephone: (33) 1 3463 0100fax: (33) 1 3463 0109e-mail: [email protected]
GERMANY, MUNICH OFFICEtelephone: (49) 89 991 5490fax: (49) 89 904 4748e-mail: [email protected]
SynopsysQ: I am just starting my first Xilinx
design with the Synopsys FPGACompiler. How should I set up my.synopsys_dc.setup file?
A: Below is a sample .synopsys_dc.setup filefor doing an XC4000 family design. Besure to edit the search path so that it pointsto the correct location of the libraries.
Manchester Decoder in 3 CLBsXilinx FPGA architectures are ideal for implement-
ing high-speed, efficient serial decoders. For example,the circuit illustrated below uses an eight-times over-sampling clock to decode Manchester-encoded data. Thecircuit requires only three CLBs in any XC3000, XC3100or XC4000-type device, and only two CLBs in anXC5200 device.
Manchester code is a self-clocking code with a mini-mum of one and a maximum of two level transitions perbit. A Zero is encoded as a Low-to-High transition, aOne is encoded as a High-to-Low transition. Betweentwo identical bits of data there is an extra level transitionwhich must be ignored by the decoder. The decoder,therefore, needs some information about the bit timing.Typically, the decoder has a clock with timing that is aknown multiple of the encoding clock.
This design assumes a decode clock at nominallyeight times the incoming data rate. After detecting avalid transition, the circuit ignores further transitions forsix clock periods. Thus, the circuit tolerates substantialfrequency errors between encoder and decoder.
Q0 and Q1 are XORed to detect any incoming levelchange. Q2/Q3/Q4 form a divide-by-six Johnsoncounter that locks up in the 000 state. (The illegal 010
state is also detected and changed to 000 on the next clockedge.) When the Johnson counter has timed out and is inthe 000 state, any incoming level transition generates apipelined STROBE signal which qualifies Q1 as DATA. Onthe next clock edge, the Johnson counter changes to 100,which terminates the strobe. For the following five clockperiods, any incoming level changes are detected, but theXOR output is ignored. When the Johnson counter againreaches 000, it locks up and enables the XOR signal. Anysimultaneously or subsequently detected level change startsa new operation as described above.
The decoder clock can be asynchronous to theincoming data, but must be faster than five times the in-coming bit rate (in order to detect the next bit transition),and slower than 12 times the incoming bit rate (in order tosuppress the between-bit transition). The nominal decodeclock frequency should, therefore, be eight times the in-coming data rate.
The circuit has been simulated for worst-case perfor-mance in excess of 200 MHz clock rate (25 MHz incomingdata rate) in an XC3120-2 device. The circuit uses onlythree CLBs — less than 5 percent of the logic availablein an XC3120 FPGA, and less than 1 percent of anXC3190 device. ◆
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3.3 Volt Programmable Logic Market SurveyWe are investigating the low voltage (3.3 V)market. If you are using or anticipate using3.3 V programmable logic devices in the future,please take a couple of minutes to fill out thisshort survey and send it back to us. Returnyour survey via FAX at 408-879-4676, or mail to:
Daniel ChanProduct MarketingXilinx Inc.2100 Logic DriveSan Jose, CA 95124
We sincerelyappreciate yourtime and effort.
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1. In which market(s) do you participate?❏ PCMCIA ❏ Computer Systems❏ PCI ❏ Memory Systems❏ ATM ❏ Computer Peripherals❏ Hand-held instruments❏ Other __________________________________________
2. Your company size (annual sales)?❏ < $10 million❏ $10 million - $100 million❏ > $100 million
3. Which type of 3.3V IC products do you think youneed or will need for your designs?❏ 3.0V to 3.6V (regulated power supply)❏ 2.7V to 3.6V (unregulated power supply)
4. In terms of the 3-V Programmable Logic Device mar-ket, please rank the following features in order ofimportance (1 - highest importance, 9 - lowest importance):
__ - speed of device/system clock rate
__ - quiescent current
__ - power consumption/dissipation
__ - supply voltage 3.0V - 3.6V Vcc only
__ - 5V tolerance (3V Vcc with 5V or 3V I/O)
__ - package style (PLCC, TQFP...)
__ - operating temperature (Commercial, Industrial, Military)
__ - price
__ - gate density
5. What is the predominant package style desired fora 3-V PLD device?❏ PLCC ❏ VQFP ❏ PQFP❏ TQFP ❏ ________________
6. What is your typical I/O requirement for a 3-V pro-grammable logic device (check one of the followingfor a and b)?a) ❏ < 86 I/O ❏ 87 - 100 I/O
❏ 100 - 150 I/O ❏ > 150 I/Ob) ❏ GTL ❏ TTL ❏ CMOS
For questions 7 - 11, please indicate the attributes thatyou estimate will be needed in 3.3V programmable logicdevices to meet your requirements.
7. Ambient operating temperature?❏ Commercial: 0°C to 70°C❏ Industrial: -40°C to 85°C❏ Military: -55°C to 125°C
8. Estimated gate density per device?(Select one column for each row.)
Gates < 3K 3K - 6K 6K - 10K > 10K
Today
1997
2000
9. Maximum quiescent current? (Select one column per row).
< 1µA 1µA-1mA 1mA-10mA > 10mA
Today
1997
2000
10. System clock speed? (Select one column for each row.)
< 33 34-50 51-66 67-100 > 100System Clock MHz MHz MHz MHz MHz
Today
1997
2000
11. Supply voltage-I/O option? (Select one row for each column.)
Today 1996 1997
IC with single operating voltageanywhere from 3V to 5V (speeddegradation at lower voltage)
Dual supply - 5V core and 3V or 5V I/O
Single 3V supply with 5V tolerant I/O
Single 3V supply only with 3V I/O
Other core and I/O combination:
3.3 V Fax Back SurveyTo: Daniel Chan, Product Please FAX your completed survey to (408) 879-4676 or mail to the address below
Marketing Manager, Xilinx Inc. by July 28 to be automatically eligible to win a Sony Watchman!
Personal (optional): Name _____________________________ Company ________________________ Phone: ( ) __________
If you choose not to fax this survey, mail it to:Daniel Chan, Product Marketing
Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124
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FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCELL Editor Xilinx Inc. FAX: 408-879-4676
From: ________________________________________ Date: ____________
❏❏❏❏❏ Please add my name to the XCELL mailing list.
NAME
COMPANY
ADDRESS
CITY/STATE/ZIP
PHONE
❏❏❏❏❏ I’m interested in having my company’s design featured in a future edition ofXCELL as a Customer Feature.
Comments and Suggestions: ___________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________
Please use this form to FAX in your comments and suggestions, or to request an addition to theXCELL mailing list. Please feel free to make copies of this form for your colleagues.
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CorporateHeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124Tel: 408-559-7778Fax: 408-559-7114
EuropeXilinx, Ltd.Suite 1B, Cobb HouseOyster LaneByfleetSurrey KT147DUUnited KingdomTel: 44-1-932-349401Fax: 44-1-932-349499
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Asia PacificXilinx Asia PacificUnit 2308-2319 Tower 1MetroplazaHing Fong RoadKwai Fong, N.T.Hong KongTel: 852-2410-2739Fax: 852-2494-7159
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