XFEL 2D Pixel Clock and Control SystemXFEL 2D Pixel Clock and Control System

Train Builder Meeting, DESYTrain Builder Meeting, DESY

4 December 20084 December 2008

Martin PostraneckyMartin PostraneckyMatt Warren, Matthew WingMatt Warren, Matthew Wing

4 Dec 2008 C+C 2

DetectorUnit

Eve

nt

Bu

ilder

F

arm

Rea

do

ut

Cra

te

C+

C

Cra

te Timing Receiver

Crate Proc-essor

C+C Master

C+C Slave

TrainBuilder

Crate Proc-essor

TrainBuilder

PC PC PC PC PC

Switch

Machine

Storage

Con

trol

s T

CP

/IP N

etw

ork

TrainBuilder

DetectorUnit

DetectorUnit

64k Pixel Unit

C+C Slave

XFEL 2D Pixel DAQ OverviewXFEL 2D Pixel DAQ Overview

4 Dec 2008 C+C 3

1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate :

- 5 MHz Bunch CLOCK

- Bunch train TRIGGER

- Event Number = TRAIN ID

- BUNCH PATTERN or Bunch PATTERN ID

2) To receive BUNCH VETO from Veto Hardware

3) To receive STATUS / ERROR ( and possibly Busy ?? ) from each FEE

4) To distribute to each FEE three fast lines :

- 100 MHz un-interrupted clock, phase-locked to 5 MHz Bunch Clock

- START pulse, followed by TRAIN ID, followed by PATTERN ID, followed by STOP signal

- BUNCH VETO signal

5) To process any BUSY information from crate controller to stop the following START pulse

6) To generate all Timing Signals in Stand-Alone mode without TR

7) To synchronise to other light sources’ Timing Systems, i.e. to accept external CLOCK

and possibly TRIGGER at different frequencies

8) To provide diagnostic and visual indication of CLOCK, TRIGGER, etc. performance and

presence / absence of any FEE

C+C HARDWARE : REQUIREMENTSC+C HARDWARE : REQUIREMENTS

4 Dec 2008 C+C 4

t1

T1

T2

T1+T2

5 MHz clock in

TRIGGER in

100 MHz clock out

TRIGGER out

VETO out

D2

D1

VETO in

INPUTS AND OUTPUTS – TIMING INPUTS AND OUTPUTS – TIMING RELATIONSHIPRELATIONSHIP

4 Dec 2008 C+C 5

μTCA Crate

Timing Receiver

Cra

te

Pro

cess

or

100 MHz Clock

Start/Info/Stop

Bunch Veto

FEE Status

C+C MasterFEE

C+C Fanout

C+C Fanout

C+C FanoutFEE

FEE

5MH

z C

lock

Trig

ger

+

Tel

egra

m

Bunch Veto

?

4

FEE

4C+C

FanoutSlave

XF

EL Timing

InterfaceOth

er1-

20M

Hz?

Clo

ck

Trig

/Dat

a

?

OverviewOverview

4 Dec 2008 C+C 6

C+C Master ClockC+C Master Clock

: 2XTAL

5MHz ClockFrom TR

Ext Clock0 – 20MHz?

Prog.Mult/Div

100MHz

MPX

FEE Clock

PLLMult

Local Clock200MHz

Prog. Delay

Standalone100MHz Prog.

Delay

MPX PLL

4 Dec 2008 C+C 7

C+C Master Trigger + InfoC+C Master Trigger + Info

Trigger+ Telegram From TR

FEE Trigger

Busy

Prog. Delay

External Interface

Ext. Trigger+ Info?

Trigger Pulse

Train ID

Bunch Pattern BPID

Clock 100MHz

ETrigger Pulse

?

SA Trigger Pulse

SA Train ID

SA Bunch Pattern

XFEL Interface

Select +

Process +

Store

Standalone Trigger +

Info

LUT

4 Dec 2008 C+C 8

C+C SlaveC+C Slave

100 MHz Clock

Start/Info/Stop

Bunch Veto

FEE Status

C+

C M

aste

r Li

nk

Fa

n-o

utF

an-

out

Sync?

Fa

n-o

ut

Prog. Delay

Prog. Delay

Prog. Delay F

EE

C+

C L

ink

Fa

n-in

x8

Front-panel? Back-plane? Wireless??? ;-)

Crate data interface?

Front panel (rear?) space?

?

?

?

4 Dec 2008 C+C 9

1) TRIGGER “Telegram” from TR : - same line / different lines for TRIGGER, Train ID, Bunch Pattern ??1) TRIGGER “Telegram” from TR : - same line / different lines for TRIGGER, Train ID, Bunch Pattern ??

- Bunch Pattern or Pattern ID ? ( Pattern ID look-up table on - Bunch Pattern or Pattern ID ? ( Pattern ID look-up table on C+C ?? )C+C ?? )

2) FEE feedback line : Status only ( e.g.. Normally floating high, pulled low by FEE when powered ),2) FEE feedback line : Status only ( e.g.. Normally floating high, pulled low by FEE when powered ),

or will contain information ( e.g.. go high when ‘busy’ or ‘error’ ) ??or will contain information ( e.g.. go high when ‘busy’ or ‘error’ ) ??

3) External clock input at other test sites : - 20 MHz range ?? 3) External clock input at other test sites : - 20 MHz range ??

- Always use internal 100MHz clock or PLL to different - Always use internal 100MHz clock or PLL to different clock ??clock ??

4) Bunch Veto signal – how fast / latency ??4) Bunch Veto signal – how fast / latency ??

5) Calibration Pattern ?? ( pre-loaded into a memory on C+C ?? )5) Calibration Pattern ?? ( pre-loaded into a memory on C+C ?? )

6) Veto Disable Pattern ??6) Veto Disable Pattern ??

7) 100 MHz clock output : - max. jitter ??7) 100 MHz clock output : - max. jitter ??

- programmable delay / step size ??- programmable delay / step size ??

8) Output Clock / Start/Stop pulses phase relationship : - only adjustable on C+C Master, i.e. same for all 8) Output Clock / Start/Stop pulses phase relationship : - only adjustable on C+C Master, i.e. same for all FEEs ?? FEEs ??

- same cable length for all FEEs ??- same cable length for all FEEs ??

- or individual delay adjustments on each C+C - or individual delay adjustments on each C+C FanOut => more complex FanOuts ?? FanOut => more complex FanOuts ??

MORE INFORMATION / QUESTIONS -1-MORE INFORMATION / QUESTIONS -1-

4 Dec 2008 C+C 10

9) Connection between C+C Master and FanOuts : - on custom backplane all signals / 9) Connection between C+C Master and FanOuts : - on custom backplane all signals / FEE feedbacks only ??FEE feedbacks only ?? - use single or double FanOut layer ??- use single or double FanOut layer ??

10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ??10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ?? - separate ‘dumb’ FanOut cards and crate ??- separate ‘dumb’ FanOut cards and crate ?? - on / near detector => fewer cables ?? - on / near detector => fewer cables ??

11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs - Double-stack RJ45 – availability / height ??- Double-stack RJ45 – availability / height ?? - HDMI - size / more signal pairs / more grounds/shielding ??- HDMI - size / more signal pairs / more grounds/shielding ??

- Double stack HDMI - size ?? - Double stack HDMI - size ?? - mini-HDMI ??- mini-HDMI ??

12) Is there 12) Is there any C&C System interface to MPS ( Machine Protection System ) ??any C&C System interface to MPS ( Machine Protection System ) ??

MORE INFORMATION / QUESTIONS -2-MORE INFORMATION / QUESTIONS -2-