Xilinx DSP Model-Based Design Solutionsdata.eefocus.com/openhard/source/94dcc7439fe02e0e4e10ee97027843… · Xilinx DSP Model-Based Design Solutions. ... Library of over 90 Xilinx

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Xilinx DSP Model-Based Design Solutions


Copyright © 2007. Avnet, Inc. All rights reserved.

2Course Goals

Present the integrated Xilinx model-based DSP design flows and their benefits

Demonstrate how AccelDSP explores and implements a MATLAB design in a Xilinx FPGA

Show how System Generator 9.1 uses Simulink to integrate system-level designs into FPGA hardware



3Agenda

Why use FPGAs for DSP?Model-based design conceptsXilinx DSP tool flowsAccelDSP 9.1DemoSystem Generator 9.1DemoSynplify™ DSP OverviewSummary & Questions



4Agenda




5DSP Performance GapPe

rform

ance

(GMA

Cs*)

(Algo

rithmi

c and

Pro

cess

or F

orec

ast)

Time

Algorithm Complexity

–Shannon’s L

aw

350 GMACs

Source: Jan Rabaey BWRC

Virtex-DSPVirtexVirtex--DSPDSP

Spartan-DSPSpartanSpartan--DSPDSP

DSP/GPP Performance Limit

* 18x18 multiply and 48-bit accumulate

• Ultrasound• Pico/Femto Base Stations• Consumer Video • Video Surveillance• Mobile Software Defined Radio

• 3D Medical Imaging• Base Stations• HD Audio/Video Broadcast• Radar & Sonar• HD Video Surveillance• Mounted Software Defined Radio• MIMO

30 GMACs

1 GMACs



6Power of Parallel Processing

256-tap filter implementation is 100 times faster256-tap filter implementation is 100 times faster

.

Data OutData Out

MAC UnitMAC Unit

CoefficientsCoefficients

Programmable DSP Programmable DSP -- SequentialSequential

1 GHz1 GHz1 GHz256 clock cycles256 clock cycles256 clock cycles = 4 MSPS= 4 MSPS= 4 MSPS

256 clock 256 clock cycles cycles

neededneeded

Data InData In

XX

++RegReg

400 MHz400 MHz400 MHz1 clock cycle1 clock cycle1 clock cycle

= 400 MSPS= 400 MSPS= 400 MSPS

FPGA FPGA -- Fully Parallel ImplementationFully Parallel Implementation

Data OutData Out

XX

++

C0C0 C0C0XXC1C1 XXC2C2 XXC3C3 XXC255C255…

RegReg

RegReg

RegReg

RegReg

RegReg

RegReg

RegReg

RegReg

++ ++ ++ ++RegReg

RegReg

RegReg

RegReg…

…Data InData In



7

Tri-Mode Ethernet

Xilinx Enabling Technology

Dual-Port Block RAM /

FIFOup to 10Mbits

ECC and Interconnect

FIFO Logic

18 Kbit

18 Kbit

DSP SlicesUp to 640 at

550MHz = 500MSPS

DCMDCMPLL

Clock Management550 MHz DCM + PLL

.



8Virtex-5 SXT / Spartan-DSP Family

94,208

52,224

34,816

Logic Cells

16

12

8

GTP 3.2Gbps

Transceivers

4

4

4

Ethernet MAC

Blocks

1

1

1

PCI ExpressEndpoint Blocks

68784640XC5VSX95T

64752288XC5VSX50T

23024192XC5VSX35T

Clock Mgmt Tiles

Block Memory(kbits)

DSP48E Slices

53,712

37,440

Logic Cells

2,268126XC3SD3400A

1,51284XC3SD1800A

Block Memory(kbits)

DSP48A Slices



9Agenda




10Problems in Traditional Development

Design Implementation Test and Verification

Requirements and

Specifications

Text-based- Prevents rapid

iteration

Simulation - Incomplete and

expensive

Manual coding - Introduces

human errors

Traditional testing

- Errors found too late



11Advantages of Model-Based Design

Executable Models

Design Implementation Test and Verification

Requirements and Specifications

Continuous verificationModel elaboration

Automatic Code Generation

Test with Design

Simulation

….



12The Platform For Model-Based Design

The leading environment for technical computing

The leading environment for modeling, simulating, and implementing dynamic and embedded systems

.



13Model-Based Design Environment

Real-timeWorkshop

Blocksets(video, comms, etc.)

Toolboxes(signal, comms, etc.)

ANSI C forMCUs & DSPs

HDL for Xilinx FPGAs



14Agenda




15Xilinx Model Based Flows

MATLAB®

Generate

Simulink w/ System Generator



16Challenges In Moving Algorithms to Silicon

Design problem - Kalman Filters– Commonly used for

• Satellite tracking, robotics, position and velocity systems– Complexity depends on size of system being estimated

• Linear algebra• Matrix operations

How do you move this model into an FPGA?

On paperMATLAB Plot



17Benefits of AccelDSP 9.1

Automates manual stepsProvides ability to analyze design tradeoffs at each stageIntegrated design environment

Manual Design Steps

AccelDSP Design Flow

Steps performed by AccelDSP

RTL Synthesis

AccelDSP / AccelWare

Floating-Pt. Algorithm

RTL Synthesis

Verify RTL

Refine Architecture

Create RTL Design

Create / Integrate IP Blocks

Architecture Definition

Fixed-Point Conversion


Manual Design Steps

AccelDSP Design Flow

Steps performed by AccelDSP

RTL Synthesis

AccelDSP / AccelWare


RTL Synthesis

Verify RTL

Refine Architecture

Create RTL Design





RTL Synthesis

Verify RTL

Refine Architecture

Create RTL Design





RTL Synthesis

Verify RTL

Refine Architecture

Create RTL Design











18Fixed-Point Conversion

Automatically generates a fixed-point model from the floating-point model– The floating-point model is

treated as “Golden Source”– User interactive and

controllable

Fixed-point analysis tools– Addresses reduced-precision

arithmetic errors– Accel_probe overlays both

floating-point and fixed-point



19Design Architecture Information

AlternativeArchitectures

Loops

Summary highlights areas available for design exploration

Alternative architectures

Loops that can be rolled and unrolled



20“Destination” Based Flows

AccelDSP compiles to multiple destinations– ISE– System Generator– HW Co-Simulation

ISE

SystemGenerator

HWCo-Sim

Intelligent Flow Bar automatically takes the user to the appropriate step in the design flow



21Vector and Matrix Multiply Operations

The computational power of MATLAB is its ability to handle linear algebra

AccelDSP understands matrices and vectors natively

Allows designer to quickly evaluate both parallel and resource-shared (rolled) implementations

a * b = c



22AccelDSP 9.1 DEMO

Kalman Filter – Simply an optimal recursive data processing algorithm

All matrix operations all the timePredict

Update

Project One Step Ahead

Enter loop

Compute filter gain

Measurement

Update filter estimate

Update filter error covariance matrix



23Separate the Hardware Part into a Function

%Kalman filter examplerand('state',0);t=0:0.001:2;A(:,1) = cos(0:pi/400:(5/3)*pi)/2;A(:,2) = sin(0:pi/200:(10/3)*pi)/2;A(:,3) = sin(0:pi/100:(20/3)*pi)/2;A_in = A + 0.5*(rand(size(A))-.5);DIM = size(A,2); LEN = size(A,1);

for i = 1:LEN[S(i,:)] = kalman_filter(A_in(i,:));

end

function [S] = kalman_filter(A)DIM = size(A,2);

persistent p P_capif isempty(P_cap)

P_cap = [8 0 0;0 8 0; 0 0 8];p = ones(DIM,1)/2;

end;

I = eye(DIM);R = [128 0 0;0 128 0; 0 0 128];

P_cap_est = P_cap+I;

% correction step:K = P_cap_est * inv(P_cap_est+R);p = p + K * (A' - p);P_cap = (I - K)*P_cap_est;S = p';

%Kalman filter examplerand('state',0);t=0:0.001:2;

A(:,1) = cos(0:pi/400:(5/3)*pi)/2;A(:,2) = sin(0:pi/200:(10/3)*pi)/2;A(:,3) = sin(0:pi/100:(20/3)*pi)/2;A_in = A + 0.5*(rand(size(A))-.5);DIM = size(A,2);LEN = size(A,1);DIM = size(A,2);

I = eye(DIM);R = [128 0 0;0 128 0; 0 0 128];P_cap_est = P_cap+I;% correction step:K = P_cap_est * inv(P_cap_est+R);p = p + K * (A' - p);P_cap = (I - K)*P_cap_est;S = p';

Script File

Design Function

MATLAB .m file

MATLAB Stimulus

DUT(design function)

MATLABAnalysis

Block diagram view



24Steps Needed For Demo

1. Designer parses MATLAB into separate filesa) Script (non-synthesizable)b) Design function (synthesizable)

2. Verify script file in floating point3. Analyze – is it synthesizable?4. Generate fixed point model (MATLAB)5. Explore architectural options6. Verify fixed point model (MATLAB)7. Generate RTL

a) VHDL and testbench8. Verify RTL – simulate in ISIM9. Generate System Generator block

MATLABenvironment

AccelDSPenvironment



25Agenda




26Agenda




27Xilinx Model Based Flows

MATLAB®

AccelDSP

Generate

Simulink w/ System Generator



28System Generator Integration

Design DSP applications in FPGAs without hardware design experience

Library of over 90 Xilinx optimized DSP building blocks

Embed MATLAB m-code

Integrate VHDL or Verilog code

ParameterizeIP Blocks

Import AccelDSP designs

Xilinx Reference Designs

…..



29FIR Filter Generation

FIR Compiler quickly generates performance optimized FIR filters

– Automatically implements DSP48 blocks to achieve up to 550 MHz performance in Virtex-5

– Supports multi-rate, oversampled, multi-channel and coefficient optimization

MathWorks FDA Tool integration provides graphical filter design and coefficient generation

FIR Compiler

FDA Tool



30

PLB Arbiter

PLB-OPB Bridge

OPB Arbiter

High-Speed DSP Block Memory

Controller UART Memory Controller

EmbeddedProcessor

Dat

a

Inst

ruct

ion

IP Core . . . IP Core

On-chip Peripheral Bus (OPB)

FPGA

High-speed Data

Converters

DDR/DDR2 Memory

RS232 Connector Flash

Embedded Processor Design

DSP system can be quickly implemented as a peripheral to a Xilinx embedded processor– Integration to Xilinx Platform Studio– Interface details abstracted away through a shared

memory interface

System Generator

Platform Studio pcorePlatform Studio pcore

Platform Studio



31Automatic HW/SW Interface Generation

Includes the software API and hardware components of a processor-to-peripheral interface– Traditionally requires both HW and SW design skills

– Time consuming even for experienced designers

System Generator automatically generates the HW/SW interface

Software DSP Hardware

SW API HW Interface

Memory Map / Address decodeDriver Files

Header Files Hardware Interface Logic

C Program RTL

HW / SW Interface



32Hardware Co-Simulation

Automated HW Co-Simulation– Up to 1000x simulation

performance improvement

Push-button flows target over 20 commercially available evaluation boards

989X.75742OFDM BER Test

69x4277Color Space Converter

113X9210422Video Scalar

32X23731DUC CFR

45X2.5113Beamformer

IncreaseHW Co-SimSoftware

Simulation Time (Seconds)Design



33What’s New in System Generator 9.1?

New device support– Complete Virtex-5 support in version 9.1– Complete Spartan-DSP support in Service Pack 1

HW Co-Simulation BSPs for new evaluation boards– Virtex-5 LX Evaluation Kit– Virtex-5 LXT/SXT Evaluation Board– Spartan-DSP Co-Processing Starter Kit– ML506 with Virtex-5 SXT50T– Spartan-DSP Starter Kit



34Enabling IP & Reference Designs

Digital Communications– Digital pre-distortion (DPD)– WiMAX (IEEE802.16e) Digital Front End– WCDMA Digital Front End– J.83Modulator, A/C and B IP cores

Video & Imaging– Video Surveillance (VoP)– Video Blockset

• Polyphase Scaler• Color Space Converter - RGB2YCrCb and YCrCb2RGB• Chroma Resampler• 2D FIR Filter• 2D Rank Filter



35Complete Digital Front End (DFE) Radio Design

Advantages Over Traditional Multi-Chip Solutions– Multi-gigabit transceivers allow lower cost single chip DFE solution– 30% lower power reduces PSU costs and increases reliability– Higher frequency reduces cost / channel

CFR Processor

DSPProcessing

8 ch DDC

DSPProcessing4 ch DUC

DPDStand-alone

ASSPCPRI

SERDES(Discrete PHY x2)

1W

2.0W

1.65W$35

$50

$29

$4 300mW

$40 2.0WDAC

ADC

ADC

ADC



36Agenda




37System Generator 9.1 Demo

1. Integrate and simulate AccelDSP design from first demo in a System Generator model

2. Generate Digital Front End (DFE) decimating filter using FIR Filter Compiler and FDA Tool– Demonstrate Hardware Co-Simulation over Gigabit

Ethernet on Avnet’s Virtex-5 LX50 evaluation platform

100 MSPS 20 MSPSSample Rates

Icos

sinDDS

Q

LPF 5 LPF

LPF 5 LPF

SampledIF Input



38Agenda




39Synplicity’s Synplify DSP

Model-based Design Flow– Simulink-based environment– Floating to fixed-point conversion– Integrated flow using Synplify Pro– Full RTL Generation

Unique System Optimization– Explore multiple architectures– Retiming for performance– Folding for area (cost)– Multi-channelization for

productivity

HDL Co-SimulationExport to System Generator

RTL

Synplify DSPBlockset

Synplify DSPSynthesis Engine

Synplify Pro

Simulink®



40Synplify DSP Design Optimizations

x x x

DRst

En

Q + DRst

En

Q +

c1 c2 c3

DRst

En

QD

Rst

En

QD

Rst

En

QD

Rst

En

Q

x x x

DRst

En

Q + DRst

En

Q +

c1 c2 c3

x

+ DRst

En

QD

Rst

En

QD

Rst

En

Q

x x x

DRst

En

Q + DRst

En

Q +

c1 c2 c3

System-level Retiming– System level re-timing/pipeline insertions– Improves performance

Folding– Fast, accurate speed-area tradeoffs– Shares resources like multipliers – Enables optimization of high-volume

designs for cost

Automatic Multi-channel capability– Creates a multi-channel system from a

single channel spec– Quickly determine optimal number of

channels before implementation

…



41Agenda




42Part of Xilinx’s Complete DSP Solution

AccelDSPOne golden MATLAB sourceFloating- to-fixed-point conversionDesign explorationAlgorithm explorationAutomated verificationSystem Generator integration

System GeneratorSimulink-based designMixed language design environmentOver 90 optimized Xilinx DSP blocks

MATLAB®



43Minimum Tool Requirements

Signal Processing Toolbox $ 800Signal Processing Blockset $ 1,000Communications Toolbox $ 1,000Communications Blockset $ 1,000

• All tools require the Xilinx ISE software for implementation• Prices shown are suggested list USD

System Generator $ 995

MATLAB $ 1,900

Simulink $ 2,800

Total: $ 5,695

AccelDSP $ 4,995

MATLAB $ 1,900

Total: $ 6,895

System Generator Flow

MathWorks DSP Recommended Options

AccelDSP Flow



44What’s Next

Contact your Avnet FAETake home the software– Evaluation copies of MATLAB/Simulink on your CDs– Download Xilinx tools at www.xilinx.com/download

• 30 day trial of AccelDSP• 60 day trial of System Generator

Get evaluation boards– Avnet bundles available for all X-Fest attendees

Attend Avnet’s Fall Speedway workshops


Appendix



46XtremeDSP Device Portfolio

94,20852, 22434, 81655, 29634,56023,04053, 71237,440Logic Cells

224 x 1+ Gb/s LVDS pairs

3,456

240

27x27

192

5002

6,9122

962

4VSX35

120 x 1+ Gb/sLVDS pairs

2,304

160

27x27

128

5002

4,6082

642

V4VSX25

180 x 1.25 Gb/s LVDS pairs,

8 x 3.2 Gb/sTransceivers

3,024

520

27x27

192

5502

6,6532

1062

5VSX35T

360 x 1+ Gb/s LVDS pairs

5,760

384

27x27

512

5002

11,5202

2562

4VSX55

Virtex-4 SX

320 x 1.25Gb/s LVDS pairs, 16 x 3.2 Gb/s Transceivers

240 x 1.25 Gb/s LVDS pairs,

12 x 3.2 Gb/sTransceivers

213 x 622+ Mb/s LVDS pairs

227 x 622+ Mb/s LVDS pairs

High Speed Connectivity

8,7844,7522,2681,512Block RAM (Kb)

1,520780373260Distributed RAM (Kb)

27x2727x2719x1919x19Min Footprint (mm)

64028812684XtremeDSP DSP48* Slices

5502550225012501Max DSP Frequency (MHz)

19,325210,45422,26811,5121Max Block RAM

Memory Bandwidth (Gbps)

35221582321211DSP Performance (GMAC/s)

5VSX95T5VSX50T3SD3400A3SD1800A

Virtex-5 SXTSpartan-3A DSP

Virtex-DSPSpartan-DSP

1 In Slow Speed Grade 2 In Fast Speed Grade



47DSP48 Comparison

Supports fast carry functions between DSP blocks. Often a speed limiting path.

Carry In & Out

Carry In & Out

Carry InCarry Signals

Enables parallel ALU operations on multiple data sets.

NoYesNoSIMD ALU Support

This feature supports convergent rounding, underflow/overflow detection for saturation arithmetic, and auto-resetting counters/accumulators.

NoYesNoPattern Detect

Similar to the ALU of a microprocessor. Enables the selection of ALU function on a clock cycle basis Enables multiple functions to be selected. (Add, Subtract, or Compare)

NoYesNoALU Logic Functions

One DSP48 can now provide more than one function.. Multiply, Multiply-add, multiply-accumulate etc.

YesYesYesDynamic Opmodes

Supports simple add and accumulate functions.2 input 48 bit

3 input 48 bit3 input 48 bit

Adder

The C input supports many 3-input mathematical functions, such as 3-input addition and 2-input multiplication with a single addition and the very valuable rounding of multiplication away from zero.

YesYesNoDedicated C input

Enables fast data path chaining of DSP48 blocks for larger filters.YesYesYesCascade Output

Enables fast data path chaining of DSP48 blocks for larger filters.OneTwoOneCascade Inputs

Reduces the critical path timing in FIR filter applications better performance. Import in FIR filter construction.

YesNoNoPre-Adder

Reduces FPGA resource needs for DSP algorithms.18 x 1825 x 1818 x 18Multiplier

BenefitDSP48ADSP48EDSP48Function



48IP Support in 9.1.01

v1.1DDS Compilerv1.0CIC Compiler (Sept 2007)

v3.3FIFOv3.3Distributed Memory Generatorv2.4Block Memory Generatorv9.1BaseBloxV10Multiplierv5.0Interleaver/Deinterleaverv6.0Convolutional Encoderv6.0Viterbi v6.0v6.0RS Encoder/Decoderv3.0FIR Compilerv4.1FFT

Virtex-5 & Spartan-DSP



49Avnet Virtex-5 LX Development Platform

Board features– XC5VLX50-1FF676– 16M x 32 DDR2– 4M x 16 of Flash– 10/100/1000 PHY– 10-bit LVDS Rx and Tx– Cypress USB 2.0– RS232 Serial Port– EXP Expansion Slot– Clocks

• Programmable LVDS• 100 MHz LVTTL

Oscillator• LVTTL Oscillator

Socket– 32P Platform Flash– JTAG Port– BPI Configuration– SystemACE interface



50Point-to-Point Hardware Co-Simulation

Tri-mode point-to-point Ethernet Co-simulationConfiguration over JTAG / Co-simulation over Ethernet

Hardw

are In- the-Loop C

o-sim

ulationH

ardware In

- the-Loop Co

-simulation

Dedicated Point -to-point Connection

Ethernet Co -simulationCommand ProcessorInterface

CommandProcessor

HardwareCo-simulation

Interface

Ethernet MAC

ClockGeneration

Ethernet PHY

Egress Unit

BRAMs

IngressUnit

Filter

BRAMs

Control

Design Under Test

FPGA

PPEthernetCosim Engine

Ethernet NIC Driver

Ethernet NIC

OS Kernel

Userspace

HOST System Generator for DSP

WinPcap BPF Filter

Dedicated Point -to-point Connection


CommandProcessor


Interface

Ethernet MAC

ClockGeneration

Ethernet PHY

Egress Unit

BRAMs

IngressUnit

Filter

BRAMs

Control

Design Under Test

FPGA


CommandProcessor


Interface

TEMAC Core

ClockGeneration

Ethernet PHY

Egress Unit

BRAMs

Egress Unit

BRAMsBRAMs

IngressUnit

Filter

BRAMs

IngressUnit

Filter

BRAMsBRAMs

Control

Design Under Test

FPGA


Ethernet NIC Driver

Ethernet NIC

OS Kernel

Userspace


WinPcap BPF Filter


Ethernet NIC Driver

Ethernet NIC

OS Kernel

Userspace


WinPcap BPF Filter

FPGA Configuration

FPGA Configuration

Documents

Xilinx DSP Model-Based Design Solutionsdata.eefocus.com/openhard/source/94dcc7439fe02e0e4e10ee97027843… · Xilinx DSP Model-Based Design Solutions. ... Library of over 90 Xilinx