Zero-voltage Zero-current Switching Scheme for Charge-pump

IEEJ Journal of Industry ApplicationsVol.9 No.4 pp.366–375 DOI: 10.1541/ieejjia.9.366

Paper

Zero-voltage Zero-current Switching Scheme forCharge-pump Based Dual Boost Converter

Mummadi Veerachary∗ Non-member, Jyoti Prakash∗ Non-member

(Manuscript received June 4, 2019, revised Dec. 6, 2019)

In this paper a modified zero-voltage zero-current transition network (MZVZCTN) is proposed for a charge-pumpbased dual boost converter. The proposed soft-switching network consists of two diodes, an auxiliary switch and aresonating inductor. To prevent the failure of zero-current transition of the main switches, auxiliary-capacitors areconnected across the diodes of the soft-switching network. The high boost ratio is realized with charge-pump capacitorintroduced on the load side. The MZVZCTN network is activated two times in a switching cycle in order to ensurezero-voltage turn-ON and zero-current turn-OFF of the main switching devices. Furthermore, the proposed networkalso ensures zero-current turn-OFF of the main diodes and does not impose any extra voltage stresses on the devices.The converter can operate at a constant frequency of operation with pulse width modulated control. A 460 W proto-type operating at a frequency of 50 kHz is constructed, soft-transitions of the devices and improvement in efficency isvalidated through experiments.

Keywords: DC-DC converter, high voltage gain, PWM control, soft-switching

1. Inroduction

Boost based non-isolated converter topologies have beenextensively used in high power applications owing to theirsimplicity and ease of implementation. However, in such ap-plications, the voltage and current stresses on the switchesand diodes are sufficiently high when a conventional boostconverter (CBC) is employed. The applications with highvoltage boosting requirement demand higher duty ratio of op-eration. Handling the stresses of the devices at these dutyratios is even more challenging. Further, the diode reverserecovery during the turn-OFF transition creates significantlosses, and thus reduces the power converter efficiency (1) (2).

Multiphase converters, based on boost or buck, with inter-leaved operation play a significant role where efficiency isof prime concern. Interleaving not only reduces the currentripple but also helps in the ripple reduction in the load volt-age. A two-cell interleaved boost converter (IBC) is widelyused in many applications (2)–(12). Though the voltage gain ofan IBC is same as that of conventional boost converter, butit offers the benefit of ripple reduction at the source and loadside. In (5), an attempt has been made to increase the voltagegain of IBC by adding a voltage multiplier (VM) cell whilestill preserving the ripple reduction features. A basic VM cellrealization needs two diodes and two capacitive elements andhence simple cascading of IBC with VM increases the totalnumber of devices. An additional capacitor along with thealready existing output diodes of an IBC can also be used toform a VM-cell. Therefore, the cascading of IBC’s input cellwith output VM-cell forms a charge-pump based interleavedboost converter (5)–(8) with a voltage gain twice that of the IBC∗ Department of Electrical Engineering, Indian Institute of Tech-

nology DelhiHauz Khas, New Delhi - 110016, India

gain. The presence of the back-end VM-cell facilitates highvoltage gain at moderate duty ratios. Furthermore, the volt-age stress on all the power switches is reduced to half andhence, lower voltage rated devices are sufficient enough toachieve higher efficiencies at low cost. An exhaustive studyon the usage of Si and SiC devices in interleaved boost con-verters has been reported in (9).

In power electronic conversion, the use of high perfor-mance high frequency switching devices along with opti-mized energy storage elements is more common to achievehigh power densities. At high frequency switching, attain-ing higher efficiencies in the dc-dc converters is the key issueand it is possible only if substantial reduction in the transi-tion losses is achieved. In hard-switching dc-dc converters,these switching losses at turn-ON and turn-OFF increase withthe increase in switching frequency. To minimize the transi-tion losses, numerous soft-switching techniques have beendiscussed in the open literature (10)–(26). Zero-voltage transition(ZVT) and zero-current transition (ZCT) networks for pulsewidth modulation (PWM) converters is proposed in (9), (10).These networks retain the fixed-frequency control of the con-verter without imposing additional stresses on the switchingdevices unlike quasi resonant converters. Furthermore, thesenetworks are capable of ensuring either zero-voltage turn-ONor zero-current turn-OFF but not both simultaneously.

A ZVT non-isolated high step-up converter has beendemonstrated in (10). The converter suffers from a very nar-row range of PWM control as the circuit is operational onlyfor duty cycle greater than 0.5. The major concern withthe bidirectional converters used for soft-switching (12)–(14) isthat the inductor current ripple magnitudes are considerablyhigh. In (13), zero-current turn-ON and zero-voltage turn-OFF of the main switches of the coupled inductor based IBCis dealt with. It provides soft-transitions at the expense of

c© 2020 The Institute of Electrical Engineers of Japan. 366

ZVZCS Scheme for CP Based Dual Boost Converter（Mummadi Veerachary et al.）

two additional auxiliary switches and their associated drivers.An n-cell single inductor based ZVT network is reported forIBC in (15). This solution needs more number of auxiliaryswitches and the corresponding gate-drive requirement is alsohigh. A modified ZCT-cell with reduced number of resonat-ing inductors is reported in (18), but this cell is introducedbetween the IBC cell and the load. A non-dissipative soft-switching cell is proposed (21) for the IBC to achieve ZCT.The conventional ZVT network (10) is based on an auxiliaryswitch and a diode, however the network proposed in (23)uses only one auxiliary switch for successful ZVT. There-fore, the loss involved in the auxiliary diode is eliminated.A zero-voltage switching (ZVS) commutation cell, (basedon four diodes, two inductors and three capacitors) was pro-posed in (24) for IBC. It gives successful ZVT to the mainswitches but the number of elements in the auxiliary transi-tion network is more.

Soft-switching of the coupled inductor based IBC withsingle auxiliary switch was reported in (25). Although thisscheme is effective in achieving ZVT, but the turn-OFF of themain switches takes place in hard-transition mode at lowercurrents. A zero-voltage turn-ON zero-current turn-OFF net-work is presented in (26) for a high boost-up interleaved con-verter wherein the adopted auxiliary switch gating schemeensured ZVT turn-ON of one of the main switch with ZCTturn-OFF of the other main switch. The ZVT of the mainswitches is guaranteed for most of the loads, but the suc-cess of ZCT depends on the equivalent impedance offeredby the parallel path constituted by the main switch conduct-ing channel, second main switch anti-parallel body diode,and non-ideal characteristics present in the respective path.The ZCT of the switch is guaranteed only if the equivalentimpedance of this parallel path is less than the ZVT switchpath impedance and in the realistic circuit, the probability ofrealizing such a condition is very less. Furthermore, the suc-cess of ZCT also depends on the ‘i-v’ characteristics of theauxiliary diodes, the output capacitances of the main switchesand the circuit layout stray inductances of the two parallelpaths. Hence, the ZCT of the outgoing switch is guaranteedonly if the equivalent impedance of ZCT switch path is lessthan the ZVT switch path.

To overcome these limitations and to have ZVT of the in-coming switch together with successful ZCT of the outgoingswitch, a modified zero-voltage zero-current transition net-work (MZVZCTN) is proposed in this paper for a charge-pump based dual boost converter (CPBBC). In this paper, thecircuit description and principle of operation of MZVZCTNCPBBC has been presented in Section 2. The design con-siderations of the proposed converter is discussed in Section3. Results and discussions are given in Section 4. Finally,Section 5 covers the conclusions.

2. Principle of Operation and Operating Modes

A. Circuit DescriptionThe circuit diagram of a proposed zero-voltage zero-

current transition charge-pump based dual boost converter(ZVZCDBC) is shown in Fig. 1. The inductors L1 and L2,switches S 1 and S 2, diodes D1 and D2 and charge pump ca-pacitor C1 form a high gain boost converter. The input induc-tor L along with its feed-forward path capacitor C3 constitutes

Fig. 1. Circuit diagram of the proposed ZVZCDBC

a filter and effectively reduces the input source current ripple.The modified ZVZCT-cell (indicated in Fig. 1 with rectangu-lar dotted box) consists of a resonating inductor Lr, auxiliaryswitch S a, auxiliary diodes Dr1, Dr2, capacitors CDr1, CDr2

and Csa. The operation of the proposed ZVZCDBC dependson the duty ratios of the main switches and auxiliary switch.The control schemes analyzed in this paper are: (i) Type-Acontrol: the main switches’ duty ratio > 0.5 and the auxil-iary switch is activated twice in a switching cycle as shownin Fig. 2, and (ii) Type-B control: the main switches’ duty ra-tio < 0.5 and the auxiliary switch PWM signal contains fourpulses as shown in Fig. 4.

Firstly, the principle of operation of the proposedZVZCDBC is analyzed for Type-A control and later, a briefanalysis of Type-B operation is given. The analysis estab-lished in this paper is based on the following assumptions:(i) the non-ideal voltage drops of the devices are neglected,(ii) all the passive components, junction capacitances are as-sumed to be linear time-invariant, (iii) resonating tank fre-quency is higher than the converter switching frequency, and(iv) the current in the main inductors is almost constant withvery low ripple content.B. Type-A control of the ZVZCDBC

Figure 2 shows the key steady-state operating waveformsof the ZVZCDBC. The gating sequence adopted for the mainas well as for the auxiliary switches is also depicted in it. Inorder to reduce the ripple content in the input current, the twomain switches are driven in an interleaved fashion, gating sig-nal of S 1 and S 2 phase shifted by 180◦. It can be noted thatthe auxiliary switch is turned-ON before the turn-ON of thefirst main switch and the gating pulse of the auxiliary switchis extended till the turn-OFF of the other main switch. Theproposed ZVZCDBC exhibits fourteen modes of operationin one switching cycle. Among these fourteen modes, thefirst seven modes of operation are identical to the subsequentseven modes and hence, the corresponding equivalent cir-cuits of the first seven modes are only shown in Figs. 3(a) to3(g). With the help of these circuits and key waveforms, theZVZCT performance of the charge-pump based boost con-verter is explained in the upcoming paragraphs.Mode-1 (t0–t1): Before the commencement of mode-1, theswitch S 1 is in the ON-state and the input dc-source is charg-ing the inductor L1 while the inductor L2 charges the up-stream charge-pump capacitor C1. This mode begins as soonas the auxiliary switch S a turns-ON and its equivalent circuitis shown in Fig. 3(a). At the beginning, the resonating in-ductor current iLr is zero while the voltage across Lr is Vc1

and hence the current through it increases linearly, which is

367 IEEJ Journal IA, Vol.9, No.4, 2020


(a) Waveform diagram for mode-1 to 7

(b) Enlarged view of mode-1 to 4

Fig. 2. Key steady-state waveforms of the ZVZCDBC(D>0.5)

defined by Eq. (1).

iLr(t) = Vc1(t − t0)/Lr · · · · · · · · · · · · · · · · · · · · · · · · · · · · (1)

Based on the KCL at the switch node of S 2, the inductorcurrent iL2(t) is given as,

iL2(t) = iD2(t) + iLr(t) · · · · · · · · · · · · · · · · · · · · · · · · · · · · (2)

(a) Mode-1 (t0–t1) (b) Mode-2 (t1–t2)

(c) Mode-3 (t2–t3) (d) Mode-4 (t3–t4)

(e) Mode-5 (t4–t5) (f) Mode-6 (t5–t6)

(g) Mode-7 (t6–t7)

Fig. 3. Equivalent circuits for operating modes of theZVZCDBC (D > 0.5)

From Eqs. (1) and (2) it can be seen that the current throughthe diode D2 decreases linearly and reaches to zero. At thistime instant t = t1, the diode D2 turns-OFF at zero-currentswitching (ZCS). The final conditions are:

iD2(t1) = 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (3a)

iLr(t1) = iL2(t1) · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (3b)

iLr(t)|t=t1 =Vc1

Lr(t1 − t0) = IL2 · · · · · · · · · · · · · · · · · · (3c)

Upon solving the above equation, the duration of mode-1 isobtained as:

t01 = (IL2Lr/Vc1) · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (3d)

Mode-2 (t1–t2): Mode-2 begins with the soft turn-OFF of D2

while S 1 continues to be in the ON-state like in mode-1. Inthis mode, there are two loops: one is formed by Lr-Cdr1-S a-Lr and the other is formed by Lr-Cs2-S a-Lr. Upon solution ofthese circuits, the following expressions for iCDr1(t), iCS 2(t),iS 1(t), iLr(t), and vS 2(t) are, given by Eqs. (4)–(8), obtained.

iCDr1(t) =

(Vc1

Zr

)CDr1

(CDr1 +CS 2)sinωr(t − t1) · · · · · · (4)

iCS 2(t) =

[Vc1

Zr

]CS 2

CDr1 +CS 2sinωr(t − t1) · · · · · · · · · (5)

iS 1(t1) = iL1(t) − iCDr1(t)



= IL1−(Vc1

Zr

)CDr1

(CDr1+CS 2)sinωr(t−t1) · · · · (6)

iLr(t) = IL2 + iCDr1(t) + iCS 2(t)

= IL2 +

(Vc1

Zr

)sinωr(t − t1) · · · · · · · · · · · · · · · · (7)

vS 2(t) = vCDr1(t) = Vc1 cosωr(t − t1) · · · · · · · · · · · · · (8)

where, ωr = 1/√

Lr(CDr1 + CS 2, and Zr =√Lr/(CDr1 +CS 2). The current though Lr starts varying si-

nusoidally from its initial value (IL2) and the voltage acrossthe switch S 2, vs2, co-sinusoidally decreases (Eq. (8)) and atthe end it reaches to zero. Thus, its body diode starts con-ducting the current which was initially flowing through thecapacitance CS 2. As vs2 is zero, at this time instant, the cur-rent through the resonating inductor Lr attains its maximumvalue. At the end of this mode, various elements’ voltagesand currents are given in Eq. (9).

VS 2=0,VDr1=0,VD1=VC1,VD2=VC1, ILrpk= IL2+(Vc1/Zr)

· · · · · · · · · · · · · · · · · · · · · · · · · (9)

From Eq. (6) it is seen that switch S 1 current, iS 1(t), de-creases in this mode. If the current iCDr1, given by Eq. (4),is larger in magnitude than inductor current IL1, then a nega-tive current flows in the switch S 1 and also creates favorableZCT conditions for it. Hence, the necessary condition to havenegative current in switch S 1 is

iCDr1|peak > IL1(Vc1

Zr

)CDr1

(CDr1 + CS 2)> IL1.

· · · · · · · · · · · · · · · · · · · · · · (10)

The time duration of this mode is given by Eq. (11)

t12 =π√

Lr(CDr1 +CS 2)2

· · · · · · · · · · · · · · · · · · · · · · · (11)

Mode-3 (t2–t3): The commencement of this mode is de-cided by the conduction of the body diode DS 2 as explainedabove. Since, the switch S 2 voltage is already brought tozero; it is ready to undergo ZVT at any time in this mode.The non-idealities of the devices also play a role in the cir-cuit operation. In this study, the following non-idealities areconsidered, which are: (i) forward voltage drop of diodesDr1 and Dr2 i.e. VFDr1 and VFDr2, (ii) drain to source on-state resistances of switches S 1, S 2 and S a i.e. RDS (on)S 1,RDS (on)S 2, RDS(on)Sa respectively and (iii) body diode volt-age drop, VSDS1, VSDS2 and VSDSa. Considering the non-idealbehavior of the devices, the voltage and current expressionsfrom Fig. 3(c) circuit are obtained and listed in Eq. (12). Thecurrent iLr(t) is given by Eq. (12a) whereas Eq. (12b) givesthe switch current iS 1(t) and iS 2(t).

iLr(t) =[ILrpke

−(t−t2)τ − ILrdrop

(1 − e−

(t−t2)τ

)]· · · · · (12a)

where,

ILrdrop =

(VSDS2 + VFDr2

RDS (on) S a

)and τ =

(Lr

RDS (on) S a

)

is1(t) = is2(t) = (iLr(t − t2) − ig)/2 · · · · · · · · · · · · · (12b)

The time interval of this mode is given by Eq. (13).

t23 = (Ta1 − t01 − t12) · · · · · · · · · · · · · · · · · · · · · · · · · · · (13)

Mode-4 (t3–t4): Mode-4 starts as soon as the switch S 2 isgiven a gate pulse which turns it to the ON-state at ZVT. Theconducting devices are: S 2, S a, Dr1 and Dr2. Also, the res-onating inductor carries a current more than the input cur-rent, and thus the main switches carry the negative current.However, the auxiliary switch continues to conduct until theswitch S 1 turns-OFF at zero-current. Further, a finite time de-lay between the turn-OFF of the auxiliary and main switchesis necessary for satisfactory ZCT of the main switches. How-ever, the use of excessive time delay must be avoided to limitthe conduction losses in the auxiliary switch. Since there isno change in the circuit configuration, the current and volt-age expressions obtained in mode-3 are also applicable in thismode. The time duration of this mode is given in Eq. (14).

t34 = (D − 0.5)T · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (14)

By substituting the time durations defined by Eqs. (13) and(14) in Eq. (12a), the resonating inductor current iLr(t) = ILr4

at the end of this mode can easily be computed.Mode-5 (t4–t5): At the end of mode-4, the main switch S 1

turns-OFF at zero-current and it is in the OFF-state even inthis mode. Soon after turn-OFF of S 1, the auxiliary switchS a turns-OFF. In this mode, as shown in Fig. 3(e), the energytransfer takes place from the resonating inductor Lr to thecapacitor CS a. The vCS a(t) and iLr(t) variation is defined byEq. (15). The capacitor Csa attains its maximum, peak volt-age stress of the auxiliary switch, at the end of this mode andit is obtained from Eq. (15b), given in Eq. (15c). Since theproposed soft-switching network is free from clamp/energyrecovery diode (10), the peak value of the auxiliary switch volt-age should not exceed the load voltage, i.e. vCS a,pk < Vo.However, if the design parameters of the transition networkare chosen such that vCS a,pk > Vo, then a clamp diode con-nection is essential to keep the voltage stress on the auxiliaryswitch within permissible limits.

iLr(t) = ILr4 cosωa(t − t3) · · · · · · · · · · · · · · · · · · · · · (15a)

vCS a(t) = ILr4Za sinωa(t − t3) · · · · · · · · · · · · · · · · · · (15b)

vCS a peak = ILr4Za · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (15c)

where ωa = 1/√

LrCS a, and Za =√

Lr/CS a. The duration forthis mode is obtained as

t45 =

[π√

LrCS a

2

]· · · · · · · · · · · · · · · · · · · · · · · · · · · · · (15d)

Mode-6 (t5–t6): This mode begins as soon as the auxiliarydiode Dr2 turns-OFF. The capacitors, CDr2 and CS 1, startcharging and finally attain a voltage Vc1. The charging cur-rents iCDr2(t) and iCS 1(t) in this mode are given by Eqs. (16a)and (16b), respectively. The peak current of switch S 2, whichis the summation of iCDr2(t) and iL2(t), increases due to thecharging of capacitor CDr2.

iCDr2(t) =

(CDr2

CDr2 +CS 1

)iL1(t − t5) · · · · · · · · · · · · · (16a)

iCS 1(t) =

(CS 1

CDr2 +CS 1

)iL1(t − t5) · · · · · · · · · · · · · · (16b)

iS 2(t) = iCDr2(t) + iL2(t) · · · · · · · · · · · · · · · · · · · · · · · (16c)

Once the voltage across the capacitors CDr2 and CS 1 attains



a value same as the charge-pump capacitor voltage Vc1, thediode D1 becomes forward biased to mark the end of thismode. Mathematically, this is identical to

vCDr2(t6) = vCS 1(t6) = Vc1. · · · · · · · · · · · · · · · · · · · · · · (17)

The time duration of this mode is given by Eq. (18).

t56 = Vc1(CDr2 + CS 1)/IL1 · · · · · · · · · · · · · · · · · · · · · · (18)

Mode-7 (t6–t7): Mode-7 commences when the main diodeD1 is forward biased like in hard-switched converter. Thetime duration of this mode is given by Eq. (19).

t67 = [(1 − D)Ts − Ta1 − t45 − t56] · · · · · · · · · · · · · · · (19)

C. Steady-state Analysis of the ConverterThe voltage gain of the hard switched converter for duty

cycles greater than 0.5 is given by the Eq. (20).

V0

Vg=

2(1 − D)

· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·(20)

Figure 2 depicts that the effective charging time of the induc-tors L1 and L2 is slightly higher than the hard-switched coun-terpart. The effective duty ratio Deff mainly depends uponthe time duration for which the auxiliary switch is in the ON-state. This time duration should be judiciously chosen in or-der to have satisfactory soft-switching performance togetherwith minimum circulating losses in the ZVZCT network. Thevoltage gain is expressed as in Eq. (21).

V0

Vg=

2(1 − Deff )

· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·(21)

D. Device StressesIn order to select the power MOSFETs and diodes, the volt-

age and current stress of the devices need to be computed wellin advance. From steady-state analysis for D > 0.5,

VS 1max = VS 2max = Vc1 = [V0/2] · · · · · · · · · · · · · · · · (22)

From Eq. (22), it is clear that the voltage stress of S 1 and S 2

equals the voltage across the charge pump capacitor C1 whichis half of the load voltage. Hence, the addition of the chargepump capacitor reduces the voltage stress on the switches S 1

and S 2. The voltage stress of the main diodes D1 and D2 isgiven in Eq. (23). It indicates that the voltage rating of themain diode D2 should be twice that of the main diode D1.

VD1max = Vc1 = (V0/2)VD2max = V0

· · · · · · · · · · · · · · · · · · · · · · · · · (23)

The peak current rating of the power switches and diodes aregiven in Eqs. (24) and (25), respectively.

IS1max = Igmax · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (24a)

IS2max = Igmax · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (24b)

ID1max = IL1max · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (25a)

ID2max = IL2max · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (25b)

E. Type-B Control of the Proposed ConverterIn Type-B control for D < 0.5, as shown in Fig. 4, there is

no overlap between the interleaved gating signals of the mainswitches S 1 and S 2 and hence there are twenty eight modes in

Fig. 4. Type-B operation: Waveforms of the ZVZCDBC(D < 0.5)

one switching cycle, of which first fourteen are symmetricalto the subsequent fourteen modes. In mode-1, the resonatinginductor current linearly increases up to a maximum value ofIL2 and at that instant, the current iD2(t) becomes zero. Inmode-2 operation, resonance occur in the loops formed byLr-S a-CS 2 and Lr-S a-CDr1, and its operation is identical asin mode-2 of Type-A control. The body diode of S 2 startsconducting in mode-3 duration while the channel of S 1 car-ries a negative current. The gating signal of S 1 is removedso that it turns-OFF at zero-current. In mode-4, soon afterthe turn-OFF of the switch S 1, the auxiliary switch S a isturned-OFF. Also, the energy stored in Lr is transferred tothe parasitic capacitance of the switch CS a. Mode-5 persistsfor a very short duration wherein the parasitic capacitances ofthe switches and diodes are charged and discharged, respec-tively. A similar trend of charging and discharging is alsoseen in mode-6 except that the main diode D1 turns-OFF. Inmode-7, the diode D2 turns-ON by the virtue of the circuitstructure. This is the conventional mode of the charge-pumpbased interleaved boost converter where both the switches arein the OFF-state. The inductors L1 and L2 delivers power tothe load. The auxiliary switch S a is turned-ON to initiate theZVT turn-ON of the switch S 2. The subsequent seven modesof operation can easily be analyzed along similar lines as ex-plained in Type- A control.

3. Design Considerations

A detailed description for designing the components of the



ZVZCDBC is discussed in this section. The design proce-dure is given for a load voltage of 420 V, with power rating of460 W. The source voltage range is 60–90 V and the adoptedswitching frequency is 50 kHz. Assuming the ZVZCDBCefficiency close to 94%, the input current drawn by the con-verter is Igmax = Po/ηVgmin = 460/(0.94 × 60) ≈ 8.2 A.With the assumption of load shared between the two inter-leaved cells, the average inductor currents IL1 and IL2 is:IL1,max = IL2,max = Ig,max/2 = 4.1 A. The approximate valueof the load current is: I0 = (Po/V0) = (460/420) = 1.09 A.For Vg = 60 V and Vo = 420 V, the computed duty ratio isDmax =

(1 − 2 Vgmin/Vo

)= (1 − 2 × 60/420) = 0.71.

A. Design of the Converter ComponentsCapacitance: The charge pump capacitor C1 and and the out-put capacitor C2 is designed by considering the ripple voltageless than 5% of their respective average voltages.

C1≥ IL1max(1−Dmin)fsΔVC1

=4.4 × (1−0.5)

50 × 103 × 0.05 × 210=4.2 μF

· · · · · · · · · · · · · · · · · · (26a)

C2 ≥ I0maxDmax

fsΔVC2=

1.07 × 0.7150 × 103 × 0.05 × 420

= 0.72 μF

· · · · · · · · · · · · · · · · · · (26b)

Inductances: The inductors L1 and L2 are designed here byconsidering the source ripple content to be less than 20% ofthe average source current i.e. ΔiL1 = ΔiL2 = 20% of Igmax

ΔiL1 = 0.2 × 8.2 = 1.64 A

L1 = L2 ≥ VgmaxDmax

fsΔiL1=

90 × 0.7150 × 103 × 1.64

= 780 μH

· · · · · · · · · · · · · · · · · · (27a)

Sendust toroid cores (27) (Hujia Part No: HJS157060, perme-ability = 60 μoH/m and AL = 81 nH/turns2) are used for theinductors L1 and L2. From the permeability -vs- DC biascurve of this core, the permeability rolls off by 70% at a DCcurrent (peak inductor current) of 4.8 A. Therefore, the effec-tive AL is: 0.70 × 81 nH/turns2 ≈ 56.7 nH/turns2. Hence, thenumber of turns required on the core is:

N =

√1000L

AL=

√1000 × 780

56.7≈ 118 · · · · · · · · (27b)

Design of Resonating Components: To have controlled‘di/dt’ in the main diodes D1 and D2 during turn-OFF, thetime duration of mode-1 (D > 0.5) should be greater than thediodes reverse recovery time i.e. t01 > trr. Using Eq. (28) thefollowing design equation is obtained.

Lr >

(2trrVc1

Igmin

)· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (28)

From Eq. (28), the peak voltage stress of diodes D1 and D2

are close to Vo/2 and Vo respectively. Taking into account theabove considerations, a 600 V diode (DSEP8-06B) is cho-sen. Using Eq. (28), the resonating inductance is computedas: Lr > (2×25×10−9×210)/1.8 = 5.8 μH. A Kool Mμ toroidcore (27) (Magnetics part No: 77314, AL = 90 nH/turns2) with8 turns gave an inductance Lr of 5.8 μH. The Eq. (10) revealsthe necessary and sufficient condition for ZVT and ZCT ofmain switches S 1 and S 2. Accordingly, the capacitors CDr1

and CDr2 are designed based on Eq. (10) of mode-2 and cor-responding expressions are given in Eq. (29).

iLrpk > ig

CDr1,CDr2 >

⎡⎢⎢⎢⎢⎢⎣(iL1,max

Vc1

)2

Lr − CS 1

⎤⎥⎥⎥⎥⎥⎦CDr1,CDr2>

⎡⎢⎢⎢⎢⎢⎣(

4.4210

)2

×5.8×10−6−0.72×10−9

⎤⎥⎥⎥⎥⎥⎦=1.82 nF.

· · · · · · · · · · · · · · · · · · · (29)

The design selection based on Eq. (29) should ensure nega-tive currents in the switches S 1 and S 2 for the entire dura-tion of mode-3 and 4. This means that the value of 1.82 nFfor CDr1 & CDr2 would be adequate to create the conditionof negative current but not sufficient enough to maintain thenegative current until its turn-OFF due to the non-idealitiesof the circuit as mentioned in Mode-3 (D > 0.5). By substi-tuting t = (t23 + t34), iLr(t) = Ig and the other parameters inthe inductor current iLr(t) expression of mode-3, defined byEq. 12(a), the capacitors CDr1 & CDr2 are computed ( (28):Coss of 720 pF (CS 1); RDS(on) = 0.4Ω, VSD = 0.8 V).B. Turn-ON time of the Auxiliary switch Sa

For satisfactory ZVT of the main switches, the pulse widthTa of the auxiliary switch is computed from the followingcondition.

Ta = (Ta1 + Ta2); Da = [2Ta/Ts] · · · · · · · · · · · · · · (30a)

Ta1 >

[IL2Lr

Vc1+π√

Lr(CDr1 + CS 2)2

]· · · · · · · · · · · (30b)

Using the design mentioned above along with Eq. (30) theturn-ON time (Ta) of the auxiliary switch is obtained as:

Ta1 > 0.433 μs · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (31a)

Ta2= (D−0.5)Ts= (0.71−0.5) × 20 × 10−6=4.2 μs

· · · · · · · · · · · · · · · · · · (31b)

Ta > (0.43 + 4.2) μs = 4.63 μs · · · · · · · · · · · · · · · · · (31c)

4. Results and Discussions

To demonstrate the soft-switching performance and tovalidate the theoretical analysis, a prototype (Fig. 5) hasbeen built with the design specifications (detailed design ofZVZCDBC is given in Section 3) mentioned in Table 1. Fig-ure 6 shows experimental waveforms of the soft-switched

Fig. 5. Experimental prototype circuit of the ZVZCDBC(TM1 and TM2 are temperature sensors of S1 and S2 respec-tively)



(a) Inductor currents iL1, iL2 (b) Source current ig and load voltage Vo

(c) Switch S1 voltage and current waveforms indicating ZVT andZCT turn-ON and ZCT turn-OFF

(d) Switch S2 voltage and current waveforms indicating ZVT turn-ON and ZCT turn-OFF

(e) Diode D1 voltage and current waveforms indicating ZVS turn-ON and ZCS turn-OFF

(f) Diode D2 voltage and current waveforms indicating ZVS turn-ON and ZCS turn-OFF

(g) Auxiliary switch Sa waveforms depicting its ZCS turn-ON

Fig. 6. Measured waveforms of the soft-switched converter at full load conditions (Vg = 90 V, Vo = 420 V, Po = 460 W)

converter corresponding to rated conditions (Vg = 90 V, Po

= 460 W). For the gating scheme indicated in Fig. 2, thesteady-state waveforms of inductor L1 and L2 currents andload voltage is depicted in Fig. 6(a). Here, it is seen that theindividual boost cell inductors are carrying almost identical

currents. Figure 6(b) shows the load voltage and source cur-rent of the ZVZCDBC. At these conditions, the measuredload voltage is 420 V whereas the current drawn from thedc-source is close to 5.53 A. Since this converter employs aninput filter, the source current ripple is very less and at the



Table 1. Converter Parameters

rated condition, the measured ripple content is close to 10%.Figures 6(c) and 6(d) shows the measured waveforms of

the ZVZCDBC for the rated conditions indicating the soft-transitions of the main switching devices S 1 and S 2. Hereit is seen that the switches S 1 and S 2 undergo ZVT turn-ON and ZCT turn-OFF transitions. Also, the voltage stress(vs1, vs2) of the main switches S 1 and S 2 are half that of theload voltage v0. The measured ZVZCT and ZVZCS wave-forms of the switch-diode pairs [(S 1, D1), (S 2, D2)] is shownin Fig. 6(e) and 6(f). The resonating inductor Lr is able to en-sure ZCS turn-OFF of the main diodes D1 and D2. Also, thecapacitors CDr1 and CDr2 facilitate ZVS turn-ON of the maindiodes D1 and D2 as depicted in Fig. 6(e) and 6(f). The zero-current turn-ON of the auxiliary switch S a is demonstratedin Fig. 6(g). This measurement indicates that the resonat-ing inductor current or the auxiliary switch current iS a is de-creasing (with a decay rate in close agreement with Eq. (12a))with time. To demonstrate the efficacy of the proposed aux-iliary transition network effectiveness at light loads, samplemeasurement waveforms of switch S 1 and S 2 depicting soft-transitions (Vg = 90 V, Vo = 420 V, Po = 250 W) is shownin Figs. 7(a) and 7(b). In all these test cases, ZVT turn-ONand ZCT turn-OFF of the switches S 1 and S 2 is demon-strated and thus, the proposed ZCZVT network guaranteessoft-transitions over a wide range of loads. The efficiencyvariation with load power for the hard-switched and soft-switched converter is shown in Fig. 8. The soft-switched con-verter ensures higher efficiency than the hard-switched con-verter for most of the loads (load power more than 130 W).Since, the resonating elements (Lr, CDr1, CDr2) are designedto satisfy soft-switching conditions for maximum load con-ditions, at lighter loads the losses are more due to highercirculating current loss and thus a fall in efficiency is seen.However in comparison to the hard-switched converter, animprovement in efficiency of nearly 2 ∼ 4% is seen in thesoft-switched converter for heavier loads.

In order to measure the impact of transition losses inthe main switching devices S 1 and S 2, both soft and hard-switched converters, their heat-sinks temperature-rise is mea-sured when the converter is supplying identical load power.The Yokogawa TX1002 digital thermometers are used for

(a) Switch S1 voltage and current waveforms indicating ZVT and ZCTturn-ON and ZCT turn-OFF

(b) Switch S2 voltage and current waveforms indicating ZVT turn-ONand ZCT turn-OFF

Fig. 7. Measured waveforms of the soft-switched con-verter at light load conditions (Vg = 90 V, Vo = 420 V, Po

= 250 W)

Fig. 8. Efficiency variation with output power (Vg =90 V)

recording the temperatures of the heat-sinks connected to theswitches S 1 and S 2 and are shown in Fig. 5. Since the rmsvalue of the current carried by the switch S 1 is higher thanthat of switch S 2, in both soft and hard-switched converters,a higher steady-state temperature is observed in the heat-sinkconnected to the switch S 1 than the heat-sink of the switchS 2. Under soft-switching conditions (Fig. 9: blue plot), therecorded value of the steady-state temperature of the heat-sinks of the switches S 1 and S 2 is 43◦C and 96◦C while therespective values for the hard-switched converter (Fig. 9: redplot), is 50◦C and 130◦C. The heat-sink temperature of thehard-switched converter is high mainly due to the transitionpower loss occurring in the main switches.

5. Conclusions

In this paper, the soft-switching performance of a charge-pump based boost converter with a modified zero-voltagezero-current transition networks was analyzed. An analyt-ical study was performed and then a design example wasillustrated. The established design was verified through



(a) Switch S1 heat-sink temperature (TS1)

(b) Switch S2 heat-sink temperature (TS2)

Fig. 9. Temperature profile of the switches S1 and S2 forthe hard-switched converter and the soft-switched con-verter (Vg = 90 V, Vo =420 V, Po =460 W)

experimental studies. It was demonstrated that a single auxil-iary network guarantees ZVT turn-ON and ZCT-turn-OFF ofthe main switches which are located in different boost cellsof the interleaved converter. The transition loss reduction ob-tained through the proposed ZVZCT network was demon-strated through the temperature measurements of heat-sinksassociated with the switching devices. The ZVZCDBC pro-totype circuit measurements demonstrated a 2∼4% efficiencyimprovement over the hard-switched converter. Furthermore,the proposed transition network resulted in soft-transitionsover a wide range of loads at a fixed frequency of operation.

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Mummadi Veerachary (Non-member) was born in Survail, India,in 1968. He received the Dr.Eng. degree in electri-cal engineering from the University of the Ryukyus,Nakagami, Okinawa, Japan, in 2002. Since July2002, he has been with the Department of ElectricalEngineering, Indian Institute of Technology Delhi,New Delhi, India, where he is currently a Profes-sor. His fields of interest are power electronics andapplications, design of power supplies, multi-inputand modular multilevel converters for dc-grid, con-

trol theory application, and digital and intelligent control solutions for powersupplies. Prof. Veerachary served as a Guest Editor of the IEEE TRANSAC-TIONS ON INDUSTRIAL ELECTRONICS, for Special Sections on Photo-voltaic Power Processing Systems and Efficient and Reliable PhotovoltaicSystems. He also served as a Guest Co-Editor of the IEEE TRANSACTIONSON POWER ELECTRONICS for a Special Section on Power Electronicsin Photovoltaic Applications. He is currently serving as a Technical Editorfor the IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYS-TEMS.

Jyoti Prakash (Non-member) was born in Daltonganj, Jharkhand, In-dia in 1991. She received the B.Tech degree in Elec-trical and Electronics Engineering from Vellore In-stitute of Technology, Vellore, India in 2012 and theM.Tech degree in power electronics from Indian In-stitute of Technology, BHU, Varanasi, India in 2015.She has served as Assistant Electrical Engineer inBihar State Power Holding Company Ltd. from Jan.2014 to Jan. 2015. She is currently working towardsthe Ph.D. degree at the Department of Electrical Engi-

neering in Indian Institute of Technology Delhi, New Delhi, India. Her cur-rent research interests include switched-mode power conversion, interleaveddc-dc power conversion, soft-switching and high step-up dc-dc converters.


Documents

Zero-voltage Zero-current Switching Scheme for Charge-pump