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ECEn 224 © 2003-2008BYU
Handling Asynchronous Inputs
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ECEn 224 © 2003-2008BYU
Asynchronous Signals
• Definition: A signal that can change at any time with respect to the clock.
• Examples:– Push buttons– Keystrokes– Digital signals from different clock domain
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ECEn 224 © 2003-2008BYU
Two Problems with Asynchronous Inputs
1. Flip flops could become metastable
2. State machines may transition to incorrect next state
These are two independent problems.
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ECEn 224 © 2003-2008BYU
Problem #1
Metastability
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ECEn 224 © 2003-2008BYU
Asynchronous Signals
• Problem: Asynchronous signals do not always respect setup and hold times– Asynchronous signals may change at any
time
Clock
tsetupthold
ok ok ok okbad bad
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Metastability
S=0
R=0Q=1
Q’=0
• Imagine if R is pulsed high for a very short time then goes back low…– Could it impart just enough energy to get Q halfway
between ‘1’ and ‘0’?– Latch might hang at the midway point for some time
• Could be a short time, could be a long time
– This is called metastability
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Metastability
• Violating tsetup for a D flip flop can cause very short pulses on signals Y and Z, and make flip flop metastable
D
CLK
Q
Q’
Y
Z
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Metastability
• Once a flip flop goes metastable, it is impossible to bound how long it will remain there
Analogy: Roll ball up roof just hard enough to get it to balance on top…
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ECEn 224 © 2003-2008BYU
Metastability
• Once a flip flop goes metastable, it is impossible to bound how long it will remain there
Analogy: Roll ball up roof just hard enough to get it to balance on top…
When will it come down?
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ECEn 224 © 2003-2008BYU
Probability of Metastability
• The probability of an asynchronous signal causing metastability in a given clock cycle is very low
• However, there are millions or even billions of clock cycles every second
• Mean Time Between Failure (MTBF) quantifies how often a flip flop with an asynchronous input is likely to go metastable
• MTBF depends on:– Flip flop’s clock frequency– Frequency of changes on the asynchronous input– Electrical characteristics of the flop flop
• Typical MTBF numbers can range from minutes for high frequency systems to thousands of years for slower devices
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Metastability Solutions
• Solution #1: Specially-designed flip flops that are particularly resistant (hardened )
• Solution #2: Multiple FF’s in series increases resistance to metastability– At the expense of response time
D Q D QAsynchronousIn SynchronizedOut
Could also be hardened flip flops
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ECEn 224 © 2003-2008BYU
Problem #2
May Lead to Wrong Next State
(No metastability involved here…)
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Wrong Next State
• Asynchronous inputs might cause the wrong next state to be loaded
• Two possible causes:– Unequal logic path lengths (Cause A)– False outputs on IFL outputs (Cause B)
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D Q
D Q
IFL
A
11
A
A’
00
N0
N1
C0
C1
5ns
10ns
clk
clk
Cause A: Unequal Path Lengths
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ECEn 224 © 2003-2008BYU
D Q
D Q
IFL
A=0
11
A
A’
00
N0=0
N1=0
Q0=0
Q1=0
5ns
10ns
clk
clkTime t = 12 ns
Cause A: Unequal Path Lengths
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Cause A: Unequal Path Lengths
D Q
D Q
IFL
A1
11
A
A’
005ns
10ns
Time t = 13 ns
N0=0
N1=0
Q0=0
Q1=0
clk
clk
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ECEn 224 © 2003-2008BYU
Cause A: Unequal Path Lengths
D Q
D Q
IFL
A1
11
A
A’
005ns
10ns
Time t = 18 ns
N0=0
N11
Q0=0
Q1=0
clk
clk
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ECEn 224 © 2003-2008BYU
Cause A: Unequal Path Lengths
D Q
D Q
IFL
A1
11
A
A’
005ns
10ns
Time t = 20 ns (clock rises)
N0=0
N11
Q0=0
Q11
clk
clk
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ECEn 224 © 2003-2008BYU
CLK
CurrentState
00 10
A
N1
N0
5ns
10ns
Wrong next state!!
Erroneous State Transition
11
A
A’
00
0 5 10 25 30
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ECEn 224 © 2003-2008BYU
CLK
CurrentState
00 10
A
N1
N0
5ns
10ns
Erroneous State Transition
11
A
A’
00
0 5 10 25 30
Dangerperiod
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Solution #1: Synchronize Signal A
D Q
D Q
IFL
A
N0
N1
C0
C1
5ns
10ns
clk
clk
D Q
clk
IFL now sees synchronous
input
Synchronizing flip flop is still susceptible tometastability due to setup time violations.
But that is a different problem with previously-seen solutions.
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Solution #2: Use Gray Codes for States
D Q
D Q
IFL
A
11
A
A’
00
N0
N1
C0
C1
5ns
10ns
clk
clk
11
A
A’
01
Will never have casewhen both pathstransitioning…
State change will occur or it won’t…
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Cause B: False Outputs
• Gray coding state transitions doesn’t always work!
• We can still have false outputs on our input forming logic
• These hazards can also lead to incorrect transitions
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F = A’B + AC
F
A’B
AC
Logic Hazards
This is the conventional K-map solution
A
BC 0 1
00 0 0
01 0 1
11 1 1
10 1 0
Asynchronous input A
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ECEn 224 © 2003-2008BYU
Gates Have Real Timing…
A
g1
g2
F
Called a false output
F
A’B=1
AC=1
g1
g2
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ECEn 224 © 2003-2008BYU
Gates Have Real Timing…
A
g1
g2
F
If the clock edge occurs here… you’re toast!
F
A’B=1
AC=1
g1
g2
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A
BC 0 1
00 0 0
01 0 1
11 1 1
10 1 0
Hazard-Free Logic Design
• Make sure all adjacent 1’s are covered by the same prime implicant– Add redundant prime implicants as needed
Redundant butwill eliminatefalse output
F
A’B
AC
BC
g1
g2
g3
On ABC = ‘111’ to ABC = ‘011’, g3 will hold F high entire time.
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No False Output…
A
g1
g2
g3
F
F
A’B=1
AC=1
B=1C=1
g1
g2
g3
A
BC 0 1
00 0 0
01 0 1
11 1 1
10 1 0
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Solution #3• Use both gray code states and hazard-free logic minimization
– Gray code encoding ensure only one state bit changes• Solves the unequal path problem
– HFLM ensures no hazards (false outputs) exist on input forming logic
11
S
01
S’
D Q
D Q
IFL
A
N0
N1
C0
C1
5ns
10ns
clk
clk
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Asynchronous Input Problem Summary
• Problem #1: Asynchronous inputs can cause flip flops to enter a metastable state
• Problem #2: Asynchronous inputs can cause invalid state transitionsA) Different propagation delays on IFL paths
to different state bitsB) False outputs on IFL outputs
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Solutions Summary
• Metastability– Solution #1: Use hardened flip flops
• May not be available– Solution #2: Add flip flops in series to decrease susceptibility
• Latency may cause problems, if we need to react immediately
• Invalid State Transitions– Solution #1: Synchronize asynchronous inputs with a flip flop
• Simplest solution• Latency may cause problems, if we need to react immediately
– Solution #2: gray code state encoding (doesn’t always work)– Solution #3: gray code + hazard-free IFL
• Takes extra hardware• May require additional states to get gray code transitions• Use when need to react quickly to input• FF’s still susceptible to metastability• HFLM only works for single-input changes
The samesolution!
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Other Asynchronous Input Issues
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Multiple Asynchronous Inputs
• What if we have a state transition that depends on multiple asynchronous inputs?
S1
A’•B
A’•B’
S0
S2
A
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Multiple Asynchronous Inputs
• Break up the states so that only one transition is dependant on each input
S1
A’
S0
S2A
S3
B
S1
A’•B
A’•B’
S0
S2
A
B’
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Multiple Clock Systems
• When you make up the rules– You can cheat…
• In this class we cheat:– One global clock simplifies our work
• In the real world:– Systems have multiple clocks
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Multi-clock System
• This is a PCI Express board that plugs into a computer’s motherboard
RAM (DDR SDRAM)
FPGA
PCI-E Interface (PHY)
Video DAC
PCI-E Connector
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Multi-clock System
• This is a PCI Express board that plugs into a computer’s motherboard
100 MHz
200 MHz
25.175 MHz
250 MHz
2.5 GHz
How do they talk to each
other?
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Multi-Clock Systems
• This system has multiple clock domains• Signals that cross domains look like
asynchronous signals to the other domain
• For simple control signals, we can use one of the methods discussed in this lecture– Synchronizing flip flops– Hazard free logic + gray codes
• When data transfer is involved, the required solutions are more complicated (ECEn 320)