1. 1)FortheMIPScodebelow,whatisthecorrespondingCcode?

Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, 1 j Loop Exit: 2. Whatarethetwofallaciesandsinglepitfallofpipelining?

Pipeliningiseasy.Pipeliningideascanbeimplementedindependentoftechnology.Failuretoconsiderinstructionsetdesigncanadverselyimpactpipelining.

3. Forthecodesequencebelow,indicatewhetheritmuststall,canavoidstallsusingonlyforwarding,orcanexecutewithoutstallingorforwarding:

addi $t1, $t0, 1 addi $t2, $t0, 2 addi $t3, $t0, 2 addi $t3, $t0, 4 addi $t5, $t0, 5 4. ThefollowingMIPScodecancausewhattypeofhazard?

add $s0, $t0, $t1 sub $t2, $s0, $t3 5. Anewprocessorcanuseeitherawrite‐throughorwrite‐backcacheselectable

throughsoftware.Assumetheprocessorwillrundataintensiveapplicationswithalargenumberofloadandstoreoperations.Whichcachewritepolicyshouldbeused?

6. Listthe4principlesofhardwaredesign.• Simplicityfavorsregularity• Smallerisfaster• Makethecommoncasefast• Gooddesigndemandscompromise

7. Explainwhatismeantbyoverflowandunderflow.• Overflowoccurswhenanoperationresultsinanumberthatistoobigtobe

representedintheavailablestoragespace.• Underflowoccurswhenanoperationresultsinanumberthatistoosmalltobe

representedintheavailablestoragespace.Itisbasicallyanegativeoverflow.8. Whatarethe5stagesoftheMIPSpipeline?

• IF:Instructionfetchfrommemory

• ID:Instructiondecodeandregisterread• EX:Executeoperationorcalculateaddress• MEM:Accessmemoryoperand• WB:Writeresultbacktoregister

9. Explaintemporalandspatiallocality.Temporallocality:ifanitemisreferenced,itwilltendtobereferencedagainsoon.Spatiallocality:ifanitemisreferenced,itemswhoseaddressesareclosebywilltendtobereferencedsoon.

10. Connectthehardwaretoimplementthefetchandexecutecycle.

11. The“factory”analogyofacomputerhas6partstoit.Nametheeachofthe6partsofthisanalogyandgivetwoexamplesofeach.

12. Inbinaryarithmetic,therearefoursituationsfromwhichanoverflowcanarise.Listallfoursituations.Listthreepossiblewaystohandleanoverflow.

13. TherearetwocommoncategoriesofISAs.Nameanddescribethembothandlistsomeadvantagesanddisadvantagesofboth

14. TherearefivestageoftheMIPSpipeline.Listthestages,andstatewhichstepistakenateverystage.

15. Listthethreetypesofhazardstalkedaboutinclassandgiveabriefdescriptionofeachone.

16. Whatarespatialandtemporallocalityandhowarethesetakenadvantageofinaprocessor?

17. Howaremissratesandthelevelofmemoryassociationrelatedandwhatkindsoftrade‐offneedtobemade?

18. Whatextrahardwareisneededforapipelinedarchitecture?

19. Whatfactorsimpactthecomplexityofapipelinedarchitecture?20. Whichprocessorisfaster?P1hasaCPIof1.5andaclockrateof2GHz.P3hasaCPI

of2.5andaclockrateof3GHz.21. Listthefivestagesofapipelineddatapathanddefinethem.22. DefinetheLeastRecentlyUsed(LRU)replacementschemeforcachesandexplain

whyitismostcommonlyused.23. Explainwhyhazardsexistwhenpipeliningisusedandhowtheycanbeavoided.24. Whenshoulddynamicbranchpredictionbeusedoverastaticpredictionscheme?25. Definethefollowingterms:latency,throughput,andexecutiontime.26. Nameanddescribethetwodifferenttypesoflocality.27. InacertainCPUimplementation,thenumberofclockcyclestoexecuteseveral

typesofinstructionsisshownbelow.

InstructionType #ofcyclesLoad 10Store 8R‐Type 4Branch 6Jump 5

• Aprogram’sinstructionsaredistributedasshownbelow;calculatetheaverage

CPIoftheprocessor

InstructionType %ofinstructionsLoad 15%Store 25%R‐Type 50%Branch 8%Jump 2%

• Iftheclockspeedis2MHz,howlongwillittakeaprogramof1,000,000instructionstoexecute?

• IftheCPIofstoreinstructionscanbecutinhalf,whatwillbethenewaverageCPI?

28. Explainwhyann‐stagepipelinewillnotcreateann‐foldperformanceincrease.29. Considerthefollowingtwobinarynumbers

A: 01011101 B: 10010010

• FindA+Bandcheckforoverflow;assumingAandBareunsignedintegers.

• FindA‐Bandcheckforoverflow;assumingAandBareintegersrepresentedin2’scomplement

30. Explainthestructureofamemoryhierarchy31. Describethethreemaintypesofhazards(structural,data,andcontrol)andgiveone

possiblesolutionforeach.AssumetheMIPSinstructionsetisused.32. Whatisbranchprediction?Describethetwomaintypesofbranchprediction.33. Identifythehazard(s)inthefollowingMIPScodesegment:

loop: add $t0, $t1, $s1 add $t2, $t0, $s2 beq $t2, $s0, loop sw $t0, 0($s3)

34. Regardingmemory,whatisthedifferencebetweenspatiallocalityandtemporallocality?

35. TrueorFalse:Pipeliningistechnology‐independent.Explain.

36. Assumethatthefollowinginstructionisreadfrominstructionmemory:add$s0,$a1,$t7

Thebinaryequivalentofthisaddinstructionisshownbelow:Instruction[31‐0]:op rs rt rd shamt funct

000000 00101 01111 10000 00000 100000 Providethebinaryvaluesofthefollowinginputandcontrollinesfromsinglecycledatapathdiagramshownbelow.

• Instruction[31‐26]:• Readregister1:• Readregister2:• Writeregister:• RegDst:• ALUSrc:• MemtoReg:• RegWrite:• MemRead:• MemWrite:• Branch:• Jump:• AluOp[1‐0]:

37. Pipeliningisacommontechniqueusedincurrentprocessorarchitectures.ExplainwhyapipelinedimplementationisusedinplaceofasinglecycleCPUmplementation(Hint:howwouldtheclockspeedbedeterminedinasinglecycleCPUimplementation)?Whataresomeofthedifficultiesassociatedwithimplementingapipelinedarchitecture?

38. Fromthesetofinstructionsbelow,showwhatdataneedstobeforwardedby

drawinganynecessaryconnectionsonthepipelinediagramthatfollows.

sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

39. Consideracachewith64blocks,whereeachblockiscomposedof16bytes.Ifwe

assumethatthiscacheisusingdirectmapping,whatblockdoesthememoryatbyteaddress528getmappedto?

40. WhatarethefourdesignprinciplesonwhichtheMIPSISAisbased?41. Listthefourprincipalsofhardwaredesign.42. InresponsetothePowerWall,CPUclockrateshavenotrisenbutfallen,yet

computerperformancehasnot,explainthisphenomenon?43. Trueorfalse,designingapipelinedprocessoriseasy?Explainwhyorwhynot.44. Systemcachecaneitherbeimplementedusingdirectmaporassociative,ideallyone

wouldliketouseafullyassociativeimplementation,whyisthisnotpossible?45. Fillintheblank:

• Thevalidbitimpliesabitis¬____________.(Donotusethewordvalid)• Thedirtybitimpliesalocationhasbeen___________.

46. Whataredatapathandcontrol?47. ConnectthefollowingcircuittoformtheR‐Formatdatapathandcontrol.

48. Whataresomespecificationadvantagestomicro‐codingandimplementation

advantagesanddisadvantages?49. Whatisthedifferencebetweenastructurehazard,datahazardandcontrolhazard?

50. Belowisasnippetofcode.Determinewheretheremightbestallsinapipelinearchitectureandrearrangethelineofcodingtoremovethestallsinthecoding.

51. Whatispipelining?Whataresomepossiblehazardsofpipelining,andwhatare

somesolutionsforthehazard?52. Howdomoderncomputersgetpastthepowerwallproblem?Whydoesitwork?

Arethereanydrawbackstothesolution?53. Whatarethe5stagesofthedatapathdoestheMIPSprocessortakeadvantageof

forpipelining?54. Whatisthememoryheirarchy?Whyisitneeded?Whatarethegeneral

charactersticsofmemoryasyougofromhighlevelstolevelsintheheirarchy?55. Howdoesanaccessindirectmappedcachework?Whathappensiftherequested

dataisnotinthecache?56. Whatisthedisadvantageofhavingasingle‐cyclearchitecture?57. Whatarethe5stepsofaMIPSinstruction?58. Definestructuralhazard:59. Theconceptofpipeliningimprovesperformancebyincreasing________________,

asopposedtodecreasing_____________ofanindividualinstruction.60. Whendealingwithdatahazards,extrahardwareisaddedtoretrievemissingdata

earlyfromtheinternalresourcesiscalled:61. Whatarethefourunderlyingprinciplesofhardwaredesign(brieflyexplain)?62. Writetheequationforcalculatingcomputerperformance(CPUtimeinseconds).

NameseveralcomponentsthataffectCPUtimeperformance:63. DrawthecompletedatapathforanR‐typeinstruction.Writethefourmain

componentsofthisinstructioncycle.64. Whatarethe5stagesofMIPSpipelining65. Namethethreehazardscategoryforpipelining.Givepossiblesolutionsforeach

hazard.

66. Convertthedecimalnumber28intosignandmagnitude,1'scomplement,2'scomplement,octal,andhexidemical.Convertthedecimalnumber‐5into.Sign/magnitude,1'scomplement,and2'scomplement.Whataretheadvantagesof2's

complement?Whatisanadvantageofhexadecimalnumberswithrespecttobinary?

67. Whatarethepartsoftheinstructioncycle?68. Whichcomputercanexecuteeachinstructionfaster?ComputerA:CycleTime=

250ps,CPI=2.0andComputerB:CycleTime=500ps,CPI=1.2.69. WhataresomeadvantagestoasmallerPLA?70. Whataresomemicrocodeadvantagesanddisadvantages?71. Explainpipeliningusinglaundryandthefollowingimageandelucidatethespeed

increasefordoinglaundry.Thengivesomeadvantagesanddisadvantagesofpipelining.

72. Provideanexampleofadatahazard,andbrieflyshowwherethehazardlies.Provideaworkaroundforthedatahazard.Provideanexampleofacontrolhazard,andbrieflyshowwherethehazardlies.

73. Whatistherelationshipbetweencapacityandspeedthatistypicalinallkindsofcomputermemory?Whyisthisthecase?

74. List2differencesbetweentheR‐typeinstructiondatapath,andtheI‐typeinstructiondatapath.List2differencesbetweentheI‐typeinstructiondatapath,andtheJ‐typeinstructiondatapath.Listtworesponsibilitiesoftheprocessorcontrolunitinadatapath.

75. DetermineifthefollowinginstructionisanR‐type,I‐type,orJ‐typeinstruction,andthendecodeit.00000001000000000000200000100000

76. Whichinstructiontypeallowsshifting?Byhowmuchcananumberbeshifted?Why?Whatistherangeofjumpaddresses?Why?WhatisthelargestnumbertheMIPSarchitecturecancompareinImmediate‐typeinstructions?

77. GivetheabbreviationsanddescriptionsforthefivestagesoftheMIPSPipeline?78. Givethenameandabriefdescriptionofthethreetypesofpipelininghazards?79. Whatarethreemethodsforavoidingdatahazards?80. Whatarethefourbasicprinciplesofcomputerdesign?81. Whatarethebenefitsanddrawbacksoffullyassociativecachevs.directmapped

cache?

82. WhatdoesthefollowingVerilogcodeaccomplish?

module testquestion( input [31:0] Din, input [15:0] Address, input WriteEnable, input clock, output reg [31:0] Dout ); parameter RAM_WIDTH = 32;//A 32 bit wide data bus parameter RAM_ADDR_BITS = 16;//A 16 bit wide address bus /*Set the size of SRAM to 64k x 32*/ reg [RAM_WIDTH-1:0] SRAM [(2**RAM_ADDR_BITS)-1:0]; /*Read in data preloaded from a hex text file*/ initial $readmemh("memtest.txt", SRAM); /*Set SRAM at the Address to Din if clock and write enable are 1*/ /*Then set Dout to be that value of SRAM at address*/ always @(posedge clock) begin if (WriteEnable) SRAM[Address] <= Din; Dout <= SRAM[Address]; end endmodule

83. WhatdoesthefollowingVerilogcodeaccomplish?

module testquestion (ALUOp, Function, A, B, ALUOut, Overflow, Zeroflag, COut); input [1:0] ALUOp;//The ALU Op Code input [5:0] Function;//The Funct input [31:0] A,B;//Inputs output reg [31:0] ALUOut;//The output after performed operation output Overflow;//Overflow bit output Zeroflag;//The zeroflag output COut;//The carryout assign Zeroflag = (ALUOut==0); //Zeroflag is true if ALUOut is 0

always @ (ALUOp or Function or A or B)

begin if (ALUOp == 2 && Function == 36) ALUOut <= A & B;//and else if (ALUOp == 2 && Function == 37) ALUOut <= A | B;//or else if (ALUOp == 2 && Function == 32) ALUOut <= A + B;//add else if (ALUOp == 2 && Function == 34) ALUOut <= A - B;//sub else if (ALUOp == 2 && Function == 42) ALUOut <= A < B ? 1:0;//slt else if (ALUOp == 2 && Function == 0) ALUOut <= A << B;//shift left else if (ALUOp == 2 && Function == 2) ALUOut <= A >> B;//shift right else if (ALUOp == 2 && Function == 39) ALUOut <= ~(A | B);//nor else if (ALUOp == 2 && Function == 38) ALUOut <= A^B;//xor else if (ALUOp == 2 && Function == 40) ALUOut <= A~^B;//xnor else ALUOut <= 0;//If the opcode is not 2, then output 0 end endmodule

84. Labelthefollowingmotherboardparts:

85. Express14,‐14,25,and‐25inOne’sComplement,Two’sComplement,andSignand

Magnitude.86. Listthe4Principlesofhardwaredesign.87. Definesignoverflowandspecifyhowwecanchecktoseeifithasoccurred.88. Whatarethefourdesignprinciplesdiscussedinchapter2?89. Listthethreedifferenttypesofmemorytechnologiesfromfastesttoslowestand

describethem.90. Listadvantagesanddisadvantagesofpipelining.91. WhatarethefourtypesofaddressinginMIPS?

92. Labelthecomponentsonthemotherboardimagebelow:

93. WhatarethefourInstructionSetArchitecture(ISA)designprinciples?94. Represent15,‐15,20,‐20,31,and‐31insix‐bittwo’scomplementbinarynotation.95. CompletetheALUunitwritteninVerilog.Assumethesecontrolvaluesforthe

operations:• 0:BitwiseAND;• 1:BitwiseOR;• 2:Addition;• 6:Subtraction;• 7:SLT;• 12:BitwiseNOR.• Alsobeabletohandleothercontrolinputvalues.

moduleMIPSALU(ALUctl,A,B,ALUOut,Zero); 96. IsiteasiertoimplementpipeliningforaRISCarchitectureoraCISCarchitecture?In

eithercase,whatshouldyouwatchoutforwhileimplementingpipelining?97. Whatarethetwotypesofcachingcalled?Whatarethetwotypesoflocalitiesthat

areusedtomakecachememoryperformfaster?98. Whatarethethreepiecesofinformationthatmustbestoredincacheforeach

word?99. Whenahazardoccurs,abubble/stallcanbeinsertedinthepipeline,butthisslows

downthepipelineanddegradesprocessorperformance.Therearetwoalternativesthatavoidstalling–whatarethey?

100. WhatarethefivestagesoftheMIPSpipeline?101. Whatarethemainproandcon(1ofeach)ofincreasingassociativityinan

associativecache?102. Definebothspatiallocalityandtemporallocality.103. ExplainthedifferencebetweenDirectMapandAssociativecachestructures.104. DescribeHittime,hitrate,missrate,andmesspenalty.105. IdentifytheFiveStagesofLoad.106. Howmanytotalbitsarerequiredforadirectmappedcachewith16KBofdata

and4‐wordblockswith32‐bitaddress?107. NameallthreePipelineHazardsanddefinethem108. WhataretheFiveStagesofaDatapath?109. WhatarethetwotypesofLocality?110. Add45and‐38in2’scomplementformat.Use8‐bits.111. NametwotypesofBranchPredictionanddefinethem.

112. Whatthreethingscompriseofthemostbasiccomputer:113. Allcomputersaremadeupofthesethings,andbuilduponthesethings.Give

oneexampleofhowthesethreethingsaremadeintoamorecomplicatedsystem.114. Inthepipeliningprocess,whatisahazard?115. Whatarethenamesofthethreekindsofhazardsdiscussed?116. Whydoeachoftheabovehazardscauseproblems?117. Assumingthatthefollowingcodeisplacedinapipeline,whatpotentialproblem

lieswithinthecode?Giveanexampleofhowthisproblemcanbefixedonahardwarelevel.

sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2)

118. Giveananalogythatexplainswhytheconceptofpipeliningiseasyatitsbasicidea.

119. Whatcomplicatesthingsinthepipeline?Giveanexampleofone.120. ThePrincipleofLocalityplaysavitalroleinthewaythatdataisstoredinthe

computermemory.ExplainwhatthePrincipleofLocalityis,thenexplainthedifferencebetweentemporallocalityandspatiallocality.Indoingso,makesuretogivepracticalprogrammingusagesofeachtype.

121. Iftheclockrateis5GHzandtheIPC=.4,whatistheMIPSrating?122. IfA=0E26andB=B4CAwhatistheirsumiftheyrepresent16bitunsigned

hexadecimalnumbers?TheresultshouldbeinHexadecimal.123. WhatareAandBindecimalassumingtheyarea)unsigned?b)signand

magnitude?124. Acomputerisbasically:

• abunchofmultiplexorsandgatestobeanALU• aninterfacememory• controlledbyabunchofgatestotellthefirstbunchofgateswhattodo,

sequencedbyanall‐controllingclockedge• alloftheabove

125. R‐typeInstructionstandsfor__________Format?126. I‐typeInstructionstandsfor____________Format?127. J‐typeInstructionstandsfor____________Format?128. InMIPScode,OPandFUNCTareeach____bits?129. InMIPS,rs,rt,andrdareeach___________bits?