30 nm In0.7Ga0.3As Inverted-type HEMT with Reduced Gate Leakage Currentg

for Logic Applications

T.-W. Kim, D.-H. Kim* and J. A. del AlamoMicrosystems Technology Laboratories

MITPresently with Teledyne Scientific

Sponsors: Intel & FCRP-MSD

Fabrication: MTL, NSL, SEBL

Ackno ledgements MBE Technolog for epi afer

IEDMDecember 7-9, 2009

11

Acknowledgements:MBE Technology for epi wafer

UNIST in Korea for TEM analysis

Outline

1. Introduction

2. Device Technology

3. Logic Characteristics

4. Benchmarking with normal HEMT and

Si CMOSSi CMOS

5 Conclusions

2

5. Conclusions

Insulator Scaling in III-V HEMTsM ti ti f fMotivation : - III-V HEMT: Model system for future III-V logic FETs

- HEMT scaling: Lg tins

- Problem: tins IG

10-4

10-3

tins = 10 nm tins = 7 nm

10-6

10-5

m]

tins

= 4 nm

InAlAs/InGaAs HEMTLg = 30 nm

ID

I

tins = 4 nm

10-8

10-7

I D, IG [A

/ Lg 30 nmIG7 nm

<del Alamo, TWHM 09>

-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.5010-10

10-9

VDS = 0.5 V

10 nm

3

VGS [V]

• Inverted HEMT design: reduced IG

Concept of Inverted HEMT<Normal HEMT > <Inverted HEMT ><Normal HEMT > <Inverted HEMT >

InsulatorCap.

Gate

Insulator

Cap.

Channel

Barrier

Channel

Barrier

Si doping

0 4

0.6

E

Inverted HEMT VGS = +0.25 V2.5

3.0

0 4

0.6 Normal HEMT VGS = +0.3 V

2.5

3.0

0.0

0.2

0.4 Electron density [Prof

iles

[eV]

1.5

2.0

0 0

0.2

0.4 Electron density

Prof

iles

[eV]

1.5

2.0

2.5

0 10 20 30 40 50-0.4

-0.2

0.0 [x 1018/cm

3]

CB

P

ns,ch =

1.5 X 1012/cm20.0

0.5

1.0

-0.4

-0.2

0.0

ns,ch =

1.6 X 1012/cm2

y [x 1018/cm

3]

CB

P

0.0

0.5

1.0

4• Lower leakage current due to higher barrier under gate

0 10 20 30 40 50Vertical depth [nm]

0 10 20 30 40 50Vertical depth [nm]

Trade-off of Inverted HEMT

: Access region  : Contact region0.8

4

0.8

4

0 2

0.4

0.6

Electron Deile

s [e

V]

2

3

0 2

0.4

0.6 Electron Denile

[eV]

2

3

-0.2

0.0

0.2 ensity [1018/cm

3]

CB

Pro

fi

ns,ch =

0 6X1012/ 2

1

2

-0.2

0.0

0.2 nsity [1018/cm

3]

CB

Pro

f

1

2

ns,ch =

0 68 x 1012 /cm2

0 20 40 60 80 100-0.4

Vertical depth [nm]

0.6X1012/cm20

0 10 20 30 40 50 60 70-0.4

Vertical depth [nm]

00.68 x 10 /cm

ns,ch ~ 2.7 x 1012/cm2 for Normal HEMT ns,ch ~ 3 x 1012/cm2 for Normal HEMT

55

• Problem: - low ns in access region - large energy barrier under contact region

New ApproachGate

New doping layer

0.6 4

: Access region  : Contact region

0.6

4

0.2

0.4 Electron Densof

iles

[eV]

2

3

0.2

0.4 Electron Densof

ile [e

V]

2

3

-0.2

0.0

sity [1018/cm

3]

CB

Pro

ns,ch =

2.7X1012/cm2

1-0.2

0.0

sity [1018/cm

3]

CB

Pro

1ns,ch =

2 4 x 1012 /cm20 20 40 60 80

-0.4

Vertical depth [nm]

2.7X10 /cm0

ns,ch ~ 2.7 x 1012/cm2 for Normal HEMT ns,ch ~ 3 x 1012/cm2 for Normal HEMT

0 10 20 30 40 50 60-0.4

Vertical depth [nm]

02.4 x 1012 /cm2

6

• High ns in access region• Low barrier in contact region

Epitaxial Heterostructure

n+ In0.65Ga0.35As 5 nmn+ In0.53Ga0.47As 15 nmCap 0.53 0.47

n+ In0.52Al0.48As 15 nmInP 6 nm Si -dopingEtch stopper

In0.52Al0.48As 2 nmIn0.52Al0.48As 8 nm

In Ga As 2 nm

S dop gBarrier

In0.53Ga0.47As 2 nmIn0.7Ga0.3As 8 nmIn0.53Ga0.47As 3 nm

Channel

In0.52Al0.48As 5 nmIn0.52Al0.48As

Back Barrier + Buffer n,Hall = 9,800 cm2/V-sec

7

S. I. InPSubstrate

Device Technology

S

Cap

DOxide

LsideCap

Lg

Etch stopper

Barrier tins

Lside

Channel

Buffer

instch

- Triple-recess process- tins = 4 nm, Lside = 80 nm- Gate: Ti/Pt/Au

8

Buffer- Lg: 30 - 130 nm

Output & Transfer Char. : LG = 30 nm0.8

V =0 3 V0.5

0.6

1200

1400VDS=0.5 V

0.4

0.6

0.1

0.2

VGS=0.3 V

mA

/m

]

0.3

0.4 GM [m

S

mA

/m

]

800

1000

1200

0.2-0.1

0 I D [m

0.1

0.2

S/mm

]I D [m

200

400

600

0.0 0.2 0.4 0.6 0.8 1.00.0

-0.2

VDS [V]

-0.4 -0.2 0.0 0.2 0.40.0

VGS [V]

0

00

Good ID saturation, pinch-off behavior

G 1 27 S/ @ V 0 5 V

99

Gm = 1.27 S/mm @ VDS=0.5 V

3 Subthreshold Char. : Lg = 30 nm

10-4

10-3

ID

10-6

10-5

VDS= 0.5 V

VDS= 0.05 V

[A/

m]

10-8

10-7

IG

I D &

I G [

-0 6 -0 4 -0 2 0 0 0 2 0 410-10

10-9

-0.6 -0.4 -0.2 0.0 0.2 0.4

VGS [V]

• DIBL = 118 mV/V, S = 83 mV/dec.

10

• Excellent IOFF

ION/IOFF= 3.9 X 104 for VDS = 0.5 V

fT & fmax Char. : Lg = 30 nm

40

30

U

]

H21

20

MAG/MSG

fmax= 550 GHzGai

n [d

B]

10

fT= 500 GHzVGS=0.2 VVDS=0.8 V

109 1010 1011 10120

Frequency [Hz]

VDS 0.8 V

11

fT=500 GHz & fmax=550 GHzHighest fT & fmax reported on Inverted HEMTs

Inverted vs. Normal HEMTs: IG

4

10-3

VDS = 50 mV

Inverted HEMT Normal HEMT

VDS = 0.5 VID

6

10-5

10-4

VDS = 50 mV

VDS = 0.5 VDS

m]

Lg = 30 nm

10-7

10-6

VDS = 50 mV

VDS = 0.5 V

& I G

[A/

m

IG

10-9

10-8I D

IG

<D -H KIM IPRM 09>

-0.50 -0.25 0.00 0.2510-10

VGS [V]

12

Inverted HEMT: ~100 X less IG than normal HEMT<D.-H. KIM IPRM 09>

Inverted vs. Normal HEMTs: ION/IOFF vs. Lg

10-3

10-2

Inverted HEMT Normal HEMT

ION

6

107

6

10-5

10-4

IA/

m]

105

106

10-8

10-7

10-6 ION /IO

FF

I ON &

I OFF

[A

3

104

20 40 60 80 100 120 14010-10

10-9

IOFF102

103

VDS = 0.5 V

Inverted HEMT:

Lg [nm]

13

Excellent ION/IOFF scalability down to Lg = 30 nm

Inverted vs. Normal HEMTs: gmi

3.2

Inverted HEMT : n,Hall = 9,800 cm2/V-s

Normal HEMT n,Hall = 11,000 cm2/V-s

g from S parameters2 4

2.8

m] gmi from S-parameters

2.0

2.4

g t& g

m,e

xt [S

/mm

gmi

1.2

1.6gm,ext

g mi &

VDS=0 5V

Inverted HEMTs:

10 100Gate Length [nm]

VDS=0.5V

Inverted HEMTs:- Lower values of gmi: from reduced and velocity- Better gmi scalability down to 30 nm 14

Inverted vs. Normal HEMTs: Rs

<Using gate current injection technique>0.40

Inverted HEMT

0 32

0.36Inverted HEMT

Normal HEMT

]

RS=0.27 ohm.mm Rsh =100 ohm/sq

0.28

0.32

Rs* [o

hm.m

m]

0 20

0.24 Rsh =70 ohm/sq

RS=0.225 ohm.mm

R

0 40 80 120 1600.20 RS 0.225 ohm.mm

Lg [nm]

15

Higher Rs in inverted HEMTWhy? Lower ns in access region, higher Rc

Inverted vs. Normal HEMTs: fT and fmax

600

700 Inverted HEMT Normal HEMT 0.30

Inverted HEMT

400

500

600

fmax

fT

GH

z]

fT 0.20

0.25

ce g

o [S/m

m] Normal HEMT

200

300fmax

f T & f m

ax [G

0.10

0.15

ut c

ondu

ctan

c-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5

0

100

V [V]

Lg = 30 nm VDS = 0.8 VVDS = 0.8 V Lg = 30 nm

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.40.00

0.05

Out

puV [V]

Inverted HEMTs: Lower f & higher f

VGS [V] VGS [V]

16

Lower fT & higher fmax

Improved go: possibly due to lower ns in access region

Benchmarking : SS & DIBL

180

] I t d HEMT

Si FETs (IEDM)400

Inverted HEMT

Si FETs (IEDM)

140

160

pe [

mV/

dec] Inverted HEMT

Normal HEMT

200

300

V/V]

Normal HEMT

100

120

hres

hold

Slo

100

200

DIB

L [m

V10 100

60

80

Gate Length [nm]

Subt

h

10 1000

Gate Length [nm]

Excellent SCE of inverted HEMT

Gate Length [nm] Gate Length [nm]

1717

Benchmarking : ION vs. ILeak

0.5 VDD = 0.5 Vx 10-3

InGaAs normal HEMT Lg = 30 nm

)(21

,ONGOFFleak III

0.4

g

InGaAs Inverted HEMT Lg = 30 nm65 nm HP-CMOS (Lg = 35 nm)

0 2

0.3

N [A

/m

] 65 nm LP-CMOS (Lg = 55nm)

0.1

0.2I ON

10-9 10-8 10-7 10-60.0

18 At Ileak = 100 nA/μm, 1.3X higher ION than 65 nm HP CMOS

Ileak [A/m]

Benchmarking : CV/I vs. Lg10

Inverted HEMTs Normal HEMTs

1 I G A HEMTAY

[pse

c]

1 In0.7Ga0.3As HEMTs (VDD = 0.5V)

GA

TE D

ELA

100 101 102 1030.1

G Si NMOSFETs(VDD = 1.1~1.3V)

Gate Length, Lg [nm]

Inverted HEMT:

19

Comparable Gate delay with Lg but at lower VDD

< Ref. : Chau et al. (T-Nano 2005) >

Conclusions

• Inverted InGaAs HEMTS li b fit– Scaling benefit:• Reduced Ig allows for further Lg scalingAt 30 i t d HEMT hibit ll t h t i ti– At 30 nm, inverted HEMTs exhibit excellent characteristics:• DIBL < 120 mV/V, S < 85 mV/dec and ION/IOFF ~ 4 x 104

• f > 500 GHz and f > 550 GHz CV/I ~ 1 psec• fT > 500 GHz and fmax > 550 GHz, CV/I ~ 1 psec

• Inverted InGaAs HEMT: promising layer structure for futureInverted InGaAs HEMT: promising layer structure for future high-K/III-V MOSFET

2020