CPU Architecture - Advanced

Yong Heui Cho @ Mokwon University

Some of slides are referred to:[1] 3.3 Computer Architectures, slideshare.

Basic Computer Design

5. Sequential Logic Circuit

6. CPU Architecture - Ba-sic7. CPU Architecture - Ad-vanced8. ARM CPU

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Simplified Architecture

□ Courtesy to The CPU, slideshare.

IR

data

Control Unit (CU)

ALU

von Neumann Architecture

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Features• Data and instructions can be stored

in the same memory.• It uses a single processor for pro-

gram control.• Cycle: fetch-decode-execute-store• Execution performs the instruction

at a time in a linear sequence.

□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.

Machine Cycle• Fetch-decode-execute-store

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Example of Cycle

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CISC• Complex Instruction Set Com-

puter• CISC has more complex instruc-

tions available to it thus it may be able to perform the task in just one cycle (by using one of its complex operations available)– Large number of instructions avail-

able

□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.

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CISC of Intel• PCs, servers → mobile devices

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RISC• Reduced Instruction Set Com-

puter• RISC only has a simple instruc-

tion set thus to perform a com-plex task it may take several ‘cycles’ of basic instructions.– Limited number of instructions

available

□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.

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RISC of ARM• Mobile devices → PCs, servers

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Example of CISC/RISCA RISC might have the opera-tions:• ADD• SUB• DIV• etc

A CISC might have the operations:• ADD• SUB• DIV• AVR (average)• etc

Task: find the average!

□ Courtesy to 3.3 Computer Architectures, slideshare, slideshare.