Cpu control.12/15
Datapath and Control Unit Design
Simple Processor!
(4.1- 4.4 4th ed)
Cpu control.22/15
Datapath vs Control
• Datapath: Storage, FU, interconnect sufficient to perform desired functions
– Gets Control inputs from control
• Controller: controls operation on data path
Datapath Controller
Control Points
signals
Cpu control.32/15
CPU Performance
• Performance determined by:–Instruction count - code–cycle time–cycles per instruction - CPI
• Processor design impacts:–cycle time clock–cycles per instruction
CPI
Inst. Count Cycle Time
Cpu control.42/15
MIPS Format (Review)• All MIPS instructions 32 bits. Three formats:
– R
– I
– J op target address
02631
6 bits 26 bits
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
Cpu control.52/15
Instructions executed in steps
• R-type: fetch inst., select registers (rs, rt), [operand fetch]
ALU operationwrite back registers
• lw/sw: fetch instructionselect a register(rs)calculate address, need ALUaccess memory (read/write)write register file (lw)
• Branch: fetch the instructionselect registers (for beq)test condition, calculate target addr., need ALU
• First two steps are common
Cpu control.62/15
Functional Units - to build datapath review
PC
Instructionmemory
Instructionaddress
Instruction
a. Instruction memory b. Program counter
Add Sum
c. Adder
ALU control
RegWrite
RegistersWriteregister
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Writedata
ALUresult
ALU
Data
Data
Registernumbers
a. Registers b. ALU
Zero5
5
5 3
16 32Sign
extend
b. Sign-extension unit
MemRead
MemWrite
Datamemory
Writedata
Readdata
a. Data memory unit
Address
Cpu control.72/15
Review: How Registers work • Register
– Similar to D Flip Flop• N-bit input and output• Write Enable input
– Write Enable:• negated (0): Data Out will not
change• asserted (1): Data Out will become
Data In after clock edge
Clk
Data In
Write Enable
N N
Data Out
Cpu control.82/15
MIPS Register File• Register File consists of 32 registers:
– Two 32-bit outputs: Read data 1 & Read data 2– A 32-bit input bus: write data
• Register selection:– R1 (read register 1) selects the register to put on read data 1– R2 (read register 2) selects the register to put on read
data 2– RW (write register) selects the register to be written
(write data) when Write Enable is 1 (Regwrite)• Clock input (CLK)
– The CLK input is a factor ONLY during write operation– During read operation, behaves as a combinational logic
block:• Read data1 & read data 2 valid after “access time.”
Clk
Write data
Write Enable
3232
Read data 1
32
5 5 5RW R1 R2
32 32-bitRegisters Read data 2
Cpu control.92/15
Memory review
• Memory (Data)– Input: Data In (Write data)– Output: Data Out (Read Data)
• Memory word selection:– Address selects word– Write Enable = 1: address selects memory
word to be written via the Data In (Memwrite)• Clock input (CLK) (omitted from Book diag for simplicity)
– The CLK input is a factor ONLY during write operation– During read operation, behaves as a combinational
logic block:• Address valid => Data Out valid after “access time.”
• Instruction memory data not shown (similar)
Clk
Data In
Write Enable
32 32DataOut
Address
read dataWrite data
Cpu control.102/15
Clocking - Review
• All storage elements are clocked by the same clock edge• Cycle Time = CLK-to-Q + Longest Delay Path + Setup +
Clock Skew• (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold
Time
Clk
Don’t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
Cpu control.112/15
Single-Cycle: Instruction Fetch Datapath
• Instruction fetch– Inst. In instr. memory– program counter points
to current instruction– adder increments PC
to point to next inst.– For branch inst., the next
inst. address may not bevalid
Ad
d
4
PC Readaddress
Instruction
Inst memory
Next AddressLogic
Cpu control.122/15
• R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt– Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields– ALUctr and RegWr: control logic after decoding the instruction
32
Result
ALU control
Clk
Write data
Write
32
32
Read data 1
32
Read data 2
5 5 5
Rw R1 R2
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
R-type Datapath
Cpu control.132/15
Complete R-type Datapath
Readregister1
Readregister2
Writeregister
write data
register file
readdata 1
readdata 2
zero
result
ALU control
WriteA
dd
4
PC Readaddress
Instruction
Inst memory
Next AddressLogic
Cpu control.142/15
Timing: One complete cycle
32Result
ALUctr
Clk
Write data
RegWr
3232
Read data 1
32Read data 2
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
Clk
PC
Rs, Rt, Rd,Op, Func
Clk-to-Q
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
Read data 1& 2
Register File Access TimeOld Value New Value
Write data
ALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
Register WriteOccurs Here
Cpu control.152/15
Load/Store Datapathfetch same as R
• lw $1, offset-value($2) ; sw $1, offset-value($2)• register file (get base reg.)• ALU to calculate memory address• data memory: read OR write• sign extension (offset ext.) A L U c o n t r o l
w r i te
re a dw r i te
Read data1 rg 1 read data2 rg2 Write reg write data
Registerfile sign
ext.
1632
address
write data
readdata
data memory
Cpu control.162/15
Branch Inst. Datapath
• beq $1, $2, offset– if ($1=$2) goto PC+offset*4
• ALU for branch condition• Adder for computing branch
target address• Shift left 2: increases
the range of offset by 4• Zero: control logic to
decide if branch.
P C + 4 f ro min s t . d a ta p a th
Registers
ReadReg 1
ReadReg 2
Data1
Data2
Branchtarget
zero
To branchcontrollogic
shiftleft 2
signext.
16
32
AL
UA
dd
ALU control
Inst.
Cpu control.172/15
Complete Datapath for : R, LD/ST, BEQ
PC
Instructionmemory
Readaddress
Instruction
16 32
Add ALUresult
Mux
Registers
W riteregister
W ritedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Shift
left 2
4
Mux
ALUresult
ZeroALU
D atam emory
Address
W ritedata
Readdata M
ux
Sign
extend
Add
Executes basic instructions in single clock cycle
Any resource can only be once during a single cycle
Cpu control.182/15
Datapath controlled by control unit
PC
Instructionmemory
Readaddress
Instruction
16 32
Add ALUresult
Mux
Registers
Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Shiftleft 2
4
Mux
ALU operation3
RegWrite
MemRead
MemWrite
PCSrc
ALUSrc
MemtoReg
ALUresult
ZeroALU
Datamemory
Address
Writedata
Readdata M
ux
Signextend
Add
Identify your controls
Identify your controls
Cpu control.192/15
Single-Cycle: Control Signals
A L Uco n tro l
C o n tro l
inst [3
1-2
6]
in s t [5 -0 ]
1 6 -b i t
A L U o p
7 l in e sc o n tro lre g is te rm e m o rym u x
2 -b i t6 -b i t
3 -b i t
R - ty p e
I- ty p e
• Control:– input: 6-bit opcode– output: 9 control lines
• ALU control:– input: ALUop + 6-bit
(function field)– output: 3 lines– for I, J type, ALU control
depends on only ALUop
op func
Main
Cpu control.202/15
ALU Control, Truth Table
Inst opcode
Inst. operation
Desired ALU act.
ALUop Function code
ALU control
lw load word 00 xxxxxx
sw store word 00 xxxxxx beq branch equal 01 xxxxxx R-type add 10 10 0000 R-type sub 10 10 0010 R-type AND 10 10 0100 R-type OR 10 10 0101 R-type slt 10 10 1010
*ALUop: output of main controlR-: ALUop=10,
lw/sw: ALUop=00
*ALU Control: combinational logic 8 inputs, 3 output.
Cpu control.212/15
Datapath with Control unit
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
Cpu control.222/15
Datapath with Control unit
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
Cpu control.232/15
Datapath timings
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
400
200120
350
100
30100
30
30
Rformat timing= 400 +200+30 +120 +30 (IF – WB) OR = 400 + 100 (IF – cntl – Pcmux)
Cpu control.242/15
Control Unit -- Control Signal Definitions
Signal Name Effect when deasserted Effect when asserted
MemRead None Data put on read dataoutput MemWrite None Write data into memory
RegWrite None Write register ALUSrc 2nd ALUinput from
register file 2nd ALUinput from
inst[15-0]
PCSrc PC = PC+4 PC = branch address
MemtoReg result of ALU is sent data in memory is sent
RegDst inst[20-16] (rt) provides register write
address
inst[15-11]] (rd) provides register write address
PCsrc = branch AND zero
Cpu control.252/15
Example 1: Execution flow for add $1, $1, $3 (4 steps + bypass)
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
1. IF
2.D3. EX, ALU func.
5. WB write back result
4.Bypass
1. IF
1. IF
5
Cpu control.262/15
Example 2: LW S0, OFF(S1)Memory address = OFF + S1
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
1. IF
2.D
OFF
4.Mem rd
3. EX, calc address
5. WB write back result
Cpu control.272/15
Example 3: BEQ S1, S0, cs330target address = PC + offset x 4
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
BranchRegDst
ALUSrc
Instruction [31– 26]
4
16 32Instruction [15– 0]
0
0Mux
0
1
Control
Add ALUresult
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Shiftleft 2
Mux
1
ALUresult
Zero
Datamemory
Writedata
Readdata
Mux
1
Instruction [15– 11]
ALUcontrol
ALUAddress
1. IF
2.D3. EX, compare s1:s0
Update PC with target addr. If successful
Cpu control.282/15
Single-Cycle: J-type
• So far, datapath can handle R-type, lw/sw, beq– How about J-type?– J-type j L1 P.372
jal L1 Exercise 5.6
address= current PC =
Actual address L1 =
31-26 25-0
address
a a25 0... PC PC PC31 30 0...
pc pc pc pc a a31 30 29 28 25 0 00...
Cpu control.292/15
Single-Cycle: Datapath + Control including jump inst
Cpu control.302/15
What’s wrong with Single cycle CPI=1 processor?
• Long Cycle Time• All instructions take as much time as the slowest• Real memory is slow
Inst Memory ALU Data Mem
Reg FileInst Memory ALU
Inst Memory ALU Data Mem
Inst Memory cmp
Reg File
Reg File
Reg File
Arithmetic & Logical
Load
Store
Branch
Critical Path
RegW
RegW
Cpu control.312/15
Single Cycle Timing Diagram
Clk
Single Cycle Implementation:Load Store Waste
Cycle 1 Cycle 2
Cpu control.322/15
8051Microcontroller Block Diagram: Used in Lab project
Used to implement low cost applications & Embedded SystemsEg automotive, appliances, elevators
CPU VS Microcontroller Microcontroller = CPU + Flash(ROM) + RAM + popular I/O peripherals.
Cpu control.332/15
Microcontroller Block Diagram: PIC