A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Cover Sheet
1 51Wednesday, November 03, 2004
Compal Electronics, Inc.
2004-11-03
Revision :
COMPAL P/N :PCB NO :
COMPAL CONFIDENTIALMODEL NAME :
1.0 (DELL: A00)
TOBAGO
TOBAGO Schematics Document
uFCBGA/uFCPGA Mobile DothanIntel Alviso + ICH6M
REV : 1.0 (DELL: A00)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
45128331001/45128331002LA2151
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Block Diagram
2 51Monday, October 18, 2004
Compal Electronics, Inc.
PCI BUS
LPC BUS
Clock Generator
USB Ports X4
uFCPGA CPU
CardBus& 1394
INTEL
DMI
H_D#(0..63)H_A#(3..31)
Compal confidentialModel : Tobago
AMP & INT.Speaker
page 7,8
page 31,32
page 6
page 10,11,12,13,14
page 28
Pentium-M
Block Diagram
88SA8040
page 25
AC97 Codec
page 26
page 34,35
Power On/OffSW & LED
page 39
System Bus
INTEL
MACALLAN III
R5C841
Memory BUS(DDR2)
+VCCP 400/533 MHz
+1.5VRUN 100MHz
+3VRUN 33MHz
+1.8VSUS 400MHz
48MHz
24.576MHz
ATA100
+3VRUN33MHz
MDCpage 29
Minipci CONN
page 33
1257BGA
page 21,22,23,24
CY28411ZCTpage 15
STAC9751
IDSEL:AD17(PIRQC,D#,GNT#1,REQ#1) AC-LINK
page 27
LPC47N354
IDSEL:AD19(PIRQB,D#,GNT#3,REQ#3)
Alviso
Int.KBDpage 36
ICH6-M
PCI-E 16XVGA CONN
CRT CONNpage 20
TV OUTpage 20
EC DEBUGpage 36
RJ11
page 27
HeadPhone &MIC Jack
page 25
IDECD-ROM+5VMOD
+5VRUN
+3VALW
+3VALW+3VRUN
+1.8VRUN
+VDDA
+5VRUN +5VRUN
+5VSUS+3VRUN
+3VSUS
+1.5VRUN
+1.5VSUS
+2.5VRUN
+3VRUN+3VSUS
+3VSUS
WIRELESS
+1.8VSUS
+1.5VRUN
+VCCP
+VCC_CORE
+VCCP (1.05V)
+3VRUN
BANK 0, 1, 2, 3
page 16,17
DDRII-DIMM X2
+0.9V_DDR_VTT
+1.8VSUS
Cable
page 18
+3VSUS
page 31
1394page 32
Card BusSLOT CONN
478pin
USB[4,5,6,7]
page 29
LCM SW & Touch Pad & LID SW
page 37
DC/DC Interface
CPU ITP Portpage 7
CRT Signal
LVDS CONNon VGA Board
LVDS CONNon M/B Board
page 19
Internal LVDS
+5VRUN
+5VRUNDothan
+3VRUN
VGA Board
SATA
+2.5VRUN
+3VRUN+3VRUN
48MHzUSB[3]
page 30
RJ45page 30
BCM4401KQL
+3VLAN
VCORE
1.5V/1.05V
page 45
page 43
page 46
CHARGER
1.8V/0.9Vpage 44
BATT IN/2.5Vpage 41
page 40
DC IN
3V/5V/15Vpage 42
IDSEL:AD16(PIRQC#,GNT#4,REQ#4)
GUARDIANEMC6N300 page 15
Thermal
+3VSUS
FAN
Parallel ATApage 25+5VHDD
+VCCP
+3VALW
Power Sequence& RTC BATT
page 38+3VALW
SST39VF080
X BUS
DELL CONFIDENTIAL/PROPRIETARY
609 BGA
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
page 32
SD cardSLOT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Index and Config.
3 51Monday, October 18, 2004
Compal Electronics, Inc.
PIRQ
D,C
C
D,B
+VCCP
PM TABLE
+15V
ON
ON
AD17
OFF
PCI DEVICE
TABLE
CARD BUS
IDSEL
S0
TABLE
3
1
PCI
ON
ON
MINI PCI
+1.5VSUS
S3
USB
ON
OFF
ON
+3VSUS
OFF
+5VSUS
AD19
+5VALW
S1
S5 S4/AC don't exist
+1.8VRUN
+VCC_CORE
AD16
REQ#/GNT#
+5VRUN
ON
powerplane
+3VRUN
4
S5 S4/AC
ON
ON
+3VALW
State
OFFOFF
LAN
OFF
+1.5VRUN
0
1
4,5
USB PORT# DESTINATION
3
SIDE
NC
2
PCMCIA
NC
REAR
Blue tooth
6,7
Tolerance0.1U_0402_6.3VXX
Ceramic Capacitors :
Temperature CharacteristicsRated VoltagePackage SizeValue
CH
A
Capacitor Spec Guide:
1
SL
CODE
COG SJ
9
B
+-3%
CODE
Symbol F
+40,-20%+-20%
4
G
+20,-10%
X
UK
5
B
Z
C
+-0.05PF
Y5V
Temperature Characteristics:
Y5P
CK
V
+-0.1PF
X5R
A
Z5U
BJ
+100,-0%
Y5U X7R
P
+-30%
C
SH
8
H
CJ
+30,-10%
K
+-5%
7
Q
+80,-20%
6
+-0.5PF +-1PF
Z5V
+-10%
J
+-0.25PF
Tolerance:
+-2%
N
D
Z5P
2
UJ
D E F G
H I J
30Symbol
X6SNPO
K
X5S
M
ValuePackage SizeRated VoltageToleranceLow ESR Mark : 45 m ohm
10U_D2_10VX_R45
Tantalum or Polymer Capacitors :+0.9V_DDR_VTT
@XX : Depop component
NOTE1:
1@XX : Pop for Integrated Graphic
2@XX : Pop for External Graphic
+1.8VSUS
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Power Rail
4 51Monday, October 18, 2004
Compal Electronics, Inc.
+5VALW
+5VSUS
BATTERY
PWR_SRC
+3VSUS
+3VALW
+3VRUN
ADAPTER
+VCC_CORE
RU
N_O
N
RU
NP
WR
OK
SU
S_O
N
SU
S_O
N
RU
N_O
N
+5VHDD +5VRUN VDDA
AUD
IO_A
VD
D_O
N
SU
SP
WR
OK
_5V
+1.8SUS +0.9V_DDR_VTT
SU
SP
WR
OK
_5V
RU
NP
WR
OK
+VCCP
+1.5VRUN
RU
N_O
N
MAX
1845
_VC
C
+1.5VSUS
(Opt
ion)
+15V
+2.5VRUN
MAX1999 MAX1987 MAX1845 MAX8550
MAX1806 +1.8VRUNR
UN
_ON
RU
N_O
N
PL8
L47
793333
FDS4435 G_PWR_SRC+5VRUN
SI4810
RU
N_O
N
SI4810SI3456SI3456
HD
DC
_EN
#
SI4810
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RU
N_O
N_D
(Inte
grat
ed)
(Dis
cret
ed)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
SMBUS TOPOLOGY
5 51Monday, October 18, 2004
Compal Electronics, Inc.
+3VRUN
CLK_SDATACLK GEN.
SBAT_SMBCLKMacallan III
7002
ICH6-M
SBAT_SMBDAT
DAT_SMB
7002
+3VALW
CLK_SMB
GUARDIAN
+5VALW
ICH_SMBDATA +3VSUS
ICH_SMBCLK
INVERTER
24C04
CLK_SCLK
SIO
PBAT_SMBCLK
PBAT_SMBDAT +5VALW BATTERY
CHARGER
DELL CONFIDENTIAL/PROPRIETARY
DIMM1
DIMM0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_SMBCLK
ICH_SMBDATA
CK_VDD_MAIN
CLKIREF
CLK_SDATA
CLK_SCLK
CLK_XTAL_OUT
CLK_ICH_48M CLKSEL2
CLK_XTAL_IN
CLK_SDATA
CLK_SCLK
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_PCIE_ICH#
CLK_PCIE_ICH
H_STP_CPU#
H_STP_PCI#
MCH_3GPLL
MCH_3GPLL# CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CLK_ICH_14M
CLK_CODEC_14M
CLKREF
CLKSEL1
CLK_ENABLE#
CLK_PCI_LOM PCI_LOM
PCI_SIOCLK_PCI_SIO
CLK_SIO_14MCLKSEL1
CLKSEL2
PCI_MINICLK_PCI_MINI
CLK_PCI_PCM PCI_PCM
CLK_PCI_ICH PCI_ICH
PCICLKF0
DOT96 DREFCLK
DREFCLK#DOT96#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CK_VDD_A
CK_VDD_REF
CK_VDD_48
CK_VDD_48CK_VDD_A CK_VDD_REF
DREFCLK#
DREFCLK
CLK_SSC_IN
CLK_PCIE_ICH#
PCIE_ICH CLK_PCIE_ICH
PCIE_ICH#
CLK_MCH_BCLK
CLK_MCH_BCLK#
MCH_BCLK
MCH_BCLK#
CPU_ITP# CLK_CPU_ITP#
CLK_CPU_ITPCPU_ITP
CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK
CPU_BCLK#
CLK_CPU_BCLK#
CLK_CPU_BCLK
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_ITP#
CLK_CPU_ITP
CLK_PCIE_SATA#
PCIE_SATA CLK_PCIE_SATA
PCIE_SATA#
PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_VGA
PCIE_VGA#
DOT96_SSC
DOT96_SSC#
DREF_SSCLK#
DREF_SSCLK
CLK_CODEC_14M
CLKSEL0
CLKSEL0
CK_VDD_MAIN+3VRUN+3VRUN
+3VRUN
+VCCP
+VCCP
+3VRUN
+3VRUN
CK_VDD_MAIN2
ICH_SMBCLK<23>
ICH_SMBDATA<23>
CLK_ICH_48M<23>
CLK_MCH_3GPLL# <12>
CLK_MCH_3GPLL <12>
H_STP_CPU# <23,45>
H_STP_PCI# <23>
CLK_ICH_14M <23>
CLK_CODEC_14M <26>
CLK_ENABLE# <11,45>
CLK_PCI_LOM<30>
CLK_PCI_SIO<34>
CLK_SIO_14M <34>
MCH_CLKSEL0 <10>
MCH_CLKSEL1 <10>
CPU_BSEL0<8>
CPU_BSEL1<8>
CLK_PCI_MINI<33>
CLK_PCI_PCM<31>
CLK_PCI_ICH<21>
DREFCLK# <10>
DREFCLK <10>
CLK_SDATA <11,16,17>
CLK_SCLK <11,16,17>
CLK_SSC_IN <11>
CLK_PCIE_ICH <23>
CLK_PCIE_ICH# <23>
CLK_MCH_BCLK# <10>
CLK_MCH_BCLK <10>
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_PCIE_SATA# <22>
CLK_PCIE_SATA <22>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>
DREF_SSCLK <10,11>
DREF_SSCLK# <10,11>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Clock Generator
6 51Monday, October 18, 2004
Compal Electronics, Inc.
31
G
Place near each pinW>40 mil
S
Place near CK410
2N7002
2
D
FSC FSB FSA CPUMHz
SRCMHz
PCIMHz
266
133
200
166
333
100
400
RESERVED
100
100
100
100
100
100
100
33.3
33.3
33.3
33.3
33.3
33.3
33.3
0 0 0
00
0
0
0
00
0
0
1
1
1 1
1
1
1
1 1 1
1
1
Table : ICS954201BG
Place crystal within500 mils of CK410
*
CLKSEL0 CLKSEL2CLKSEL1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R27110K_0402_5%~D
12
R2732.2_0603_5%~D
1 2
R2741_0603_5%~D
1 2
R3300_0402_5%~D
1 2
C326
0.1U_0402_16V4Z~D
1
2
R322 49.9_0402_1%~D
12
R27
52.
2K_0
402_
5%~D
12
R259 12.1_0402_1%~D 1 2
C61
0.04
7U_0
402_
16V4
Z~D
1
2
R3050_0402_5%~D
@
12
R392 49.9_0402_1%~D
1 2
R27
02.
2K_0
402_
5%~D
12
R266 12.1_0402_1%~D
1 2
C50
4.7U
_080
5_10
V4Z~
D 1
2
R538
100K_0402_5%~D
@ 12
R294 33_0402_5%~D
12
R27810K_0402_5%~D@
12
R377 49.9_0402_1%~D
12
R385 49.9_0402_1%~D
1 2
R375 33_0402_5%~D1 2
X214.31818MHz_20P_1BX14318CC1A~D
12
R344 49.9_0402_1%~D
1 2
R3290_0402_5%~D
1 2
C3840.1U_0402_16V4Z~D
1
2 R349 49.9_0402_1%~D
12
U16
ICS954226AG_TSSOP56~D
VDD_SRC021VDD_SRC128VDD_SRC234
VDD_PCI01VDD_PCI17
VDD_4811
VDD_CPU42VDD_REF48
FSA/USB_4812
VSS_PCI02
FSB/TEST_MODE16
XTAL_OUT49
XTAL_IN50
VSS_SRC29
VSS_4813
VSS_CPU45
PCI2/REQ_SEL56
FSC/TEST_SEL53
SDATA47
SCLOCK46
PCIF0/ITP_EN8
PCIF1/SELPCIEX_LCDCLK#9
IREF39
SRC5 31
CPU_STOP# 54
CPU1 41
CPU1# 40
CPU_2_ITP/SRC_7 36
SRC5# 30
PCI33
PCI44
PCI55
CPU0# 43
CPU0 44
SRC6 33
SRC6# 32
PCI_STOP# 55
VSS_A 38
VDD_A 37
REF 52
VSS_PCI16
VSS_REF51
CPU_2_ITP/SRC7# 35
SRC4 26
SRC4# 27
SRC3 24
SRC3# 25
SRC2 22
SRC2# 23
SRC1 19
SRC1# 20
SRC0/LCDCLK_SS 17
SRC0#/LCDCLK_SS 18
DOT96 14DOT96# 15
VTT_PWRGD#/PD 10
R366 33_0402_5%~D1 2
R374 49.9_0402_1%~D
1 2
R368 33_0402_5%~D1 2
R33133_0402_5%~D
12
R355 49.9_0402_1%~D
1 2
R3421K_0402_5%~D
@
12
R393 49.9_0402_1%~D
1 2
R369 49.9_0402_1%~D
12
C3440.1U_0402_16V4Z~D
1
2
R381 49.9_0402_1%~D
1 2
C3890.1U_0402_16V4Z~D
1
2
R298 33_0402_5%~D
12
R397 33_0402_5%~D1 2
R376 33_0402_5%~D1 2
R400 33_0402_5%~D1 2
R277 33_0402_5%~D
12
R532 12.1_0402_1%~D
@12
R3531K_0402_5%~D
@
12
R3430_0402_5%~D
1 2
C3300.1U_0402_16V4Z~D
1
2
R399 49.9_0402_1%~D
1 2
R525 33_0402_5%~D1@1 2
R365 49.9_0402_1%~D
1 2
R301 12.1_0402_1%~D@ 1 2
G
D S
Q382N7002_SOT23~D
2
1 3
R5318.2K_0402_5%~D
12
C402
10U_0805_10V4M~D
1
2
G
D S
Q362N7002_SOT23~D2
1 3
C32927P_0402_50V8J~D
12
R360 49.9_0402_1%~D
12
R402 33_0402_5%~D1 2
R345 33_0402_5%~D
1 2
R4012.2_0603_5%~D
1 2
R31610K_0402_5%~D
1 2
C640.1U_0402_16V4Z~D
1
2
R394 33_0402_5%~D1 2
R522 49.9_0402_1%~D1@1 2
R3540_0402_5%~D
1 2
C52
0.04
7U_0
402_
16V4
Z~D1
2
R524 33_0402_5%~D1@1 2
R293 33_0402_5%~D
12
L32BLM21PG600SN1D_0805~D
1 2R338 49.9_0402_1%~D
12
C308
10U_0805_10V4M~D
1
2
R359 33_0402_5%~D1 2
C33327P_0402_50V8J~D
12
R356 33_0402_5%~D
1 2
R250 12.1_0402_1%~D
1 2
R321 33_0402_5%~D1 2
R382 33_0402_5%~D1 2
R523 49.9_0402_1%~D1@1 2
R3640_0402_5%~D
@
12
C68
4.7U
_080
5_10
V4Z~
D 1
2
R302 33_0402_5%~D
12
L40BLM21PG600SN1D_0805~D
1 2
C580.1U_0402_16V4Z~D
1
2
R362 475_0603_1%~D
1 2
R403 49.9_0402_1%~D
1 2
R348 33_0402_5%~D1 2
R337 33_0402_5%~D1 2
R386 33_0402_5%~D1 2
C51
0.04
7U_0
402_
16V4
Z~D1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ITP_TDIITP_TMS
ITP_TCK
ITP_TDO
ITP_TRST#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#4
ITP_BPM#5
ITP_DBRESET#
ITP_TDO
H_RESET#
H_RESET#
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
ITP_DBRESET#
H_A#28
H_THERMDA
H_FERR#
H_ADSTB#0
H_D#52
H_D#20H_A#23
H_REQ#2
H_D#10
H_D#5
H_D#49
H_D#3
H_A#31
H_REQ#0
H_D#39
H_D#57
H_D#29
H_A#17
H_IGNNE#
H_D#34
H_D#14
H_BNR#
H_A#29
H_DSTBP#0
H_D#51
H_D#22
H_A#8
H_DEFER#
H_INIT#
H_REQ#1
H_D#50
H_D#48
H_D#0H_A#3
H_RS#0
H_DSTBN#1
H_D#58
H_D#28
H_A#6
ITP_BPM#2
H_BPRI#
H_ADS#
H_A#25
ITP_BPM#3
H_RS#1
H_DSTBP#1
H_D#46
H_D#41
H_D#12
H_A#4
H_IERR#H_HITM#
H_DSTBN#0
H_D#47
H_D#37
H_THERMDC
H_INTR
H_DSTBN#2
H_D#9
H_D#7
H_A#22
H_A#7
H_REQ#4
H_D#31
H_D#13
ITP_DBRESET#
H_DRDY#
H_A#15H_A#14
ITP_TCK
ITP_BPM#3
H_A20M#
H_D#27
H_D#25
H_D#4
H_DSTBP#2
H_D#56
H_D#35
H_D#59
H_D#63
H_D#45
H_D#24
H_D#30
H_D#55
H_D#40
H_D#19
H_D#62
H_D#44
H_D#23
H_D#2
H_D#8
H_D#6
H_D#54
H_D#33
H_D#18
H_D#16
H_D#61
H_D#43
H_D#1
H_D#26
H_DSTBN#3
H_D#53
H_D#32
H_D#11
H_DSTBP#3
H_D#38
H_D#36
H_D#17
H_D#15
H_NMI
H_D#60
H_D#42
H_D#21
H_A#30
H_A#27
H_A#18
H_A#10
H_BR0#
H_LOCK#
H_A#11
H_A#21
H_A#26
H_A#13
H_A#9
CLK_CPU_BCLK#
ITP_BPM#0
H_DPSLP#
H_A#20
H_A#16
H_A#12
H_TRDY#
H_HIT#
H_ADSTB#1
H_DBSY#
H_A#19
H_A#24
H_A#5
H_RS#2
CLK_CPU_BCLK
H_RESET#
ITP_BPM#1
H_REQ#3
H_SMI#H_STPCLK#
ITP_TCK
ITP_TRST#
TEST1TEST2ITP_TMS
H_CPUSLP#
ITP_TDOITP_TDI
ITP_BPM#5ITP_BPM#4
H_DPRSTP#
H_THERMTRIP#
H_PWRGOOD
CLK_CPU_ITP#CLK_CPU_ITP
CPU_ITTP#CPU_ITTP
+VCCP
+VCCP
+VCCP
+VCCP
+3VSUS
+VCCP
+VCCP
+VCCP
H_THERMTRIP#<15>
H_THERMDA<15>H_THERMDC<15>
H_ADS#<10>
H_REQ#[0..4]<10>
H_A#[3..31]<10>
H_BPRI#<10>H_BNR#<10>
CLK_CPU_BCLK#<6>
H_DEFER#<10>
H_HITM#<10>
H_BR0#<10>
CLK_CPU_BCLK<6>
H_HIT#<10>
H_D#[0..63] <10>
H_DPSLP#<22>
H_RESET#<10>
H_DRDY#<10>
H_TRDY#<10>
H_RS#[0..2]<10>
H_ADSTB#0<10>
H_DSTBP#[0..3] <10>
H_ADSTB#1<10>
H_DSTBN#[0..3] <10>
H_DINV#0 <10>
H_DINV#2 <10>
CLK_CPU_ITP#<6>CLK_CPU_ITP<6>
H_DBSY#<10>
H_DINV#1 <10>
H_IGNNE# <22>
H_LOCK#<10>
H_INTR <22>H_NMI <22>
H_DINV#3 <10>
H_INIT# <22>
H_FERR# <22>
ITP_DBRESET#<38>
H_A20M# <22>
H_STPCLK# <22>H_SMI# <22>
H_PWRGOOD<22>H_CPUSLP#<10,22>
H_DPWR#<10>
H_PROCHOT#<35>
H_DPRSTP#<22>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Dothan Processor in mFCPGA479
7 51Monday, October 18, 2004
Compal Electronics, Inc.
This shall place near CPU
Add pullups for PWRGOOD and THERMTRIP per INTEL
Place near JITP
Check ITP connector.
H_THERMDA, H_THERMDC routing together.Trace width / Spacing = 10 / 10 mil
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R38739.2_0603_1%~D 1 2
R367150_0603_1%~D
1 2
ADDR GROUP
CONTROL GROUP
HOST CLK
MISC
DATA GROUP
THERMALDIODE
LEGACY CPU
DothanJCPUA
TYCO_1612364-1~D
A3#P4A4#U4A5#V3A6#R3A7#V2A8#W1A9#T4A10#W2A11#Y4A12#Y1A13#U1A14#AA3A15#Y3A16#AA2A17#AF4A18#AC4A19#AC7A20#AC3A21#AD3A22#AE4A23#AD2A24#AB4A25#AC6A26#AD5A27#AE2A28#AD6A29#AF3A30#AE1A31#AF1
REQ0#R2REQ1#P3REQ2#T2REQ3#P1REQ4#T1
ADSTB0#U3ADSTB1#AE5
BCLK0B15BCLK1B14
ITP_CLK0A16ITP_CLK1A15
ADS#N2BNR#L1BPRI#J3BR0#N4DEFER#L4DRDY#H2HIT#K3HITM#K4IERR#A4LOCK#J2RESET#B11
RS0#H1RS1#K1RS2#L2TRDY#M3
BPM0#C8BPM1#B8BPM2#A9BPM3#C9
DBR#A7DBSY#M2DPSLP#B7
DPWR#C19PRDY#A10PREQ#B10PROCHOT#B17
PWRGOODE4SLP#A6TCKA13TDIC12TDOA12TEST1C5TEST2F23TMSC11TRST#B13
THERMDAB18THERMDCA18THERMTRIP#C17
D0# A19D1# A25D2# A22D3# B21D4# A24D5# B26D6# A21D7# B20D8# C20D9# B24
D10# D24D11# E24D12# C26D13# B23D14# E23D15# C25D16# H23D17# G25D18# L23D19# M26D20# H24D21# F25D22# G24D23# J23D24# M23D25# J25D26# L26D27# N24D28# M25D29# H26D30# N25D31# K25D32# Y26D33# AA24D34# T25D35# U23D36# V23D37# R24D38# R26D39# R23D40# AA23D41# U26D42# V24D43# U25D44# V26D45# Y23D46# AA26D47# Y25D48# AB25D49# AC23D50# AB24D51# AC20D52# AC22D53# AC25D54# AD23D55# AE22D56# AF23D57# AD24D58# AF20D59# AE21D60# AD21D61# AF25D62# AF22D63# AF26
DINV0# D25DINV1# J26DINV2# T24DINV3# AD20
DSTBN0# C23DSTBN1# K24DSTBN2# W25DSTBN3# AE24DSTBP0# C22DSTBP1# L24DSTBP2# W24DSTBP3# AE25
A20M# C2FERR# D3
IGNNE# A3INIT# B5
LINT0 D1LINT1 D4
STPCLK# C6SMI# B4
DPRSTP#G1
R417150_0603_1%~D
1 2
T37 PAD~D@
R41554.9_0603_1%~D
1 2
R42422.6_0603_1%~D
1 2
R39856_0402_5%~D 1 2
T38 PAD~D@
JITP
MOLEX_52435-2891_28P~D@
TDI1 TMS2 TRST#3 NC14 TCK5 NC26 TDO7 BCLKN8 BCLKP9 GND010 FBO11 RESET#12 BPM5#13
BPM4#15
BPM3#17
BPM2#19
BPM1#21
BPM0#23 DBA#24 DBR#25 VTAP26 VTT027 VTT128
GND114
GND216
GND318
GND420
GND522
GN
D6
29G
ND
730
R423200_0402_5%~D 1 2
R391680_0402_5%~D
1 2
R41654.9_0603_1%~D
1 2
RN28
0_0404_4P2R_5%~D
@
1 42 3
R42256_0402_5%~D
1 2
C381
0.1U_0402_16V4Z~D
1
2
R43627.4_0603_1%~D
1 2
R43422.6_0603_1%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COMP3
VCCSENSE
COMP2
VID1VID0
VID2
VID5
VSSSENSE
VID3VID4
H_PSI#
CPU_BSEL0CPU_BSEL1
COMP1COMP0
+VCCP
+VCC_CORE
+VCCA_PROC
+1.8VRUN
+VCCP
V_CPU_GTLREF
V_CPU_GTLREF
+1.5VRUN
+VCC_CORE
H_PSI#<45>
VID0<45>VID1<45>VID2<45>VID3<45>VID4<45>VID5<45>
CPU_BSEL0<6>CPU_BSEL1<6>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Dothan Processor in mFCPGA479
8 51Monday, October 18, 2004
Compal Electronics, Inc.
Resistor placed within0.5" of CPU pin.Traceshould be at least 25miles away from anyother toggling signal.
R_B
R_A
Layout close CPU
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Note:Pop R97 for Dothan-A,Pop R92 for Dothan-B
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
JCPUB
TYCO_1612364-1~D
PSI#E1
GTLREFAD26
VCCQ0P23VCCQ1W4
VCCSENSEAE7VSSSENSEAF6
BSEL0C16BSEL1C14
VCCA0F26VCCA1B1VCCA2N1VCCA3AC26
VCCPD10VCCPD12VCCPD14VCCPD16VCCPE11VCCPE13VCCPE15VCCPF10VCCPF12VCCPF14VCCPF16VCCPK6VCCPL5VCCPL21VCCPM6VCCPM22VCCPN5VCCPN21VCCPP6VCCPP22VCCPR5VCCPR21VCCPT6VCCPT22VCCPU21
VCCD6VCCD8VCCD18VCCD20VCCD22VCCE5VCCE7VCCE9VCCE17VCCE19VCCE21VCCF6VCCF8VCCF18
VID0E2VID1F2VID2F3VID3G3VID4G4VID5H4
COMP0P25COMP1P26COMP2AB2COMP3AB1
RSVDAF7
RSVDB2RSVDC3RSVDE26
VSS A2VSS A5VSS A8VSS A11VSS A14VSS A17VSS A20VSS A23VSS A26VSS B3VSS B6VSS B9VSS B12VSS B16VSS B19VSS B22VSS B25VSS C1VSS C4VSS C7VSS C10VSS C13VSS C15VSS C18VSS C21VSS C24VSS D2VSS D5VSS D7VSS D9VSS D11VSS D13VSS D15VSS D17VSS D19VSS D21VSS D23VSS D26VSS E3VSS E6VSS E8VSS E10VSS E12VSS E14VSS E16VSS E18VSS E20VSS E22VSS E25VSS F1VSS F4VSS F5VSS F7VSS F9VSS F11VSS F13VSS F15VSS F17VSS F19VSS F21VSS F24VSS G2VSS G6VSS G22VSS G23VSS G26VSS H3VSS H5VSS H21VSS H25VSS J1VSS J4VSS J6VSS J22VSS J24VSS K2VSS K5VSS K21VSS K23VSS K26VSS L3VSS L6VSS L22VSS L25VSS M1RSVDAC1
R920_0805_5%~D
1 2
R15854.9_0603_1%~D@
1 2
C88
0.01
U_0
402_
16V7
K~D
1
2
R12
927
.4_0
603_
1%~D
12
R970_0805_5%~D
@
1 2
R1401K_0603_1%~D
12
R15954.9_0603_1%~D@
1 2
C87
10U
_080
5_10
V4M
~D
1
2
R46
527
.4_0
603_
1%~D
12
R12
454
.9_0
603_
1%~D
12
Dothan
POWER, GROUND
JCPUC
TYCO_1612364-1~D
VCCF20VCCF22VCCG5VCCG21VCCH6VCCH22VCCJ5VCCJ21VCCK22VCCU5VCCV6VCCV22VCCW5VCCW21VCCY6VCCY22VCCAA5VCCAA7VCCAA9VCCAA11VCCAA13VCCAA15VCCAA17VCCAA19VCCAA21VCCAB6VCCAB8VCCAB10VCCAB12VCCAB14VCCAB16VCCAB18VCCAB20VCCAB22VCCAC9VCCAC11VCCAC13VCCAC15VCCAC17VCCAC19VCCAD8VCCAD10VCCAD12VCCAD14VCCAD16VCCAD18VCCAE9VCCAE11VCCAE13VCCAE15VCCAE17VCCAE19VCCAF8VCCAF10VCCAF12VCCAF14VCCAF16VCCAF18
VSSM4VSSM5VSSM21VSSM24VSSN3VSSN6VSSN22VSSN23VSSN26VSSP2VSSP5VSSP21VSSP24VSSR1VSSR4VSSR6VSSR22VSSR25VSST3VSST5VSST21VSST23
VSS T26VSS U2VSS U6VSS U22VSS U24VSS V1VSS V4VSS V5VSS V21VSS V25VSS W3VSS W6VSS W22VSS W23VSS W26VSS Y2VSS Y5VSS Y21VSS Y24VSS AA1VSS AA4VSS AA6VSS AA8VSS AA10VSS AA12VSS AA14VSS AA16VSS AA18VSS AA20VSS AA22VSS AA25VSS AB3VSS AB5VSS AB7VSS AB9VSS AB11VSS AB13VSS AB15VSS AB17VSS AB19VSS AB21VSS AB23VSS AB26VSS AC2VSS AC5VSS AC8VSS AC10VSS AC12VSS AC14VSS AC16VSS AC18VSS AC21VSS AC24VSS AD1VSS AD4VSS AD7VSS AD9VSS AD11VSS AD13VSS AD15VSS AD17VSS AD19VSS AD22VSS AD25VSS AE3VSS AE6VSS AE8VSS AE10VSS AE12VSS AE14VSS AE16VSS AE18VSS AE20VSS AE23VSS AE26VSS AF2VSS AF5VSS AF9VSS AF11VSS AF13VSS AF15VSS AF17VSS AF19VSS AF21VSS AF24
R45
754
.9_0
603_
1%~D
12
R1472K_0603_1%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
CPU Bypass
9 51Monday, October 18, 2004
Compal Electronics, Inc.
10uF 0805 X6S -> 105 degree C High Frequence Decoupling
9mOhm7343PS CAP
9mOhm7343PS CAP
9mOhm7343PS CAP
ESR <= 3m ohmCapacitor > 880uF
Near VCORE regulator.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
9mOhm7343PS CAP
C43110U_0805_4VAM~D
@1
2
C10210U_0805_4VAM~D
1
2
C4510.1U_0402_10V7K~D
1
2
C42610U_0805_4VAM~D
1
2
C13710U_0805_4VAM~D
1
2
+
C49
733
0U_D
_2VM
~D@
1
2
C47210U_0805_4VAM~D
1
2
C43210U_0805_4VAM~D
1
2
C47010U_0805_4VAM~D
1
2
C14110U_0805_4VAM~D
1
2
C46710U_0805_4VAM~D
1
2
C44710U_0805_4VAM~D
1
2
C11810U_0805_4VAM~D
@1
2
C4740.1U_0402_10V7K~D
1
2
+
C35
433
0U_D
_2VM
~D
1
2
C42910U_0805_4VAM~D
1
2
C4620.1U_0402_10V7K~D
1
2
C4380.1U_0402_10V7K~D
1
2
C9910U_0805_4VAM~D
1
2
C10110U_0805_4VAM~D
1
2
C43010U_0805_4VAM~D
1
2
+
C35
233
0U_D
_2VM
~D@
1
2
C4150.1U_0402_10V7K~D
1
2
C12010U_0805_4VAM~D
1
2
C47110U_0805_4VAM~D
1
2
C4160.1U_0402_10V7K~D
1
2
C47310U_0805_4VAM~D
1
2
C46610U_0805_4VAM~D
1
2
C11710U_0805_4VAM~D
1
2
C46810U_0805_4VAM~D
1
2
C4570.1U_0402_10V7K~D
1
2
C14010U_0805_4VAM~D
1
2
C13910U_0805_4VAM~D
1
2
C13810U_0805_4VAM~D
1
2
C44610U_0805_4VAM~D
@1
2
C46910U_0805_4VAM~D
1
2
C10010U_0805_4VAM~D
1
2
+C455150U_D2_4VK~D
1
2
+
C49
633
0U_D
_2VM
~D
1
2
C9710U_0805_4VAM~D
1
2
C14210U_0805_4VAM~D
1
2
C4450.1U_0402_10V7K~D
1
2
C9810U_0805_4VAM~D
1
2
C42710U_0805_4VAM~D
1
2
C42810U_0805_4VAM~D
@1
2
C4390.1U_0402_10V7K~D
1
2
C4140.1U_0402_10V7K~D
1
2
C43310U_0805_4VAM~D
1
2
C11910U_0805_4VAM~D
@1
2
C44810U_0805_4VAM~D
@1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_SWNG1
H_A#6
H_A#31
H_A#28
H_A#14
H_A#24
H_A#4
H_A#22
H_A#8H_A#9
H_A#18
H_A#27
H_A#19
H_A#16
H_A#21
H_A#25
H_A#7
H_A#17
H_A#30
H_A#5
H_A#10
H_A#3
H_A#26
H_A#15
H_A#20
H_A#23
H_A#11
H_A#13
H_A#29
H_A#12
H_D#11
H_D#23
H_D#46
H_D#21
H_D#2
H_D#50
H_D#31
H_D#37
H_D#58
H_D#35
H_D#39
H_D#27
H_D#5
H_D#52
H_D#30
H_D#8
H_D#10
H_D#51
H_D#44
H_D#60
H_D#18
H_D#4
H_D#43
H_D#56
H_D#59
H_D#14
H_D#63
H_D#28
H_D#48
H_D#3
H_D#62
H_D#34
H_D#36
H_D#24
H_D#13
H_D#55
H_D#57
H_D#22
H_D#20
H_D#16
H_D#29
H_D#9
H_D#1H_D#0
H_D#53
H_D#17
H_D#26
H_D#45
H_D#33
H_D#40
H_D#7
H_D#47
H_D#41
H_D#25
H_D#38
H_D#15
H_D#54
H_D#61
H_D#49
H_D#42
H_D#6
H_D#32
H_D#12
H_D#19
PLTRST_R#
TP_H_EDRDY#
H_REQ#4
H_REQ#0
H_REQ#2H_REQ#1
H_REQ#3
H_ADSTB#1H_ADSTB#0
H_R_CPUSLP#
H_DRDY#
H_TRDY#
H_BR0#
H_ADS#
H_HIT#H_HITM#
H_LOCK#
H_BPRI#H_BNR#
H_DEFER#
H_DBSY#
H_RESET#
H_RS#2
H_RS#0H_RS#1
H_XSCOMP
H_YSCOMPH_YRCOMP
H_XRCOMP
H_SWNG0H_SWNG1
H_SWNG0
PM_EXTTS#0
PM_EXTTS#1
CFG19
DDR_CKE3_DIMMB
DDR_CKE1_DIMMADDR_CKE2_DIMMB
DDR_CKE0_DIMMA
M_CLK_DDR#0M_CLK_DDR#1
M_CLK_DDR#3M_CLK_DDR#4
TP_H_PCREQ#
SMRCOMPN
H_CPUSLP# H_R_CPUSLP#
CFG9
M_OCDOCMP0M_OCDOCMP1
M_OCDOCMP0M_OCDOCMP1
THERMTRIP_MCH#
H_VREF
H_DSTBP#1
DMI_TXP1
H_DSTBN#2
IMVP_PWRGD
H_DSTBP#3
DDR_CS3_DIMMB#
CFG12
M_CLK_DDR4
DMI_TXP2
H_DSTBP#2
CFG13
DDR_CS1_DIMMA#
DMI_TXP0
H_DSTBP#0
M_ODT0
M_ODT3
DMI_RXN2
DMI_RXN0
PM_EXTTS#1
CFG7
M_CLK_DDR3
DMI_RXN3
CFG0
DDR_CS0_DIMMA#
DMI_RXN1
CFG6
H_DSTBN#0
CFG18
M_CLK_DDR0
DMI_TXN3
M_ODT2
DMI_RXP2
DMI_RXP0
CFG5
MCH_CLKSEL0
M_CLK_DDR1
H_DSTBN#3
DDR_CS2_DIMMB#
DMI_TXN2
H_DSTBN#1
DMI_TXN0
CFG16
SMRCOMPP
M_ODT1
DMI_RXP3
DMI_TXN1 MCH_CLKSEL1
DMI_RXP1
DMI_TXP3
PM_EXTTS#0
+VCCP
+VCCP
+VCCP
+VCCP
+2.5VRUN
+1.8VSUS
+VCCP
H_A#[3..31]<7> H_D#[0..63] <7>
PM_BMBUSY# <23>
THERMTRIP_MCH# <15>IMVP_PWRGD <23,38,45>
H_REQ#[0..4]<7>
H_ADSTB#1<7>H_ADSTB#0<7>
H_TRDY#<7>
H_HITM#<7>H_HIT#<7>H_LOCK#<7>
H_DEFER#<7>
H_BPRI#<7>
H_BR0#<7>
H_RESET#<7>
H_DPWR#<7>
H_DINV#0<7>H_DINV#1<7>
H_DINV#3<7>H_DINV#2<7>
H_DRDY#<7>
H_DBSY#<7>
CLK_MCH_BCLK#<6>CLK_MCH_BCLK<6>
H_BNR#<7>
H_ADS#<7>
H_RS#[0..2]<7>
PLTRST# <21,23,25,34>
M_ODT0<16>M_ODT1<16>M_ODT2<17>M_ODT3<17>
DDR_CS2_DIMMB#<17>DDR_CS3_DIMMB#<17>
DDR_CS0_DIMMA#<16>DDR_CS1_DIMMA#<16>
DDR_CKE3_DIMMB<17>DDR_CKE2_DIMMB<17>
DDR_CKE0_DIMMA<16>DDR_CKE1_DIMMA<16>
M_CLK_DDR#0<16>M_CLK_DDR#1<16>
M_CLK_DDR#3<17>M_CLK_DDR#4<17>
M_CLK_DDR0<16>M_CLK_DDR1<16>
M_CLK_DDR3<17>M_CLK_DDR4<17>
DMI_RXP1<23>DMI_RXP0<23>
DMI_RXN0<23>DMI_RXN1<23>
DMI_TXP0<23>DMI_TXP1<23>
DMI_TXN0<23>DMI_TXN1<23>
V_DDR_MCH_REF<16,17,44>
H_CPUSLP#<7,22>
CFG5 <12>CFG6 <12>CFG7 <12>
CFG12 <12>CFG13 <12>
CFG16 <12>
CFG19 <12>CFG18 <12>
CFG0 <12>
CFG9 <12>
DMI_RXP3<23>DMI_RXP2<23>
DMI_RXN2<23>DMI_RXN3<23>
DMI_TXP2<23>DMI_TXP3<23>
DMI_TXN2<23>DMI_TXN3<23>
MCH_CLKSEL1 <6>MCH_CLKSEL0 <6>
DREFCLK# <6>DREFCLK <6>DREF_SSCLK <6,11>DREF_SSCLK# <6,11>
H_DSTBP#[0..3]<7>
H_DSTBN#[0..3]<7>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Alviso(1 of 5)
10 51Wednesday, November 03, 2004
Compal Electronics, Inc.
Layout Guidewill show thesesignals routeddifferentially.
Note:"Do not install R88 for Dothan-A,Install R88 for Dothan-B"
Note : CFG3:17 hasinternal pullup,CFG18:19 hasinternal pulldown
Layout Note:Rote as shortas possible
Layout Note:H_XRCOMP & H_YRCOMP trace widthand spacing is 10/20
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R64
221_
0603
_1%
~D
12
R43
740
.2_0
402_
1%~D
@
12
T35PAD~D@
R33610K_0402_5%~D
12
R441 100_0603_1%~D
1 2
R880_0402_5%~D 1 2
T32 PAD~D@
T33 PAD~D@
R57
24.9
_060
3_1%
~D 12
C65
0.1U
_040
2_16
V4Z~
D
1
2
C36
30.
1U_0
402_
16V4
Z~D
1
2
R33556_0402_5%~D
1 2
C48
0.1U
_040
2_16
V4Z~
D
1
2
R32
520
0_06
03_1
%~D
12
R65
100_
0603
_1%
~D
12
R25310K_0402_5%~D
12
R90
24.9
_060
3_1%
~D 12
R52
54.9
_060
3_1%
~D
12
R142
80.6_0603_1%~D 1 2
C43
52.
2U_0
805_
6.3V
6K~D
1
2
R32
610
0_06
03_1
%~D
12
DMI
DDR
MUXI
NG
CFG/
RSVD
PMCLK
NC
U4B
ALVISO-915PM-B0_BGA1257~D
DMIRXN0AA31DMIRXN1AB35
DMIRXP0Y31DMIRXP1AA35
DMITXN0AA33DMITXN1AB37
DMITXP0Y33DMITXP1AA37
SM_CK0AM33SM_CK1AL1SM_CK2AE11SM_CK3AJ34SM_CK4AF6SM_CK5AC10
SM_CK0#AN33SM_CK1#AK1SM_CK2#AE10SM_CK3#AJ33SM_CK4#AF5SM_CK5#AD10
SM_CKE0AP21SM_CKE1AM21SM_CKE2AH21SM_CKE3AK21
SM_CS0#AN16SM_CS1#AM14SM_CS2#AH15SM_CS3#AG16
SM_OCDCOMP0AF22SM_OCDCOMP1AF16SM_ODT0AP14SM_ODT1AL15SM_ODT2AM11SM_ODT3AN10
SMRCOMPNAK10SMRCOMPPAK11SMVREF0AF37SMVREF1AD1SMXSLEWINAE27SMXSLEWOUTAE28SMYSLEWINAF9SMYSLEWOUTAF10
CFG0 G16CFG1 H13CFG2 G14CFG3 F16CFG4 F15CFG5 G15CFG6 E16CFG7 D17CFG8 J16CFG9 D15
CFG10 E15CFG11 D14CFG12 E14CFG13 H12CFG14 C14CFG15 H15CFG16 J15CFG17 H14CFG18 G22CFG19 G23CFG20 D23
RSVD21 G25RSVD22 G24RSVD23 J17RSVD24 A31RSVD25 A30RSVD26 D26RSVD27 D25
BM_BUSY# J23EXT_TS0# J21EXT_TS1# H22
THRMTRIP# F5PWROK AD30RSTIN# AE29
DREF_CLKN A24DREF_CLKP A23
DREF_SSCLKN C37DREF_SSCLKP D37
NC1 AP37NC2 AN37NC3 AP36NC4 AP2NC5 AP1NC6 AN1NC7 B1NC8 A2NC9 B37
NC10 A36NC11 A37
DMITXN2AC33DMITXN3AD37
DMIRXN3AD35 DMIRXN2AC31
DMITXP2AB33DMITXP3AC37
DMIRXP2AB31DMIRXP3AC35
C42
50.
1U_0
402_
16V4
Z~D
1
2
HOST
AlvisoU4A
ALVISO-915PM-B0_BGA1257~D
HD0# E4HD1# E1HD2# F4HD3# H7HD4# E2HD5# F1HD6# E3HD7# D3HD8# K7HD9# F2
HD10# J7HD11# J8HD12# H6HD13# F3HD14# K8HD15# H5HD16# H1HD17# H2HD18# K5HD19# K6HD20# J4HD21# G3HD22# H3HD23# J1HD24# L5HD25# K4HD26# J5HD27# P7HD28# L7HD29# J3HD30# P5HD31# L3HD32# U7HD33# V6HD34# R6HD35# R5HD36# P3HD37# T8HD38# R7HD39# R8HD40# U8HD41# R4HD42# T4HD43# T5HD44# R1HD45# T3HD46# V8HD47# U6HD48# W6HD49# U3HD50# V5HD51# W8HD52# W7HD53# U2HD54# U1HD55# Y5HD56# Y2HD57# V4HD58# Y7HD59# W1HD60# W3HD61# Y3HD62# Y6HD63# W2
HA3#G9HA4#C9HA5#E9HA6#B7HA7#A10HA8#F9HA9#D8HA10#B10HA11#E10HA12#G10HA13#D9HA14#E11HA15#F10HA16#G11HA17#G13HA18#C10HA19#C11HA20#D11HA21#C12HA22#B13HA23#A12HA24#F12HA25#G12HA26#E12HA27#C13HA28#B11HA29#D13HA30#A13HA31#F13
HREQ#0A7HREQ#1D7HREQ#2B8HREQ#3C7HREQ#4A8HADSTB#0B9HADSTB#1E13
HPCREQ#A11
HCLKNAB1HCLKPAB2
HVREF J11HXRCOMP C1HXSCOMP C2HYRCOMP T1HYSCOMP L1
HYSWING P1HXSWING D1
HDSTBN#0G4HDSTBN#1K1HDSTBN#2R3HDSTBN#3V3HDSTBP#0G5HDSTBP#1K2HDSTBP#2R2HDSTBP#3W4HDINV#0H8HDINV#1K3HDINV#2T7HDINV#3U5
HCPURST#H10
HADS#F8HTRDY#B5HDPWR#G6HDRDY#F7HDEFER#E6HEDRDY#F6HHITM#D6HHIT#D4HLOCK#B3HBREQ0#E7HBNR#A5HBPRI#D5HDBSY#C6HCPUSLP#G8HRS0#A4HRS1#C5HRS2#B4
R80
54.9
_060
3_1%
~D
12
R43
540
.2_0
402_
1%~D
@1
2
R14180.6_0603_1%~D
12
R85
221_
0603
_1%
~D
12
T34PAD~D@
R86
100_
0603
_1%
~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D5
DDR_A_D0
DDR_A_D3
DDR_A_D10
DDR_A_D4
DDR_A_D1
DDR_A_D11
DDR_A_D2
DDR_A_D8
DDR_A_D6
DDR_A_D9
DDR_A_D7
DDR_A_DM5
DDR_A_BS#0DDR_A_BS#1
DDR_A_DQS0
DDR_A_D17
DDR_A_D12DDR_A_D13
DDR_A_D16
DDR_A_D22
DDR_A_D15
DDR_A_D23
DDR_A_D20
DDR_A_D14
DDR_A_D21
DDR_A_D18DDR_A_D19
DDR_A_D29
DDR_A_D24DDR_A_D25
DDR_A_D28
DDR_A_D34
DDR_A_D27
DDR_A_D35
DDR_A_D32
DDR_A_D26
DDR_A_D33
DDR_A_D30DDR_A_D31
DDR_A_D44
DDR_A_D47
DDR_A_D39
DDR_A_D46
DDR_A_D40
DDR_A_D37DDR_A_D36
DDR_A_D41
DDR_A_D43DDR_A_D42
DDR_A_D45
DDR_A_D38
DDR_A_D53
DDR_A_D48DDR_A_D49
DDR_A_D52
DDR_A_D58
DDR_A_D51
DDR_A_D59
DDR_A_D56
DDR_A_D50
DDR_A_D57
DDR_A_D54DDR_A_D55
DDR_A_D63
DDR_A_D61DDR_A_D60
DDR_A_D62
DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3DDR_A_MA4DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9DDR_A_MA10DDR_A_MA11DDR_A_MA12DDR_A_MA13
DDR_A_BS#2
DDR_A_DM0DDR_A_DM1
DDR_A_DM3DDR_A_DM4
DDR_A_DM2
DDR_A_DM7DDR_A_DM6
DDR_A_DQS1DDR_A_DQS2DDR_A_DQS3DDR_A_DQS4DDR_A_DQS5DDR_A_DQS6DDR_A_DQS7
DDR_A_CAS#DDR_A_RAS#
DDR_A_WE#
DDR_A_DQS#0DDR_A_DQS#1DDR_A_DQS#2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS#5DDR_A_DQS#6DDR_A_DQS#7
DDR_B_D11
DDR_B_D57
DDR_B_D46
DDR_B_D7
DDR_B_D0
DDR_B_D44
DDR_B_D40
DDR_B_D30
DDR_B_D27
DDR_B_D15
DDR_B_D3
DDR_B_D35
DDR_B_D25
DDR_B_D23
DDR_B_D49
DDR_B_D37
DDR_B_D19
DDR_B_D48DDR_B_D47
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D62
DDR_B_D60
DDR_B_D9
DDR_B_D2
DDR_B_D52
DDR_B_D50
DDR_B_D22
DDR_B_D56
DDR_B_D51
DDR_B_D39
DDR_B_D28
DDR_B_D17
DDR_B_BS#0
DDR_B_D45
DDR_B_D6
DDR_B_D61
DDR_B_D58
DDR_B_BS#1 DDR_B_D1
DDR_B_D54
DDR_B_D41
DDR_B_D31
DDR_B_D12
DDR_B_D5
DDR_B_D38
DDR_B_D32
DDR_B_D20
DDR_B_D16
DDR_B_D14
DDR_B_D33
DDR_B_D63
DDR_B_D59
DDR_B_D42
DDR_B_D55
DDR_B_D53
DDR_B_D43
DDR_B_D29
DDR_B_D26
DDR_B_D13
DDR_B_D4
DDR_B_BS#2
DDR_B_D34
DDR_B_D24
DDR_B_D21
DDR_B_D10
DDR_B_DQS#4DDR_B_DQS#5
DDR_B_DQS0
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_B_DM1
DDR_B_DQS#6DDR_B_DQS#7
DDR_B_DQS1DDR_B_DQS2DDR_B_DQS3DDR_B_DQS4DDR_B_DQS5DDR_B_DQS6DDR_B_DQS7
DDR_B_DQS#0
DDR_B_MA0
DDR_B_MA5
DDR_B_MA3DDR_B_MA2
DDR_B_MA7
DDR_B_MA1
DDR_B_MA6
DDR_B_MA4
DDR_B_MA12
DDR_B_MA9DDR_B_MA8
DDR_B_MA10DDR_B_MA11
DDR_B_MA13
DDR_B_DQS#1DDR_B_DQS#2DDR_B_DQS#3
DDR_B_DM6DDR_B_DM7
DDR_B_DM2
DDR_B_DM4DDR_B_DM5
DDR_B_DM3
DDR_B_DM0
CLK_SSC_IN
SSC_S3
SSC_S1SSC_S2
DREFSSCLK#DREFSSCLK
SSC_S2
SSC_S3
SSC_S1
CLK_ENABLE#
CLK_SCLKCLK_SDATA
DREF_SSCLK#
DREF_SSCLK
+3VRUN
+3VRUN
+3VRUN
DDR_B_D[0..63] <17>DDR_A_D[0..63] <16>DDR_A_BS#0<16>DDR_A_BS#1<16>
DDR_A_DQS[0..7]<16>
DDR_A_MA[0..13]<16>
DDR_A_BS#2<16>
DDR_B_BS#0<17>DDR_B_BS#1<17>DDR_B_BS#2<17>
DDR_A_WE#<16>
DDR_A_CAS#<16>DDR_A_RAS#<16>
DDR_A_DQS#[0..7]<16>
DDR_A_DM[0..7]<16>
DDR_B_DQS[0..7]<17>
DDR_B_CAS#<17>DDR_B_RAS#<17>
DDR_B_MA[0..13]<17>
DDR_B_DQS#[0..7]<17>
DDR_B_WE#<17>
DDR_B_DM[0..7]<17>
DREF_SSCLK <6,10>DREF_SSCLK# <6,10>
CLK_SSC_IN<6>
CLK_ENABLE#<6,45>
CLK_SCLK<6,16,17>CLK_SDATA<6,16,17>
REFOUT_14M
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Alviso(2 of 5)
11 51Monday, October 18, 2004
Compal Electronics, Inc.
This Symbol as sameas Intel CRBschematic, So LayoutGuide will show thesesignals routeddifferentially.
This Symbol as sameas Intel CRBschematic, So LayoutGuide will show thesesignals routeddifferentially.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R389 33_0402_5%~D@
1 2
R38849.9_0402_1%~D
@
1 2R395475_0603_1%~D
@
12
R29
110
K_04
02_5
%~D
@ 12
U18
@CY25823
CLKIN1
SSC_S32
PWRDWN5
SDATA8
REFOUT/SEL6
VDDA 16
SSC_S14 SSC_S23
SCLOCK7
VDD 9
VSS 10
CLKOUT# 11CLKOUT 12
VSSIREF 13
VSSA 15
IREF 14
R38449.9_0402_1%~D
@1 2
R29
010
K_04
02_5
%~D
@
12
DDR MEMORY SYSTEM A
U4C
ALVISO-915PM-B0_BGA1257~D
SADQ0 AG35SADQ1 AH35SADQ2 AL35SADQ3 AL37SADQ4 AH36SADQ5 AJ35SADQ6 AK37SADQ7 AL34SADQ8 AM36SADQ9 AN35
SADQ10 AP32SADQ11 AM31SADQ12 AM34SADQ13 AM35SADQ14 AL32SADQ15 AM32SADQ16 AN31SADQ17 AP31SADQ18 AN28SADQ19 AP28SADQ20 AL30SADQ21 AM30SADQ22 AM28SADQ23 AL28SADQ24 AP27SADQ25 AM27SADQ26 AM23SADQ27 AM22SADQ28 AL23SADQ29 AM24SADQ30 AN22SADQ31 AP22SADQ32 AM9SADQ33 AL9SADQ34 AL6SADQ35 AP7SADQ36 AP11SADQ37 AP10SADQ38 AL7SADQ39 AM7SADQ40 AN5SADQ41 AN6SADQ42 AN3SADQ43 AP3SADQ44 AP6SADQ45 AM6SADQ46 AL4SADQ47 AM3SADQ48 AK2SADQ49 AK3SADQ50 AG2SADQ51 AG1SADQ52 AL3SADQ53 AM2SADQ54 AH3SADQ55 AG3SADQ56 AF3SADQ57 AE3SADQ58 AD6SADQ59 AC4SADQ60 AF2SADQ61 AF1SADQ62 AD4SADQ63 AD5
SA_BS0#AK15SA_BS1#AK16SA_BS2#AL21
SA_DM0AJ37SA_DM1AP35SA_DM2AL29SA_DM3AP24SA_DM4AP9SA_DM5AP4SA_DM6AJ2SA_DM7AD3
SA_DQS0AK36SA_DQS1AP33SA_DQS2AN29SA_DQS3AP23SA_DQS4AM8SA_DQS5AM4SA_DQS6AJ1SA_DQS7AE5
SA_DQS0#AK35SA_DQS1#AP34SA_DQS2#AN30SA_DQS3#AN23SA_DQS4#AN8SA_DQS5#AM5SA_DQS6#AH1SA_DQS7#AE4
SA_MA0AL17SA_MA1AP17SA_MA2AP18SA_MA3AM17SA_MA4AN18SA_MA5AM18SA_MA6AL19SA_MA7AP20SA_MA8AM19SA_MA9AL20SA_MA10AM16SA_MA11AN20SA_MA12AM20SA_MA13AM15
SA_CAS#AN15SA_RAS#AP16SA_RCVENIN#AF29SA_RCVENOUT#AF28SA_WE#AP15
DDR SYSTEM MEMORY B
U4D
ALVISO-915PM-B0_BGA1257~D
SBDQ0 AE31SBDQ1 AE32SBDQ2 AG32SBDQ3 AG36SBDQ4 AE34SBDQ5 AE33SBDQ6 AF31SBDQ7 AF30SBDQ8 AH33SBDQ9 AH32
SBDQ10 AK31SBDQ11 AG30SBDQ12 AG34SBDQ13 AG33SBDQ14 AH31SBDQ15 AJ31SBDQ16 AK30SBDQ17 AJ30SBDQ18 AH29SBDQ19 AH28SBDQ20 AK29SBDQ21 AH30SBDQ22 AH27SBDQ23 AG28SBDQ24 AF24SBDQ25 AG23SBDQ26 AJ22SBDQ27 AK22SBDQ28 AH24SBDQ29 AH23SBDQ30 AG22SBDQ31 AJ21SBDQ32 AG10SBDQ33 AG9SBDQ34 AG8SBDQ35 AH8SBDQ36 AH11SBDQ37 AH10SBDQ38 AJ9SBDQ39 AK9SBDQ40 AJ7SBDQ41 AK6SBDQ42 AJ4SBDQ43 AH5SBDQ44 AK8SBDQ45 AJ8SBDQ46 AJ5
SB_BS0#AJ15SB_BS1#AG17SB_BS2#AG21
SBDQ47 AK4SBDQ48 AG5SBDQ49 AG4SBDQ50 AD8SBDQ51 AD9SBDQ52 AH4SBDQ53 AG6SBDQ54 AE8SBDQ55 AD7SBDQ56 AC5SBDQ57 AB8SBDQ58 AB6SBDQ59 AA8SBDQ60 AC8SBDQ61 AC7SBDQ62 AA4SBDQ63 AA5
SB_CAS#AH14SB_RAS#AK14SB_RCVENIN#AF15SB_RCVENOUT#AF14SB_WE#AH16
SB_MA0AH17SB_MA1AK17SB_MA2AH18SB_MA3AJ18SB_MA4AK18SB_MA5AJ19SB_MA6AK19SB_MA7AH19SB_MA8AJ20SB_MA9AH20SB_MA10AJ16SB_MA11AG18SB_MA12AG20SB_MA13AG15
SB_DQS0#AF35SB_DQS1#AK33SB_DQS2#AK28SB_DQS3#AJ23SB_DQS4#AL10SB_DQS5#AH7SB_DQS6#AF7SB_DQS7#AB5
SB_DQS0AF34SB_DQS1AK32SB_DQS2AJ28SB_DQS3AK23SB_DQS4AM10SB_DQS5AH6SB_DQS6AF8SB_DQS7AB4
SB_DM0AF32SB_DM1AK34SB_DM2AK27SB_DM3AK24SB_DM4AJ10SB_DM5AK5SB_DM6AE7SB_DM7AB7
R29
210
K_04
02_5
%~D
@ 12
C3850.1U_0402_16V4Z~D@
1
2
R289
33_0402_5%~D@
1 2
R31
010
K_04
02_5
%~D
@12
R31
310
K_04
02_5
%~D
@
12
R390 33_0402_5%~D@
1 2
R31
110
K_04
02_5
%~D
@ 12
R31
210
K_04
02_5
%~D
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_RXP14
PEG_RXP12
PEG_RXP2
PEG_TXP11
PEG_TXN14PEG_TXN13
PEG_TXN9
PEG_TXN3
PEG_RXP13
PEG_RXN13
PEG_RXN6
L_IBG
PEG_TXP9
PEG_TXP3
PEG_RXP5
PEG_RXN15
PEG_RXN2
LDDC_CLK
G_DAT_DDC2 PEG_RXP[0..15]
PEG_RXP8
PEG_RXP3
PEG_TXN[0..15]
PEG_TXP4
PEG_TXN12PEG_TXN11
PEG_TXN1
PEG_RXN7TVIREF
PEG_TXP1
PEG_TXN7
PEG_RXN0
PEG_TXP13
PEG_RXN1
PEGCOMP
PEG_TXP7
PEG_RXP9
PEG_RXN14
PEG_TXP15
PEG_TXP5
PEG_TXN8
PEG_TXN4
PEG_TXN0
PEG_RXP7
PEG_RXN5
G_CLK_DDC2
SDVO_CTRLDATA
PEG_TXP[0..15]PEG_TXP0
PEG_TXN6
PEG_RXP1
PEG_TXP12
PEG_TXP6
PEG_RXP0
PEG_RXN11
LCTLA_CLK
PEG_RXP11
PEG_RXN10
PEG_RXN[0..15]
PEG_TXN5
PEG_RXP10
PEG_RXP6
PEG_RXN4
PEG_TXP10
PEG_TXN15
PEG_TXN10
PEG_TXN2
PEG_RXP15
PEG_RXN12
PEG_RXN8
PANEL_BKEN
PEG_TXP8
PEG_TXP2
PEG_RXN9
PEG_TXP14
PEG_RXP4
PEG_RXN3
LDDC_DATA
LCTLB_DATA
PANEL_BKEN
BIA_PWM_MCH
LCD_DDCCLK
LCD_DDCDATA
LCD_DDCDATA
SDVO_CTRLDATA
LCD_DDCCLK
INT_DAT_DDC2
INT_CLK_DDC2
LDDC_DATA
LDDC_CLK
LCTLA_CLK
LCTLB_DATAG_DAT_DDC2
G_CLK_DDC2
INTCRT_R
INTCRT_G
INTCRT_B
BIA_PWM_MCH
+1.5VRUN_PCIE
+3VRUN
+2.5VRUN
+VCCP
+2.5VRUN
+2.5VRUN
+2.5VRUN
+2.5VRUN
+2.5VRUN
+2.5VRUN
PEG_RXN[0..15] <18>
PEG_RXP[0..15] <18>
PEG_TXN[0..15] <18>
PEG_TXP[0..15] <18>
ENVDD<19>
COMP/B<18>Y/G<18>C/R<18>
CLK_MCH_3GPLL<6>CLK_MCH_3GPLL#<6>
INTCRT_B<18>
INTCRT_G<18>
INTCRT_R<18>
LCD_B2+<19>LCD_B1+<19>LCD_B0+<19>
LCD_B2-<19>LCD_B1-<19>LCD_B0-<19>
LCD_A2+<19>LCD_A1+<19>LCD_A0+<19>
LCD_A2-<19>LCD_A1-<19>LCD_A0-<19>
LCD_BCLK+<19>LCD_BCLK-<19>LCD_ACLK+<19>LCD_ACLK-<19>
PANEL_BKEN<19>
CFG5<10>
CFG7<10>
CFG12<10>
CFG13<10>
CFG16<10>
CFG18<10>CFG19<10>
LCD_DDCDATA <19>
LCD_DDCCLK <19>
CFG9<10>
CFG0<10>
INT_HSYNC<18>INT_VSYNC<18>
CFG6<10>
INT_DAT_DDC2 <18>
INT_CLK_DDC2 <18>
BIA_PWM<18,35>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Alviso(3 of 5)
12 51Monday, October 18, 2004
Compal Electronics, Inc.
This Symbol as sameas Intel CRBschematic, So LayoutGuide will show thesesignals routeddifferentially.
CFG[18:19] have internal pulldown
*
*
*
CFG18 (VCC Select)
*
*
*
Low = DMI x 2
CFG7
High = DMI x 4
CFG5
Low = DT/Transportable CPU
High = Mobile CPU
CFG[13:12] CFG[3:17] have internal pullup
CFG16(FSB DynamicODT)
Low = 1.05V (Default)
00 = Reserved01 = XOR Mode Enabled10 = All Z Mode Enabled11 = Normal Operation
High = 1.2V
Low = 1.05V (Default)
High = 1.5V
High = Enabled
Low = Disabled
Low = Reverse LaneCFG9
High = Normal Operation *
CFG19 (VTT Select)
SDVO_CTRLDATALow = No SDVO Device Present
High = SDVO Device Present
(Default)
(Default)
Have internal pulldown
*
*CFG6Low = DDR-II
High = DDR-I
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Strap Table
R24
22.
2K_0
402_
5%~D
1@
12
R2511.5K_0603_1%~D1@
12
R306 1K_0402_5%~D@1 2
G
DS
Q33BSS138_SOT23~D
1@
2
13
R5330_0402_5%~D
1@
12
R34
2.2K
_040
2_5%
~D
1@
12
R23
150_
0603
_1%
~D12
R288 2.2K_0402_5%~D @1 2
MISC
TV
VGA
LVDS
PCI - EXPRESS GRAPHICS
U4G
ALVISO-915PM-B0_BGA1257~D
SDVOCTRL_DATAH24SDVOCTRL_CLKH25GCLKNAB29GCLKPAC29
TVDAC_AA15TVDAC_BC16TVDAC_CA17TV_REFSETJ18TV_IRTNAB15TV_IRTNBB16TV_IRTNCB17
GREEN#B20
HSYNCG21
DDCCLKE24DDCDATAE23BLUEE21BLUE#D21GREENC20
REDA19RED#B19VSYNCH21
REFSETJ20
LDDC_CLKF23
LBKLT_CTLE25LBKLT_ENF25LCTLA_CLKC23LCTLB_DATAC22
LDDC_DATAF22LVDD_ENF26LIBGC33LVBGC31LVREFHF28LVREFLF27
LACLKNB30LACLKPB29LBCLKNC25LBCLKPC24
LADATAN0B34LADATAN1B33LADATAN2B32
LADATAP0A34LADATAP1A33LADATAP2B31
LBDATAN0C29LBDATAN1D28LBDATAN2C27
LBDATAP2C26
EXP_COMPI D36EXP_ICOMPO D34
EXP_RXN0 E30EXP_RXN1 F34EXP_RXN2 G30EXP_RXN3 H34EXP_RXN4 J30EXP_RXN5 K34EXP_RXN6 L30EXP_RXN7 M34EXP_RXN8 N30EXP_RXN9 P34
EXP_RXN10 R30EXP_RXN11 T34EXP_RXN12 U30EXP_RXN13 V34EXP_RXN14 W30EXP_RXN15 Y34
EXP_RXP0 D30EXP_RXP1 E34EXP_RXP2 F30EXP_RXP3 G34EXP_RXP4 H30EXP_RXP5 J34EXP_RXP6 K30EXP_RXP7 L34EXP_RXP8 M30EXP_RXP9 N34
EXP_RXP10 P30EXP_RXP11 R34EXP_RXP12 T30EXP_RXP13 U34EXP_RXP14 V30EXP_RXP15 W34
EXP_TXN0 E32EXP_TXN1 F36EXP_TXN2 G32EXP_TXN3 H36EXP_TXN4 J32EXP_TXN5 K36EXP_TXN6 L32EXP_TXN7 M36EXP_TXN8 N32EXP_TXN9 P36
EXP_TXN10 R32EXP_TXN11 T36EXP_TXN12 U32EXP_TXN13 V36EXP_TXN14 W32EXP_TXN15 Y36
EXP_TXP0 D32EXP_TXP1 E36EXP_TXP2 F32EXP_TXP3 G36EXP_TXP4 H32EXP_TXP5 J36EXP_TXP6 K32EXP_TXP7 L36EXP_TXP8 M32EXP_TXP9 N36
EXP_TXP10 P32EXP_TXP11 R36EXP_TXP12 T32EXP_TXP13 U36EXP_TXP14 V32EXP_TXP15 W36LBDATAP0C28
LBDATAP1D27
R279 2.2K_0402_5%~D
1@ 1 2
R31
4
4.99
K_06
03_1
%~D
12
R247 2.2K_0402_5%~D
1@ 1 2
R299 2.2K_0402_5%~D
1 2
R282 2.2K_0402_5%~D @ 1 2
R323 2.2K_0402_5%~D @ 1 2
R283 2.2K_0402_5%~D
1@ 1 2
R307 2.2K_0402_5%~D@1 2
R25
150_
0603
_1%
~D12
R334 1K_0402_5%~D@1 2
R346 2.2K_0402_5%~D @1 2
R284255_0603_1%~D
1@12
R24
150_
0603
_1%
~D12
R37 2.2K_0402_5%~D
1@ 1 2
R333 10K_0402_5%~D12
R285 100K_0402_5%~D
@1 2
G
DS
Q7BSS138_SOT23~D1@
2
13
R260 150_0603_1%~D
1 2
R300 100K_0402_5%~D
@1 2
R28724.9_0603_1%~D 1 2
R308 1K_0402_5%~D@
1 2
G
DS
Q31BSS138_SOT23~D
1@
2
13
R23
22.
2K_0
402_
5%~D
1@
12
R295 150_0603_1%~D
1 2
R281 2.2K_0402_5%~D @1 2
R22
92.
2K_0
402_
5%~D
1@
12
G
DS
Q27BSS138_SOT23~D1@
2
13
R261 150_0603_1%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3GRLL_R
VSSA_TVBG
+2.5VRUN_CRT
VCC_SYNC
VCC_SYNC
+2.5VRUN_CRT
VSSA_TVBG
V1.8_DDR_CAP1
V1.8_DDR_CAP6
V1.8_DDR_CAP3V1.8_DDR_CAP4
V1.8_DDR_CAP5V1.8_DDR_CAP2
+1.5VRUN
+1.5VRUN_DPLLA+1.5VRUN_DPLLB
+1.5VRUN+1.5VRUN_DDRDLL
+1.5VRUN+1.5VRUN_PCIE
+1.5VRUN+1.5VRUN_3GPLL
+2.5VRUN+2.5VRUN_3GBG
+VCCP
+1.8VSUS
+2.5VRUN
+1.5VRUN_MPLL
+1.5VRUN
+1.5VRUN_MPLL
+1.5VRUN_HPLL
+1.5VRUN
+1.5VRUN_HPLL
+1.5VRUN
+1.5VRUN_DPLLB
+1.5VRUN
+1.5VRUN_DPLLA
+3VRUN+3VRUN_TVDACA+1.5VRUN+1.5VRUN_QTVDAC
+3VRUN_TVDACB +3VRUN
+3VRUN_TVDACC
+3VRUN_TVDACA
+3VRUN_TVDACB
+2.5VRUN
+1.5VRUN_QTVDAC
+3VRUN+3VRUN_TVDACC
+3VRUN+3VRUN_ATVBG
+3VRUN_ATVBG
+1.5VRUN_TVDAC
+1.5VRUN_TVDAC +1.5VRUN
+1.5VRUN_DLVDS
+1.5VRUN_DLVDS +1.5VRUN
+2.5VRUN_ALVDS
+2.5VRUN_ALVDS +2.5VRUN
+2.5VRUN+2.5VRUN_TXLVDS
+2.5VRUN_TXLVDS
+VCCP
+2.5VRUN+3VRUN
+1.5VRUN+VCCP
+VCCP
+VCCP
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Alviso(4 of 5)
13 51Monday, October 18, 2004
Compal Electronics, Inc.
Route VSSA3GBG gnd from GMCH todecoupling cap ground lead andthen connect to the gnd plane.
Note : All VCCSM pinshorted internally.
CRTDAC: Route caps within250mil of Alviso. Route FBwithin 3" of Alviso.
Route VSSACRTDAC gnd from GMCH todecoupling cap ground lead and thenconnect to the gnd plane.
Note : C294, C335 No stuff for Ext. VGA. Stuff for Int. VGA.
Route VSSA_TVBG GND from GMCH todecoupling cap ground lead and thenconnect to the GND plane.
W=30 mils
CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Note : R370, R357 stuff and R347, L37 no stuff for Ext. VGA.R370, R357 no stuff and R347, L37 stuff for Int. VGA.
C35, C36, C37, C304, C305, C306, C357replace by 0 ohm 0805 resistor
C29
80.
1U_0
402_
16V4
Z~D
1
2
C33
10.
1U_0
402_
16V4
Z~D
1
2
POWER
U4F
ALVISO-915PM-B0_BGA1257~D
VTT0K13VTT1J13VTT2K12VTT3W11VTT4V11VTT5U11VTT6T11VTT7R11VTT8P11VTT9N11VTT10M11VTT11L11VTT12K11VTT13W10VTT14V10VTT15U10VTT16T10VTT17R10VTT18P10VTT19N10VTT20M10VTT21K10VTT22J10VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51G1
VCCSM0 AM37VCCSM1 AH37VCCSM2 AP29VCCSM3 AD28VCCSM4 AD27VCCSM5 AC27VCCSM6 AP26VCCSM7 AN26VCCSM8 AM26VCCSM9 AL26
VCCSM10 AK26VCCSM11 AJ26VCCSM12 AH26VCCSM13 AG26VCCSM14 AF26VCCSM15 AE26VCCSM16 AP25VCCSM17 AN25VCCSM18 AM25VCCSM19 AL25VCCSM20 AK25VCCSM21 AJ25VCCSM22 AH25VCCSM23 AG25VCCSM24 AF25VCCSM25 AE25VCCSM26 AE24VCCSM27 AE23VCCSM28 AE22VCCSM29 AE21VCCSM30 AE20VCCSM31 AE19VCCSM32 AE18VCCSM33 AE17VCCSM34 AE16VCCSM35 AE15VCCSM36 AE14VCCSM37 AP13VCCSM38 AN13VCCSM39 AM13VCCSM40 AL13VCCSM41 AK13VCCSM42 AJ13VCCSM43 AH13VCCSM44 AG13VCCSM45 AF13VCCSM46 AE13VCCSM47 AP12VCCSM48 AN12VCCSM49 AM12VCCSM50 AL12VCCSM51 AK12VCCSM52 AJ12VCCSM53 AH12VCCSM54 AG12VCCSM55 AF12VCCSM56 AE12VCCSM57 AD11VCCSM58 AC11VCCSM59 AB11VCCSM60 AB10VCCSM61 AB9VCCSM62 AP8VCCSM63 AM1VCCSM64 AE1
C36
22n_
0805
_25V
1 2
3
C32
00.
1U_0
402_
16V4
Z~D
1@
1
2
R1210_0402_5%~D1@
1 2
C32
50.
01U
_040
2_16
V7K~
D
1
2
C53
10U
_080
5_4V
AM~D
1
2
C41
80.
1U_0
402_
16V4
Z~D
1
2
C30
622
n_08
05_2
5V
1 2
3
C59
8
4.7U
_080
5_10
V4Z~
D
1@
1
2
L26BLM18PG181SN1_0603~D
12
C29
90.
1U_0
402_
16V4
Z~D
1
2
L24
BLM18PG181SN1_0603~D
12
POWER
U4E
ALVISO-915PM-B0_BGA1257~D
VCC0T29VCC1R29VCC2N29VCC3M29VCC4K29VCC5J29VCC6V28VCC7U28VCC8T28VCC9R28VCC10P28VCC11N28VCC12M28VCC13L28VCC14K28VCC15J28VCC16H28VCC17G28VCC18V27VCC19U27VCC20T27VCC21R27VCC22P27VCC23N27VCC24M27VCC25L27VCC26K27VCC27J27VCC28H27VCC29K26VCC30H26VCC31K25VCC32J25VCC33K24VCC34K23VCC35K22VCC36K21VCC37W20VCC38U20VCC39T20VCC40K20VCC41V19VCC42U19VCC43K19VCC44W18VCC45V18VCC46T18VCC47K18VCC48K17
VCCD_HMPLL2AC2VCCA_DPLLAB23VCCA_DPLLBC35VCCA_HPLLAA1VCCA_MPLLAA2
VCCA_TVDACA0 F17VCCA_TVDACA1 E17VCCA_TVDACB0 D18VCCA_TVDACB1 C18VCCA_TVDACC0 F18VCCA_TVDACC1 E18
VCCA_TVBG H18VSSA_TVBG G18
VCCD_TVDAC D19VCCDQ_TVDAC H17
VCCD_LVDS0 B26VCCD_LVDS1 B25VCCD_LVDS2 A25
VCCA_LVDS A35
VCCHV0 B22VCCHV1 B21VCCHV2 A21
VCCTX_LVDS0 B28VCCTX_LVDS1 A28VCCTX_LVDS2 A27
VCCA_SM0 AF20VCCA_SM1 AP19VCCA_SM2 AF19VCCA_SM3 AF18
VCC3G0 AE37VCC3G1 W37VCC3G2 U37VCC3G3 R37VCC3G4 N37VCC3G5 L37VCC3G6 J37
VCCA_3GPLL0 Y29VCCA_3GPLL1 Y28VCCA_3GPLL2 Y27
VCCA_3GBG F37VSSA_3GBG G37
VCC_SYNC H20
VCCA_CRTDAC0 F19VCCA_CRTDAC1 E19
VSSA_CRTDAC G19
VCCD_HMPLL1AC1
L35BLM21PG600SN1D_0805~D
12
C32
30.
1U_0
402_
16V4
Z~D
1
2
C41
30.
1U_0
402_
16V4
Z~D
1
2
C30
210
U_0
805_
4VAM
~D1@
1
2
R252
0_0402_5%~D
12
C23
0.1U
_040
2_16
V4Z~
D
1
2
+
C33
522
0U_D
2_4V
M_R
45~D
1@
1
2
L9BLM18PG181SN1_0603~D
12
C46
50.
1U_0
402_
16V4
Z~D1
2
+
C49
220U
_D2_
4VM
_R45
~D
1
2
C35
80.
1U_0
402_
16V4
Z~D
1
2
D8MMBD4148_SOT23~D1@
1
3
2
+
C29
422
0U_D
2_4V
M_R
45~D
1@
1
2
C46
00.
1U_0
402_
16V4
Z~D1
2
C31
80.
01U
_040
2_16
V7K~
D
1
2
R3470_0402_5%~D
1@
1 2
C39
02.
2U_0
805_
6.3V
6K~D
1
2
C54
0.22
U_0
402_
10V4
Z~D 1
2
+
C16
410
0U_D
_6.3
VM~D
1
2
C36
40.
1U_0
402_
16V4
Z~D
1
2
C36
610
U_0
805_
4VAM
~D
1
2
C29
30.
022U
_040
2_16
V7K~
D
1
2
L18BLM21PG600SN1D_0805~D
12
C38
30.
1U_0
402_
16V4
Z~D
1
2
L37 BLM11A601S_0603~D 1@1 2
D14MMBD4148_SOT23~D1@
1
3
2
C33
60.
1U_0
402_
16V4
Z~D
1
2
L11BLM18PG181SN1_0603~D
12
C3450.1U_0402_16V4Z~D
1
2
L3810U_MLZ2012E100PTAIN_60mA_25%_0805~D
1 2
C30
422
n_08
05_2
5V
1 2
3
C45
00.
1U_0
402_
16V4
Z~D1
2
C16
80.
1U_0
402_
16V4
Z~D
1
2
C36
710
U_0
805_
4VAM
~D
1
2
L2810U_MLZ2012E100PTAIN_60mA_25%_0805~D
1 2
C32
20.
1U_0
402_
16V4
Z~D
1
2
C37
90.
1U_0
402_
16V4
Z~D
1
2
C44
10.
1U_0
402_
16V4
Z~D
1
2
C37
22n_
0805
_25V
1 2
3
+
C41
915
0U_D
2_2V
M_R
15~D
1
2
C31
60.
47U
_060
3_16
V4Z~
D
1
2
C35
722
n_08
05_2
5V
1 2
3
C43
70.
1U_0
402_
16V4
Z~D1
2
C40
40.
1U_0
402_
16V4
Z~D
1
2
C46
30.
1U_0
402_
16V4
Z~D1
2
+
C16
533
0U_D
2E_2
.5VM
~D@
1
2
C30
522
n_08
05_2
5V
1 2
3
C35
22n_
0805
_25V
1 2
3
L3310U_MLZ2012E100PTAIN_60mA_25%_0805~D
1 2
C31
010
U_0
805_
4VAM
~D
1
2
C36
810
U_0
805_
4VAM
~D
1
2
L10BLM18PG181SN1_0603~D
12
L3910U_MLZ2012E100PTAIN_60mA_25%_0805~D
1 2
L25BLM18PG181SN1_0603~D
12
C45
0.47
U_0
603_
16V4
Z~D1
2
L34BLM21PG600SN1D_0805~D
12
R3570_0402_5%~D
2@
1 2
C3510.1U_0402_16V4Z~D
1
2
L36BLM11A601S_0603~D
12
C31
44.
7U_0
805_
10V4
Z~D
1
2
C81
0.22
U_0
402_
10V4
Z~D 1
2
C24
0.1U
_040
2_16
V4Z~
D
1
2
C59
10U
_080
5_4V
AM~D
1
2
C29
70.
1U_0
402_
16V4
Z~D
1
2
L31
BLM11A601S_0603~D
12
C15
810
U_0
805_
4VAM
~D
1
2
C22
0.1U
_040
2_16
V4Z~
D
1
2
C29
10.
1U_0
402_
16V4
Z~D
1
2
R3700_0402_5%~D
2@
1 2
C31
110
U_0
805_
4VAM
~D
1
2
C16
010
U_0
805_
4VAM
~D
1
2
C32
40.
1U_0
402_
16V4
Z~D
1
2
C33
20.
1U_0
402_
16V4
Z~D
1
2
+
C94
150U
_D2_
2VM
_R15
~D
1
2
C46
40.
1U_0
402_
16V4
Z~D1
2
C39
14.
7U_0
805_
10V4
Z~D
1
2
L30BLM11A601S_0603~D
12
R2670.5_0805_1%~D
1 2
R32010_0402_5%~D1@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP+1.8VSUS
+VCCP
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Alviso(5 of 5)
14 51Monday, October 18, 2004
Compal Electronics, Inc.DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VSS
U4J
ALVISO-915PM-B0_BGA1257~D
VSS267AL24VSS266AN24VSS265A26VSS264E26VSS263G26VSS262J26VSS261B27VSS129E27VSS128G27VSS127W27VSS126AA27VSS125AB27VSS124AF27VSS123AG27VSS122AJ27VSS121AL27VSS120AN27VSS119E28VSS118W28VSS117AA28VSS116AB28VSS115AC28VSS114A29VSS113D29VSS112E29VSS111F29VSS110G29VSS109H29VSS108L29VSS107P29VSS106U29VSS105V29VSS104W29VSS103AA29VSS102AD29VSS101AG29VSS100AJ29VSS99AM29VSS98C30VSS97Y30VSS96AA30VSS95AB30VSS94AC30VSS93AE30VSS92AP30VSS91D31VSS90E31VSS89F31VSS88G31VSS87H31VSS86J31VSS85K31VSS84L31VSS83M31VSS82N31VSS81P31VSS80R31VSS79T31VSS78U31VSS77V31VSS76W31VSS75AD31VSS74AG31VSS73AL31VSS72A32VSS71C32VSS70Y32VSS69AA32VSS68AB32
VSS67 AC32VSS66 AD32VSS65 AJ32VSS64 AN32VSS63 D33VSS62 E33VSS61 F33VSS60 G33VSS59 H33VSS58 J33VSS57 K33VSS56 L33VSS55 M33VSS54 N33VSS53 P33VSS52 R33VSS51 T33VSS50 U33VSS49 V33VSS48 W33VSS47 AD33VSS46 AF33VSS45 AL33VSS44 C34VSS43 AA34VSS42 AB34VSS41 AC34VSS40 AD34VSS39 AH34VSS38 AN34VSS37 B35VSS36 D35VSS35 E35VSS34 F35VSS33 G35VSS32 H35VSS31 J35VSS30 K35VSS29 L35VSS28 M35VSS27 N35VSS26 P35VSS25 R35VSS24 T35VSS23 U35VSS22 V35VSS21 W35VSS20 Y35VSS19 AE35VSS18 C36VSS17 AA36VSS16 AB36VSS15 AC36VSS14 AD36VSS13 AE36VSS12 AF36VSS11 AJ36VSS10 AL36
VSS9 AN36VSS8 E37VSS7 H37VSS6 K37VSS5 M37VSS4 P37VSS3 T37VSS2 V37VSS1 Y37VSS0 AG37
NCTF
U4H
ALVISO-915PM-B0_BGA1257~D
VCCSM_NCTF31 AB12VCCSM_NCTF30 AC12VCCSM_NCTF29 AD12VCCSM_NCTF28 AB13VCCSM_NCTF27 AC13VCCSM_NCTF26 AD13VCCSM_NCTF25 AC14VCCSM_NCTF24 AD14VCCSM_NCTF23 AC15VCCSM_NCTF22 AD15VCCSM_NCTF21 AC16VCCSM_NCTF20 AD16VCCSM_NCTF19 AC17VCCSM_NCTF18 AD17VCCSM_NCTF17 AC18VCCSM_NCTF16 AD18VCCSM_NCTF15 AC19VCCSM_NCTF14 AD19VCCSM_NCTF13 AC20VCCSM_NCTF12 AD20VCCSM_NCTF11 AC21VCCSM_NCTF10 AD21
VCCSM_NCTF9 AC22VCCSM_NCTF8 AD22VCCSM_NCTF7 AC23VCCSM_NCTF6 AD23VCCSM_NCTF5 AC24VCCSM_NCTF4 AD24VCCSM_NCTF3 AC25VCCSM_NCTF2 AD25VCCSM_NCTF1 AC26
VCC_NCTF78 L17VCC_NCTF77 M17VCC_NCTF76 N17VCC_NCTF75 P17VCC_NCTF74 T17VCC_NCTF73 U17VCC_NCTF72 V17VCC_NCTF71 W17VCC_NCTF70 L18VCC_NCTF69 M18VCC_NCTF68 N18VCC_NCTF67 P18VCC_NCTF66 R18VCC_NCTF65 Y18VCC_NCTF64 L19VCC_NCTF63 M19VCC_NCTF62 N19VCC_NCTF61 P19VCC_NCTF60 R19VCC_NCTF59 Y19VCC_NCTF58 L20VCC_NCTF57 M20VCC_NCTF56 N20VCC_NCTF55 P20VCC_NCTF54 R20VCC_NCTF53 Y20VCC_NCTF52 L21VCC_NCTF51 M21VCC_NCTF50 N21VCC_NCTF49 P21VCC_NCTF48 T21VCC_NCTF47 U21VCC_NCTF46 V21VCC_NCTF45 W21VCC_NCTF44 L22VCC_NCTF43 M22VCC_NCTF42 N22VCC_NCTF41 P22VCC_NCTF40 R22VCC_NCTF39 T22VCC_NCTF38 U22VCC_NCTF37 V22VCC_NCTF36 W22VCC_NCTF35 L23VCC_NCTF34 M23VCC_NCTF33 N23VCC_NCTF32 P23VCC_NCTF31 R23VCC_NCTF30 T23VCC_NCTF29 U23VCC_NCTF28 V23VCC_NCTF27 W23VCC_NCTF26 L24VCC_NCTF25 M24VCC_NCTF24 N24VCC_NCTF23 P24VCC_NCTF22 R24VCC_NCTF21 T24VCC_NCTF20 U24VCC_NCTF19 V24VCC_NCTF18 W24VCC_NCTF17 L25VCC_NCTF16 M25VCC_NCTF15 N25VCC_NCTF14 P25VCC_NCTF13 R25VCC_NCTF12 T25VCC_NCTF11 U25
VCCSM_NCTF0 AD26
VTT_NCTF17L12VTT_NCTF16M12VTT_NCTF15N12VTT_NCTF14P12VTT_NCTF13R12VTT_NCTF12T12VTT_NCTF11U12VTT_NCTF10V12VTT_NCTF9W12VTT_NCTF8L13VTT_NCTF7M13VTT_NCTF6N13VTT_NCTF5P13VTT_NCTF4R13VTT_NCTF3T13VTT_NCTF2U13VTT_NCTF1V13VTT_NCTF0W13
VSS_NCTF68Y12VSS_NCTF67AA12VSS_NCTF66Y13VSS_NCTF65AA13VSS_NCTF64L14VSS_NCTF63M14VSS_NCTF62N14VSS_NCTF61P14VSS_NCTF60R14VSS_NCTF59T14VSS_NCTF58U14VSS_NCTF57V14VSS_NCTF56W14VSS_NCTF55Y14VSS_NCTF54AA14VSS_NCTF53AB14VSS_NCTF52L15VSS_NCTF51M15VSS_NCTF50N15VSS_NCTF49P15VSS_NCTF48R15VSS_NCTF47T15VSS_NCTF46U15VSS_NCTF45V15VSS_NCTF44W15VSS_NCTF43Y15VSS_NCTF42AA15VSS_NCTF41AB15VSS_NCTF40L16VSS_NCTF39M16VSS_NCTF38N16VSS_NCTF37P16VSS_NCTF36R16VSS_NCTF35T16VSS_NCTF34U16VSS_NCTF33V16VSS_NCTF32W16VSS_NCTF31Y16VSS_NCTF30AA16VSS_NCTF29AB16VSS_NCTF28R17VSS_NCTF27Y17VSS_NCTF26AA17VSS_NCTF25AB17VSS_NCTF24AA18VSS_NCTF23AB18VSS_NCTF22AA19VSS_NCTF21AB19VSS_NCTF20AA20VSS_NCTF19AB20VSS_NCTF18R21VSS_NCTF17Y21VSS_NCTF16AA21VSS_NCTF15AB21VSS_NCTF14Y22VSS_NCTF13AA22VSS_NCTF12AB22VSS_NCTF11Y23VSS_NCTF10AA23VSS_NCTF9AB23VSS_NCTF8Y24VSS_NCTF7AA24VSS_NCTF6AB24VSS_NCTF5Y25VSS_NCTF4AA25VSS_NCTF3AB25VSS_NCTF2Y26VSS_NCTF1AA26VSS_NCTF0AB26
VCC_NCTF10V25VCC_NCTF9W25VCC_NCTF8L26VCC_NCTF7M26VCC_NCTF6N26VCC_NCTF5P26VCC_NCTF4R26VCC_NCTF3T26VCC_NCTF2U26VCC_NCTF1V26VCC_NCTF0W26
VSS
U4I
ALVISO-915PM-B0_BGA1257~D
VSS271Y1VSS270D2VSS269G2VSS268J2VSS260L2VSS259P2VSS258T2VSS257V2VSS256AD2VSS255AE2VSS254AH2VSS253AL2VSS252AN2VSS251A3VSS250C3VSS249AA3VSS248AB3VSS247AC3VSS246AJ3VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239AF4VSS238AN4VSS237E5VSS236W5VSS235AL5VSS234AP5VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228AA6VSS227AC6VSS226AE6VSS225AJ6VSS224G7VSS223V7VSS222AA7VSS221AG7VSS220AK7VSS219AN7VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213AL8VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207AA9VSS206AC9VSS205AE9VSS204AH9VSS203AN9VSS202D10VSS201L10VSS200Y10
VSSALVDS B36
VSS199AA10VSS198F11VSS197H11VSS196Y11
VSS195 AA11VSS194 AF11VSS193 AG11VSS192 AJ11VSS191 AL11VSS190 AN11VSS189 B12VSS188 D12VSS187 J12VSS186 A14VSS185 B14VSS184 F14VSS183 J14VSS182 K14VSS181 AG14VSS180 AJ14VSS179 AL14VSS178 AN14VSS177 C15VSS176 K15VSS175 A16VSS174 D16VSS173 H16VSS172 K16VSS171 AL16VSS170 C17VSS169 G17VSS168 AF17VSS167 AJ17VSS166 AN17VSS165 A18VSS164 B18VSS163 U18VSS162 AL18VSS161 C19VSS160 H19VSS159 J19VSS158 T19VSS157 W19VSS156 AG19VSS155 AN19VSS154 A20VSS153 D20VSS152 E20VSS151 F20VSS150 G20VSS149 V20VSS148 AK20VSS147 C21VSS146 F21VSS145 AF21VSS144 AN21VSS143 A22VSS142 D22VSS141 E22VSS140 J22VSS139 AH22VSS138 AL22VSS137 H23VSS136 AF23VSS135 B24VSS134 D24VSS133 F24VSS132 J24VSS131 AG24VSS130 AJ24
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FAN1_VFBFAN1_ON
FAN1_VOUT
FAN1TACH_ON
FAN1VREF
THERMATRIP1#
THERMATRIP2#
REM_DIODE1_PREM_DIODE1_NTHERMATRIP1#
THERMATRIP2#
THERMATRIP_VGA#
FAN1_TACH_FB
+5VRUN
+15V
+3VRUN+5VRUN
+3VSUS
+RTC_CELL
+3VALW
+5VSUS
+3VSUS
+3VSUS
+VCCP
+VCCP
+3VSUS
+15V
+5VSUS
FAN1_TACH <35>FAN1_PWM<35>
DAT_SMB<35,36>CLK_SMB<35,36>
H_THERMDA<7>
H_THERMDC<7>
SUSPWROK<23,38>
POWER_SW#<35,39>
ATF_INT# <34>
THERMTRIP_SIO <35>
THERM_STP# <42>
SM_INTRUDER# <22>
5V_CAL_SIO# <34>
THERMTRIP_MCH#<10>
H_THERMTRIP#<7>
THERMATRIP_VGA#<18>
ICH_PWRGD#<38>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
FAN & Thermal Sensor
15 51Wednesday, November 03, 2004
Compal Electronics, Inc.
FAN1 Control and Tachometer
1
E 3
2222 SYMBOL(SOT23-NEW)
2
C
B
Place under CPU
REM_DIODE1_N, REM_DIODE1_P routing together.Trace width / Spacing = 10 / 10 mil
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
REM_DIODE1_N, REM_DIODE1_P routing together.Trace width / Spacing = 10 / 10 mil
C3412200P_0402_50V7K~D
1
2
R49910K_0402_5%~D@
12
C21022U_1206_10V4Z~D<BOM Structure>
1
2
R61
1K_0
402_
5%~D
12
R467
10KB_0603_1%_TSM1A103F34D3R~D
12
R59 1K_0402_5%~D1 2
R60100K_0402_5%~D
12
R4981K_0402_5%~D
@
1 2
C3030.1U_0402_16V4Z~D
1
2
EB
C
Q34MMBT3904_SOT23~D
2
31
R50
015
0K_0
402_
5%~D
12
JFAN1
MOLEX_53398-0390~D
112233
R38 1K_0402_5%~D1 2
U29ALM358M_SO8~D
P8
IN+3
IN-2 G4
O 1
R42 1K_0402_5%~D1 2
C3172200P_0402_50V7K~D
1
2
R512.21K_0603_1%~D
12
R2418.2K_0402_5%~D
12
C54
11U
_060
3_10
V4Z~
D
1
2
C440.1U_0402_16V4Z~D
1
2
R392.2K_0402_5%~D
1 2
U15
EMC6N300_SSOP24~D
THDAT_SMB1THCLK_SMB2
SMBADDRSEL13
REM_DIODE2_P18REM_DIODE2_N17
+3VSUS4VSUS_PWRGD11
+RTC_PWR3V10
+3V_PWROK5
POWER_SW21
THERMTRIP16
THERMTRIP27
THERMTRIP38
VSET22HW_LOCK14VSS3
ATF_INT 9
VCP 23
RESSERVED 16
REM_DIODE1_N 19REM_DIODE1_P 20
THERMTRIP_SIO 15THERM_STP 24
INTRUDER 12
R502100K_0402_5%~D
1 2
C462200P_0402_50V7K~D
1
2
C20
910
00P_
0402
_50V
7K~D
@
1
2
C5382200P_0402_50V7K~D
1 2
EB
C
Q39MMBT3904_SOT23~D
2
31
R41310K_0402_5%~D
12
G
D
S
Q402N7002_SOT23~D
2
13
C420.1U_0402_16V4Z~D
1
2
C54
00.
1U_0
603_
50V4
Z~D
1
2
U29BLM358M_SO8~D
P8
IN+5
IN-6 G4
O 7
R47510K_0402_5%~D
12
EB
CQ12MMBT3904_SOT23~D
2
31
R249147K_0603_1%~D
12
C410.1U_0402_16V4Z~D
1
2
R4970_0402_5%~D
1 2
R5049.9_0603_1%~D
1 2
S
GD Q48
SI3456DV-T1_TSOP6~D
3
624
51
R402.2K_0402_5%~D
1 2
R41 8.2K_0402_5%~D1 2
D10RB751V_SOD323~D
21
R2398.2K_0402_5%~D
12
R501100K_0402_5%~D
12
C472200P_0402_50V7K~D
1
2
Q47PMBT2222_SOT23~D @
2
31
R26212.1K_0603_1%~D
12
C430.1U_0402_16V4Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_MA11
V_DDR_MCH_REF
DDR_CKE1_DIMMA
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
CLK_SCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D3
DDR_A_D9
DDR_A_D1DDR_A_D0
DDR_A_D2
DDR_A_D10
DDR_A_D25
DDR_A_D17
DDR_A_D19
DDR_A_D16
DDR_A_D18
DDR_A_D11
DDR_A_D24
DDR_A_D40
DDR_A_D27
DDR_A_D35
DDR_A_D33
DDR_A_D34
DDR_A_D26
DDR_A_D32
DDR_A_D56
DDR_A_D43DDR_A_D42
DDR_A_D50
DDR_A_D49
DDR_A_D51
DDR_A_D48
DDR_A_D41
DDR_A_D59DDR_A_D58
DDR_A_D57
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
CLK_SDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_BS#1DDR_A_RAS#
DDR_A_D6
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D15
DDR_A_D20
DDR_A_D14
DDR_A_D21
DDR_A_D22
DDR_A_D12DDR_A_D13
DDR_A_D29
DDR_A_D30DDR_A_D31
DDR_A_D37DDR_A_D36
DDR_A_D23
DDR_A_D38
DDR_A_D28
DDR_A_D39
DDR_A_D46
DDR_A_D44
DDR_A_D54
DDR_A_D53
DDR_A_D47
DDR_A_D52
DDR_A_D45
DDR_A_D60
DDR_A_D63
DDR_A_D61
DDR_A_D62
DDR_A_D55
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS#0
DDR_A_BS#2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA4
DDR_A_BS#1
DDR_A_MA6
DDR_A_MA2
DDR_A_RAS#DDR_CS0_DIMMA#
M_ODT0
M_ODT1
M_ODT0DDR_A_MA13
DDR_A_MA7
DDR_A_DM0
M_ODT1DDR_CS1_DIMMA#
DDR_A_CAS#DDR_A_WE#
DDR_A_BS#0DDR_A_MA10
DDR_A_MA3DDR_A_MA1
DDR_A_MA5DDR_A_MA8
DDR_A_MA9DDR_A_MA12
DDR_A_BS#2DDR_CKE0_DIMMA
+1.8VSUS +1.8VSUS
+0.9V_DDR_VTT
+3VRUN
+0.9V_DDR_VTT
+1.8VSUS
DDR_A_D[0..63]<11>
DDR_A_DQS[0..7]<11>
DDR_A_MA[0..13]<11>
DDR_A_DM[0..7]<11>
M_CLK_DDR0 <10>
M_CLK_DDR1 <10>
M_CLK_DDR#0 <10>
M_CLK_DDR#1 <10>
DDR_CKE1_DIMMA <10>
DDR_CS0_DIMMA# <10>
DDR_CKE0_DIMMA<10>
DDR_CS1_DIMMA#<10>
DDR_A_DQS#[0..7]<11>
M_ODT0 <10>
M_ODT1<10>
DDR_A_BS#1 <11>
DDR_A_WE#<11>DDR_A_RAS# <11>
DDR_A_CAS#<11>
DDR_A_BS#0<11>
DDR_A_BS#2<11>
V_DDR_MCH_REF <10,17,44>
CLK_SDATA<6,11,17>CLK_SCLK<6,11,17>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
DDRII-SODIMM SLOT1
16 51Monday, October 18, 2004
Compal Electronics, Inc.Layout Note:Place these resistorclosely DIMM0,alltrace lengthMax=1.3"
RESERVEDIMMA
Layout Note:Place near JDIM1
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT
Layout Note:Place these resistorclosely DIMM0,alltrace length<750 mil
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C230
2.2U_0805_6.3V6K~D
1
2
C235
0.1U_0402_16V4Z~D
1
2C219
0.1U_0402_16V4Z~D
1
2 C232
0.1U_0402_16V4Z~D
1
2
C213
2.2U_0805_6.3V6K~D
1
2
C225
2.2U_0805_6.3V6K~D
1
2
C222
2.2U_0805_6.3V6K~D
1
2
RN26
56_0404_4P2R_5%~D
1423
RN16
56_0404_4P2R_5%~D
1 42 3
C228
0.1U_0402_16V4Z~D
1
2
C223
0.1U_0402_16V4Z~D
1
2
RN18
56_0404_4P2R_5%~D
1423
C237
0.1U_0402_16V4Z~D
1
2 C236
0.1U_0402_16V4Z~D
1
2
C215
0.1U_0402_16V4Z~D
1
2
C212
0.1U_0402_16V4Z~D
1
2
JDIM2
JAE_MM50-200B1-1R~D
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
DQS5# 146DQS5 148
VSS 150DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SAO 198SA1 200
RN20
56_0404_4P2R_5%~D
1423
C229
2.2U_0805_6.3V6K~D
1
2
R175 10K_0402_5%~D
1 2
C218
0.1U_0402_16V4Z~D
1
2 C234
0.1U_0402_16V4Z~D
1
2
C227
0.1U_0402_16V4Z~D
1
2
C231
0.1U_0402_16V4Z~D
1
2C220
0.1U_0402_16V4Z~D
1
2 C216
0.1U_0402_16V4Z~D
1
2
RN27
56_0404_4P2R_5%~D
1423
C233
0.1U_0402_16V4Z~D
1
2
RN21
56_0404_4P2R_5%~D
1 42 3
RN17
56_0404_4P2R_5%~D
1423
C226
2.2U_0805_6.3V6K~D
1
2
RN23
56_0404_4P2R_5%~D
1 42 3
C214
2.2U_0805_6.3V6K~D
1
2
C221
0.1U_0402_16V4Z~D
1
2
RN19
56_0404_4P2R_5%~D
1423
RN22
56_0404_4P2R_5%~D
1 42 3
RN15
56_0404_4P2R_5%~D
1423
R176 10K_0402_5%~D
1 2
C224
0.1U_0402_16V4Z~D
1
2
C217
0.1U_0402_16V4Z~D
1
2
RN25
56_0404_4P2R_5%~D
1 42 3
RN24
56_0404_4P2R_5%~D
1 42 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_MA0
DDR_B_RAS#DDR_CS2_DIMMB#
DDR_B_BS#1
DDR_CKE3_DIMMB
DDR_B_MA4
DDR_B_MA7
DDR_B_MA2
DDR_B_MA11
DDR_B_MA6
M_ODT2DDR_B_MA13
M_ODT3DDR_CS3_DIMMB#
DDR_B_WE#DDR_B_CAS#
DDR_B_BS#0DDR_B_MA10
DDR_B_MA1DDR_B_MA3
DDR_B_MA5DDR_B_MA8
DDR_B_MA9DDR_B_MA12
DDR_B_BS#2DDR_CKE2_DIMMB
DDR_B_DQS#5
DDR_B_D50
DDR_B_D20
DDR_B_D27
DDR_B_D3
DDR_B_D62
DDR_B_D52
DDR_B_BS#1
DDR_CKE3_DIMMB
DDR_B_D23
DDR_B_D21
DDR_B_D33
M_ODT3
DDR_CS3_DIMMB#
DDR_B_BS#0
DDR_B_D2
DDR_B_D60
M_CLK_DDR4
DDR_B_D59
DDR_B_RAS#
DDR_B_MA4
DDR_B_D29
DDR_B_D22
DDR_B_DM2
DDR_B_MA9
DDR_B_DQS6
DDR_B_DM5
DDR_B_MA1
DDR_B_DQS#1
DDR_B_D46DDR_B_D42
DDR_B_DQS#3
DDR_CKE2_DIMMB
DDR_B_D25DDR_B_D24
DDR_B_D16
DDR_B_D8
DDR_B_D61
DDR_B_D48
DDR_B_D44
DDR_B_D38
M_ODT2
DDR_B_D31
DDR_B_D14
DDR_B_DM1
DDR_B_D35
DDR_B_D0
V_DDR_MCH_REF
DDR_B_D54
DDR_B_D57
DDR_B_DM4
DDR_B_MA0
DDR_B_DM0
DDR_B_D41
DDR_B_DQS#4
DDR_B_CAS#
DDR_B_MA3
DDR_B_BS#2
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS1
CLK_SCLK
DDR_B_D43
DDR_B_DQS3
DDR_B_D5
DDR_B_WE#
DDR_B_D19
DDR_B_D11
DDR_B_DQS0
DDR_B_D63
DDR_B_D51
DDR_B_MA7
DDR_B_D30
DDR_B_D28
DDR_B_D13
DDR_B_D26
DDR_B_DQS2
DDR_B_D1
DDR_B_DM6
DDR_B_D53
DDR_B_MA2
DDR_B_MA10
DDR_B_DM3
DDR_B_DQS#2
CLK_SDATA
DDR_B_D39
DDR_B_MA13
DDR_B_D7DDR_B_D6
DDR_B_MA5
DDR_B_D17
M_CLK_DDR#4
DDR_B_D56
DDR_B_D18
DDR_B_DQS#0
DDR_B_DQS#7
DDR_B_DQS#6
DDR_B_D49
DDR_B_D36
DDR_CS2_DIMMB#
DDR_B_D12
DDR_B_D40
DDR_B_D9
DDR_B_D55
DDR_B_D45
DDR_B_D37
DDR_B_MA11
M_CLK_DDR#3
DDR_B_D10
DDR_B_DQS7
DDR_B_D47
DDR_B_D58
DDR_B_DM7
DDR_B_MA6
DDR_B_D4
DDR_B_MA12
DDR_B_D15
M_CLK_DDR3
DDR_B_D34
DDR_B_D32
DDR_B_MA8
+0.9V_DDR_VTT
+0.9V_DDR_VTT
+1.8VSUS
+3VRUN
+3VRUN
+1.8VSUS+1.8VSUS
V_DDR_MCH_REF <10,16,44>DDR_B_D[0..63]<11>
DDR_B_DQS[0..7]<11>
DDR_B_MA[0..13]<11>
DDR_B_DM[0..7]<11>
DDR_B_DQS#[0..7]<11>
DDR_B_CAS#<11>
M_ODT3<10>
DDR_CKE3_DIMMB <10>
DDR_B_WE#<11>
M_CLK_DDR4 <10>
CLK_SCLK<6,11,16>
DDR_CKE2_DIMMB<10>
DDR_B_BS#0<11> DDR_B_RAS# <11>
CLK_SDATA<6,11,16>
M_CLK_DDR3 <10>
DDR_B_BS#1 <11>
M_CLK_DDR#4 <10>
DDR_B_BS#2<11>
M_ODT2 <10>DDR_CS3_DIMMB#<10>
DDR_CS2_DIMMB# <10>
M_CLK_DDR#3 <10>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
DDRII-SODIMM SLOT2
17 51Monday, October 18, 2004
Compal Electronics, Inc.
Layout Note:Place these resistorclosely DIMM0,alltrace length<750 mil
Layout Note:Place these resistorclosely DIMM0,alltrace lengthMax=1.3"
Layout Note:Place near JDIM2
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
DIMMBSTANDARD
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RN14
56_0404_4P2R_5%~D
1423
C240
0.1U_0402_16V4Z~D
1
2
RN10
56_0404_4P2R_5%~D
1 42 3
C239
0.1U_0402_16V4Z~D
1
2
C269
0.1U_0402_16V4Z~D
1
2
RN11
56_0404_4P2R_5%~D
1 42 3
C266
0.1U_0402_16V4Z~D
1
2
JDIM1
JAE_MM50-200B1-1~D
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
DQS5# 146DQS5 148
VSS 150DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SAO 198SA1 200
C254
2.2U_0805_6.3V6K~D
1
2
R173
10K_0402_5%~D
12
R17410K_0402_5%~D
12
C245
0.1U_0402_16V4Z~D
1
2
C250
0.1U_0402_16V4Z~D
1
2
RN7
56_0404_4P2R_5%~D
1423
RN8
56_0404_4P2R_5%~D
1 42 3
C265
0.1U_0402_16V4Z~D
1
2
RN3
56_0404_4P2R_5%~D
1 42 3
C263
0.1U_0402_16V4Z~D
1
2
C241
2.2U_0805_6.3V6K~D
1
2
C243
0.1U_0402_16V4Z~D
1
2
C252
0.1U_0402_16V4Z~D
1
2
C246
0.1U_0402_16V4Z~D
1
2
C253
2.2U_0805_6.3V6K~D
1
2
RN4
56_0404_4P2R_5%~D
1 42 3
C248
0.1U_0402_16V4Z~D
1
2 C267
0.1U_0402_16V4Z~D
1
2
RN12
56_0404_4P2R_5%~D
1423
C548
2.2U_0805_6.3V6K~D
1
2
C247
0.1U_0402_16V4Z~D
1
2 C264
0.1U_0402_16V4Z~D
1
2
RN13
56_0404_4P2R_5%~D
1423
RN2
56_0404_4P2R_5%~D
1423
C549
0.1U_0402_16V4Z~D
1
2
C244
0.1U_0402_16V4Z~D
1
2
C261
2.2U_0805_6.3V6K~D
1
2
C255
0.1U_0402_16V4Z~D
1
2
C251
0.1U_0402_16V4Z~D
1
2
RN9
56_0404_4P2R_5%~D
1 42 3
C268
0.1U_0402_16V4Z~D
1
2
C242
2.2U_0805_6.3V6K~D
1
2
RN6
56_0404_4P2R_5%~D
1423
RN5
56_0404_4P2R_5%~D
1423
C249
2.2U_0805_6.3V6K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_TXP1PEG_TXP2
PEG_TXP4PEG_TXP5
PEG_TXP3
PEG_TXP6
PEG_TXP8PEG_TXP7
PEG_TXP12PEG_TXP13PEG_TXP14
PEG_TXP9
PEG_TXP0
PEG_TXP11PEG_TXP10
PEG_TXP[0..15]
PEG_TXP15
PEG_TXN1
PEG_TXN7
PEG_TXN3
PEG_TXN5
PEG_TXN2
PEG_TXN4
PEG_TXN8
PEG_TXN12
PEG_TXN0
PEG_TXN6
PEG_TXN13
PEG_TXN10
PEG_TXN14
PEG_TXN9
PEG_TXN11
PEG_TXN15
PEG_TXN[0..15]
PEG_RXP6
PEG_RXP9
PEG_RXN11
PEG_RXN13
PEG_RXP10
PEG_RXN5
PEG_RXP7
PEG_RXN3
PEG_RXP3
PEG_RXP15
PEG_RXN9
PEG_RXP8
PEG_RXP0
PEG_RXN7
PEG_RXP5
PEG_RXP14PEG_RXP13
PEG_RXN14
PEG_RXN0
PEG_RXN15
PEG_RXP2
PEG_RXN10
PEG_RXN2
PEG_RXP4
PEG_RXN4
PEG_RXP12
PEG_RXN12
PEG_RXN8
PEG_RXN1
PEG_RXP11
PEG_RXP1
PEG_RXN6
PEG_A_TXN_7
PEG_A_TXP_6PEG_A_TXN_6
PEG_A_TXP_7
PEG_A_TXP_8PEG_A_TXN_8
PEG_A_TXP_10PEG_A_TXN_10
PEG_A_TXP_9PEG_A_TXN_9
PEG_A_TXP_11PEG_A_TXN_11
PEG_A_TXP_0PEG_A_TXN_0
PEG_A_TXP_12PEG_A_TXN_12
PEG_A_TXP_1PEG_A_TXN_1
PEG_A_TXP_15PEG_A_TXN_15
PEG_A_TXN_13PEG_A_TXP_13
PEG_A_TXN_14PEG_A_TXP_14
PEG_A_TXP_2PEG_A_TXN_2
PEG_A_TXP_3PEG_A_TXN_3
PEG_A_TXP_5PEG_A_TXN_5
PEG_A_TXP_4PEG_A_TXN_4
PEG_TXP1
PEG_TXP2
PEG_TXP0
PEG_TXP4
PEG_TXN1
PEG_TXN2
PEG_TXN0
PEG_TXP3
PEG_TXP5PEG_TXN5
PEG_TXN4
PEG_TXP7PEG_TXN7
PEG_TXP8PEG_TXN8
PEG_TXP6
PEG_TXN3
PEG_TXN10
PEG_TXP11PEG_TXN11
PEG_TXN6
PEG_TXP10
PEG_TXN9
PEG_TXP12PEG_TXN12
PEG_TXP9
PEG_TXP14PEG_TXN14
PEG_TXP13
PEG_TXP15PEG_TXN15
PEG_TXN13
PEG_RXN[0..15]
PEG_RXP[0..15]
RUNPWROK
SBAT_SMBCLKSBAT_SMBDAT
TV_Y
TV_CVBS
TV_C
VSYNCHSYNC
VGA_RED
VGA_BLU
VGA_GRN
CLK_DDC2DAT_DDC2
CLK_PCIE_VGA#CLK_PCIE_VGA
PLTRST_DELAY#
PEG_RXN0
PEG_RXN2
PEG_RXP1PEG_RXN1
PEG_RXN5
PEG_RXN6
PEG_RXP3
PEG_RXP2
PEG_RXN3
PEG_RXP0
PEG_RXP4
PEG_RXP6
PEG_RXN7
PEG_RXN4
PEG_RXP5
PEG_RXP7
PEG_RXN8
PEG_RXP9
PEG_RXP8
PEG_RXN9
PEG_RXP15
PEG_RXN14PEG_RXP14
PEG_RXN13PEG_RXP13
PEG_RXN15
PEG_RXP11
PEG_RXN10PEG_RXP10
PEG_RXP12
PEG_RXN11
PEG_RXN12
THERMATRIP_VGA#+5VRUNGC_BL_SUSPEND
ICH_PCIE_WAKE#
VGA_BLU
VGA_GRN
VGA_RED
TV_Y
TV_CVBS
TV_C
CLK_DDC2
DAT_DDC2
HSYNC
VSYNC
BIA_PWM_VGA
G_PWR_SRC
+3VRUN
+15V +5VRUN
+5VALW
+1.5VRUN
+3VSUS
+2.5VRUN
+1.8VRUN
VDDM
PEG_TXP[0..15]<12>
PEG_TXN[0..15]<12>
PEG_RXN[0..15] <12>
PEG_RXP[0..15] <12>
RUNPWROK<35,38,43,45>
SBAT_SMBCLK <35>SBAT_SMBDAT <35>
TV_Y <20>
TV_C <20>
TV_CVBS <20>
VSYNC <20>HSYNC <20>
VGA_BLU <20>
VGA_GRN <20>
VGA_RED <20>
DAT_DDC2 <20>CLK_DDC2 <20>
CLK_PCIE_VGA <6>CLK_PCIE_VGA# <6>
PLTRST_DELAY# <23>
THERMATRIP_VGA# <15>
GC_BL_SUSPEND <34>
ICH_PCIE_WAKE# <23,34>
INTCRT_R<12>
INTCRT_G<12>
INTCRT_B<12>
COMP/B<12>
Y/G<12>
C/R<12>
INT_CLK_DDC2<12>
INT_DAT_DDC2<12>
INT_HSYNC<12>
INT_VSYNC<12>
BIA_PWM <12,35>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
VGA connector
18 51Monday, October 18, 2004
Compal Electronics, Inc.
DVI Interface
DVI Interface
Depop when with external graphics
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C56
910
U_1
206_
25V6
M~D
@
1
2
C104 0.1U_0402_10V6K~D2@
1 2
C103 0.1U_0402_10V6K~D2@
1 2
C129 0.1U_0402_10V6K~D2@
1 2
R53 0_0402_5%~D
1@ 12
C91 0.1U_0402_10V6K~D2@
1 2
C57 0.1U_0402_10V6K~D2@
1 2
R73 0_0402_5%~D
1@ 12
C132 0.1U_0402_10V6K~D2@
1 2
C75 0.1U_0402_10V6K~D 2@
1 2
C31
90.
047U
_040
2_16
V4Z~
D
2@
1
2
C16
10.
1U_0
603_
50V4
Z~D
2@ 1
2
C56 0.1U_0402_10V6K~D2@
1 2
C111 0.1U_0402_10V6K~D2@
1 2
C116 0.1U_0402_10V6K~D 2@
1 2
R79 0_0402_5%~D
1@ 1 2
C79 0.1U_0402_10V6K~D2@
1 2
C107 0.1U_0402_10V6K~D2@
1 2
C17
10.
1U_0
603_
50V4
Z~D
2@ 1
2
JVID
JAE_WB3M200VD1~D2@
1133557799111113131515171719192121232325252727292931313333353537373939414143434545474749495151535355555757595961616363656567676969717173737575777779798181838385858787898991919393959597979999101101103103105105107107109109111111113113115115117117119119121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149151151153153155155157157159159161161163163165165167167169169171171173173175175177177179179181181183183185185187187189189191191193193195195197197199199201201
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 6062 6264 6466 6668 6870 7072 7274 7476 7678 7880 8082 8284 8486 8688 8890 9092 9294 9496 9698 98
100 100102 102104 104106 106108 108110 110112 112114 114116 116118 118120 120122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150152 152154 154156 156158 158160 160162 162164 164166 166168 168170 170172 172174 174176 176178 178180 180182 182184 184186 186188 188190 190192 192194 194196 196198 198200 200202 202
203203 204 204205205 206 206
C84 0.1U_0402_10V6K~D2@
1 2
C122 0.1U_0402_10V6K~D2@
1 2
C96 0.1U_0402_10V6K~D2@
1 2
PJP18@PAD-OPEN 4x4m1 2
C15
50.
1U_0
603_
50V4
Z~D
2@
1
2
R63 0_0402_5%~D
1@ 1 2
C67 0.1U_0402_10V6K~D2@
1 2
C72 0.1U_0402_10V6K~D2@
1 2
C95 0.1U_0402_10V6K~D2@
1 2
C123 0.1U_0402_10V6K~D2@
1 2
C31
30.
047U
_040
2_16
V4Z~
D2@
1
2
C16
70.
1U_0
603_
50V4
Z~D
2@ 1
2
C128 0.1U_0402_10V6K~D2@
1 2
C85 0.1U_0402_10V6K~D2@
1 2
R70 0_0402_5%~D
1@ 12
C71 0.1U_0402_10V6K~D 2@
1 2
R5340_0402_5%~D
2@
1 2
R58 0_0402_5%~D
1@ 1 2
C126 0.1U_0402_10V6K~D2@
1 2
R67 0_0402_5%~D
1@ 12
C115 0.1U_0402_10V6K~D2@
1 2
C69 0.1U_0402_10V6K~D2@
1 2
C125 0.1U_0402_10V6K~D2@
1 2
R49 0_0402_5%~D
1@ 12
C80 0.1U_0402_10V6K~D2@
1 2
R76 0_0402_5%~D
1@ 1 2
C62 0.1U_0402_10V6K~D2@
1 2
C74 0.1U_0402_10V6K~D2@
1 2
C92 0.1U_0402_10V6K~D2@
1 2
R48 0_0402_5%~D
1@ 12
C106 0.1U_0402_10V6K~D2@
1 2
C30
90.
047U
_040
2_16
V4Z~
D2@
1
2
C112 0.1U_0402_10V6K~D2@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+LCDVCC
LCD_TST
BACKLITE_ON
LAMP_STAT
LCD_DDCCLKLCD_DDCDATA
LCD_A1-
LCD_A0+
LCD_A2-
LCD_A0-
LCD_A2+
LCD_A1+
LCD_ACLK+LCD_ACLK-
LCD_BCLK+
LCD_B0+LCD_B0-
LCD_B2-
LCD_B1-
LCD_B2+
LCD_BCLK-
LCD_B1+
+3VRUN
+LCDVDD
+3VRUN
G_PWR_SRCPWR_SRC
G_PWR_SRC
+5VALW
+LCDVDD
+LCDVDD+15V
+15V
PBAT_SMBDAT <35,41,46>PBAT_SMBCLK <35,41,46>
RUN_ON<34,37,38,42,44>
LCD_TST <23,34>
PANEL_BKEN <12>
LAMP_STAT <21>
LCD_DDCCLK <12>LCD_DDCDATA <12>
LCD_A0- <12>LCD_A0+ <12>
LCD_A1- <12>LCD_A1+ <12>
LCD_A2- <12>LCD_A2+ <12>
LCD_ACLK- <12>LCD_ACLK+ <12>
LCD_B0- <12>LCD_B0+ <12>
LCD_B1- <12>LCD_B1+ <12>
LCD_B2- <12>LCD_B2+ <12>
LCD_BCLK- <12>LCD_BCLK+ <12>
ENVDD<12>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Internal LVDS
19 51Wednesday, November 03, 2004
Compal Electronics, Inc.
FDS4435: P CHANNAL
40mil40mil
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R272100K_0402_5%~D 1@
12
C27
0.1U_0402_16V4Z~D
1@ 1
2
C2960.1U_0603_50V4Z~D 1@
1
2
G
D S
Q292N7002_SOT23~D
2
1 3
C2890.1U_0603_50V4Z~D
1
2
Q32FDS4435_SO8~D
4
78
65
123
R2380_0805_5%~D
1@12
G
D
S
Q10
2N70
02_S
OT2
3~D
1@
2
13
R35470_0402_5%~D 1@
12
S
GD Q9
SI3456DV-T1_TSOP6~D 1@
3
6
24 5
1
R236
100K_0402_5%~D
1 2
R248
0_0805_5%~D 1@
12
C31
50.
1U_0
402_
16V4
Z~D
1@
1
2
R263100K_0402_5%~D 1@
12
G
D
S Q372N7002_SOT23~D 1@
2
13
R240 0_0402_5%~D
1@1 2
C29
0.1U
_040
2_16
V4Z~
D 1
@
1
2
Q8DTC124EKA_SC59~D
1@I2
O1
G3
C260.1U_0402_16V4Z~D
1@
1
2
R54100K_0402_5%~D 1@
12
C2901000P_0603_50V7K~D
1
2
JLVDS
JAE_FI-TD44SB-L~D1@
TXUCLKUT- 44
GND1 42
TXUOUT2+ 40
TXUOUT1- 38
GND3 36
TXUOUT0+ 34
TXLCLKOUT- 32
GND5 30
TXLOUT2+ 28
TXLOUT1- 26
GND7 24
TXLOUT0+ 22
PANEL_I2C_DAT 19GND9 18
GND10 16
LCDVDD2 14
LCDPWR_SRC 12
LCDPWR_SRC 10
+5V_ALWF 3
PBAT_SMBCLK 6
GND13 4
FPBACK 8
TXUCLKUT+ 43
TXUOUT2- 41
GND2 39
TXUOUT1+ 37
TXUOUT0- 35
GND4 33
TXLCLKOUT+ 31
TXLOUT2- 29
GND6 27
TXLOUT1+ 25
TXLOUT0- 23
GND8 21PANEL_I2C_CLK 20
VEDID 17
LCDVDD1 15
PNL_SLFTST 13
LCDPWR_SRC 11
GND11 9
LAMP_START 2
PBAT_SMBDAT 5
GND12 7
GND14 1
MGND145MGND246MGND347MGND448MGND549MGND650MGND751MGND856MGND957MGND1054MGND1155
C280.1U_0402_16V4Z~D1@
1
2
R235100K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA_GRN
VGA_BLU
VGA_RED
SVIDEO_Y
SVIDEO_CSVIDEO_CVBS
HSYNC_R
VSYNC_R
BLUE
JVGA_VSCRT_VCC
GREEN
JVGA_HS
DAT_DDC2
CLK_DDC2
M_ID2#
RED
+5VRUN
+3VRUN
+3VRUN
CRT_VCC
CRT_VCC
CRT_VCC
TV_Y<18>
VGA_RED<18>
VSYNC<18>
VGA_GRN<18>
CLK_DDC2<18>
TV_CVBS<18>
HSYNC<18>
VGA_BLU<18>
TV_C<18>
DAT_DDC2<18>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
TV_OUT and CRT
20 51Monday, October 18, 2004
Compal Electronics, Inc.
A2
A1
K1
K2
DA204U
CLOSE TO JTV1
Evaluate Package
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R13, R16, R17, R18, R19, and R20 Pop150 ohm resistor for internal Gfx
C10
82P
_040
2_50
V8J~
D
1
2
D7
RB
751V
_SO
D32
3~D
21
C15
22P
_040
2_50
V8J~
D
@
1
2R20
75_0
402_
1%~D
12
L22BLM11A121S_0603~D
1 2
R16
75_0
402_
1%~D
1
2
T1 PAD~D@
R17
75_0
402_
1%~D
12
R11
1K_0
402_
5%~D
@1
2
R233
39_0402_5%~D
1 2
L11.8UH_MDF1608A1R8K_10%_0603~D
1 2
C5
82P
_040
2_50
V8J~
D
1
2
D11DA204U_SOT323~D@
2 31
D13DA204U_SOT323~D@
2 31
R234
39_0402_5%~D
1 2
C28
622
P_0
402_
50V8
J~D
1
2
C14
22P
_040
2_50
V8J~
D
@
1
2
JTVOUT
FOX_MH11777-WRUR6~D
246
35
1
98
7
C16
82P
_040
2_50
V8J~
D
1
2
U12
74AHCT1G125GW_SOT353~D
A2 Y 4OE#
1
G3
P5
C310P_0402_50V8J~D@
1
2R19
75_0
402_
1%~D
12
L6BLM18BB600SN1D_0603~D
1 2
R9
2.2K
_040
2_5%
~D
12
R13
75_0
402_
1%~D
12
U13
74AHCT1G125GW_SOT353~D
A2 Y 4OE#
1
G3
P5
D4DA204U_SOT323~D@
2 31
C12
22P
_040
2_50
V8J~
D
@
1
2 C11
0.01
U_0
402_
16V7
K~D
1
2
L31.8UH_MDF1608A1R8K_10%_0603~D
1 2
D5DA204U_SOT323~D@
2 31
D12DA204U_SOT323~D @
2 31
R2281K_0402_5%~D1 2
C7
82P
_040
2_50
V8J~
D
1
2
R18
75_0
402_
1%~D
12
L4BLM18BB600SN1D_0603~D
1 2
C210P_0402_50V8J~D@
1
2
JCRT
FOX_DZ11A91-L8
611
17
1228
1339
144
1015
5
1819
R10
2.2K
_040
2_5%
~D
12
C110P_0402_50V8J~D@
1
2
C40.1U_0402_16V4Z~D
1
2
R7
1K_0
402_
5%~D
@
12
L23BLM11A121S_0603~D
1 2
D6DA204U_SOT323~D@
2 31
L21.8UH_MDF1608A1R8K_10%_0603~D
1 2
C17
82P
_040
2_50
V8J~
D
1
2
L5BLM18BB600SN1D_0603~D
1 2
C6
82P
_040
2_50
V8J~
D
1
2
C8
22P
_040
2_50
V8J~
D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_ICH
PCI_SERR#
PCI_DEVSEL#PCI_PCIRST#
PCI_C_BE0#
PCI_REQ4#
PCI_PERR#
PCI_GNT4#
PCI_GNT1#
ICH_GPIO4_PIRQG#PCI_PIRQB#
PCI_REQ5#
PCI_STOP#
PCI_C_BE1#
PCI_C_BE3#
ICH_GPIO3_PIRQF#PCI_PIRQC#
PCI_REQ2#
ICH_GPIO2_PIRQE#
LAMP_STAT
PCI_FRAME#
PCI_REQ3#
PCI_PLOCK#
PCI_IRDY#
PCI_C_BE2#
PCI_REQ1#
PCI_REQ0#
PCI_PIRQD#
PCI_PIRQA#
PCI_PAR
PCI_GNT3#
PCI_TRDY#
ICH_GPIO5_PIRQH#
PCI_PCIRST#PCI_RST#
PCI_PLTRST#CLK_PCI_ICHICH_PME#
PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5
PCI_AD7PCI_AD6
PCI_AD8PCI_AD9
PCI_AD11PCI_AD10
PCI_AD14PCI_AD15
PCI_AD13PCI_AD12
PCI_AD16PCI_AD17
PCI_AD19PCI_AD18
PCI_AD22PCI_AD23
PCI_AD21PCI_AD20
PCI_AD25PCI_AD24
PCI_AD28PCI_AD29
PCI_AD31PCI_AD30
PCI_AD26PCI_AD27
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_PLOCK#
PCI_SERR#
PCI_PERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
ICH_GPIO5_PIRQH#
ICH_GPIO4_PIRQG#
ICH_GPIO3_PIRQF#
ICH_GPIO2_PIRQE#
PCI_REQ0#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
LAMP_STAT
PCI_PLTRST#PLTRST#
PCI_REQ1#
PCI_GNT5#
PCI_GNT5#
+3VRUN
+3VRUN +3VSUS
+3VSUS
PCI_C_BE1# <30,31,33>
PCI_SERR# <30,31,33>
PCI_PAR <30,31,33>PCI_IRDY# <30,31,33>
PCI_REQ4# <30>
PCI_PERR# <30,31,33>
PCI_GNT1# <31>
PCI_PIRQC#<30,31>
PCI_C_BE3# <30,31,33>
PCI_FRAME#<30,31,33>
PCI_REQ1# <31>
PCI_C_BE2# <30,31,33>
PCI_DEVSEL# <30,31,33>
PCI_PIRQB#<31,33>
PCI_GNT4# <30>
PCI_PIRQD#<31,33>
PCI_TRDY# <30,31,33>
PCI_GNT3# <33>
PCI_C_BE0# <30,31,33>
PCI_STOP# <30,31,33>
PCI_REQ3# <33>
PCI_AD[0..31]<30,31,33>
CLK_PCI_ICH <6>ICH_PME# <34>
PCI_RST# <30,31,33>
PLTRST# <10,23,25,34>
LAMP_STAT <19>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
ICH6(1/4)
21 51Monday, October 18, 2004
Compal Electronics, Inc.
Place closely pin G6Pop resistor to boot from PCI
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R43 8.2K_0402_5%~D
1 2
R72 8.2K_0402_5%~D
1 2
R339 8.2K_0402_5%~D
1 2
R286 8.2K_0402_5%~D
1 2
U21C74VHC08MTC_TSSOP14~D
IN110
IN29 OUT 8
P14
G7
R257 8.2K_0402_5%~D
1 2
Interrupt I/F
PCI
RESERVED
U3B
ICH6_BGA609~D
AD[0]E2AD[1]E5AD[2]C2AD[3]F5AD[4]F3AD[5]E9AD[6]F2AD[7]D6AD[8]E6AD[9]D3AD[10]A2AD[11]D2AD[12]D5AD[13]H3AD[14]B4AD[15]J5AD[16]K2AD[17]K5AD[18]D4AD[19]L6AD[20]G3AD[21]H4AD[22]H2AD[23]H5AD[24]B3AD[25]M6AD[26]B2AD[27]K6AD[28]K3AD[29]A5AD[30]L1AD[31]K4
FRAME#J3
REQ[0]# L5GNT[0]# C1REQ[1]# B5GNT[1]# B6REQ[2]# M5GNT[2]# F1REQ[3]# B8GNT[3]# C8
REQ[4]#/GPI[40] F7GNT[4]#/GPO[48] E7
REQ[5]#/GPI[1] E8GNT[5]#/GPO[17] F6
REQ[6]#/GPI[0] B7
TRDY# J2STOP# J1
PLTRST# R5PCICLK G6
PME# P6
PIRQ[E]#/GPI[2] D9PIRQ[F]#/GPI[3] C7PIRQ[G]#GPI[4] C6PIRQ[H]#/GPI[5] M3
GNT[6]#/GPO[16] D8
C/BE[0]# J6C/BE[1]# H6C/BE[2]# G4C/BE[3]# G2
IRDY# A3PAR E1
PCIRST# R2DEVSEL# C3
PERR# E3PLOCK# C5
SERR# G5
PIRQ[C]#M1
SATA[1]TXP/RSVD[4]AG4
PIRQ[A]#N2
SATA[3]RXN/RSVD[5]AC9
SATA[1]RXP/RSVD[2]AD5SATA[1]TXN/RSVD[3]AF4
PIRQ[B]#L2
PIRQ[D]#L3
SATA[1]RXN/RSVD[1]AC5
SATA[3]RXP/RSVD[6]AD9SATA[3]TXN/RSVD[7]AF8SATA[3]TXP/RSVD[8]AG8TP[3]/RSVD[9]U3
R46 8.2K_0402_5%~D1 2
R309 8.2K_0402_5%~D
1 2
R33210_0402_5%~D@
12
U21D74VHC08MTC_TSSOP14~D
IN113
IN212 OUT 11
P14
G7
R256 8.2K_0402_5%~D
1 2
R45 8.2K_0402_5%~D
1 2
R258 8.2K_0402_5%~D
1 2
R69 8.2K_0402_5%~D
1 2
R254 8.2K_0402_5%~D1 2
R324 8.2K_0402_5%~D
1 2
C3498.2P_0402_50V8J~D@
1
2
R77 8.2K_0402_5%~D
1 2
R44 8.2K_0402_5%~D
1 2
R75 8.2K_0402_5%~D
1 2
R340 8.2K_0402_5%~D
1 2
R327 8.2K_0402_5%~D
1 2
R350 8.2K_0402_5%~D
1 2
R317 8.2K_0402_5%~D
1 2
R255 8.2K_0402_5%~D
1 2
R47 8.2K_0402_5%~D1 2
R3281K_0402_5%~D @
12
R315 8.2K_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IDE_DDREQ
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMIH_SMI#
H_STPCLK#
H_FERR#
IDE_IRQ
H_DPRSTP#
IDE_DD9
IDE_DD2
IDE_DCS3#SATA_TXN0_C
ICH_RTCX2
CLK_PCIE_SATA#
IDE_DD15
IDE_DD0
IDE_DIOR#
CLK_PCIE_SATA
SATA_TXP0_C
DPRSLP#
LPC_LFRAME#
IDE_DA1
IDE_DD14
IDE_DA2
LPC_LDRQ1#
IDE_DIOW#
ICH_AC_SDIN1
IDE_DD6
IDE_DA0
FERR#
ICH_AC_SDOUT_R
IDE_DD13
ICH_AC_BITCLK
SATA_ACT#
IDE_DD10
IDE_DD8
IDE_DD1
IDE_DD7
IDE_DD4
LPC_LAD3LPC_LAD2
ICH_AC_RST_R#
IDE_IRQ
H_PWRGOOD
IDE_DD12
IDE_DD3
THRMTRIP_ICH#
IDE_DD5
ICH_RTCX1
SIO_RCIN#
LPC_LAD0
ICH_RTCRST#
IDE_DD11
IDE_DDACK#
ICH_AC_SDIN0
SIO_A20GATE
SATA_RXP0_C
LPC_LDRQ0#
H_DPSLP#
SM_INTRUDER#
IDE_DIORDY
IDE_DCS1#
LPC_LAD1
ICH_AC_BITCLK
SATA_RXN0_C
SM_INTRUDER#
ICH_AC_SYNC_R
ICH_AC_SYNC_R
ICH_AC_RST_R#
ICH_AC_SDOUT_R
H_DPRSTP#
SATA_TXP0_C SATA_TXP0
SATA_TXN0SATA_TXN0_C
H_CPUSLP#H_CPUSLP_R#
+3VRUN
+VCCP
+RTC_CELL
+VCCP
+RTC_CELL
IDE_DD[0..15] <25>
LPC_LFRAME# <34>
IDE_DDACK#<25>
IDE_DIOR#<25>IDE_DIOW#<25>
ICH_AC_SDIN1<29>
IDE_DDREQ <25>
LPC_LAD[0..3] <34>
IDE_DA[0..2] <25>
CLK_PCIE_SATA<6>
H_INTR <7>H_INIT# <7>
H_DPSLP# <7>
H_NMI <7>
H_IGNNE# <7>
H_A20M# <7>
H_SMI# <7>
H_STPCLK# <7>
H_CPUSLP# <7,10>
SATA_ACT#<39>
IDE_IRQ<25>
H_DPRSTP# <7>
H_FERR# <7>
H_PWRGOOD <7>
SIO_RCIN# <34>
IDE_DIORDY<25>
IDE_DCS1# <25>
LPC_LDRQ0# <34>SM_INTRUDER#<15>
SIO_A20GATE <35>
SATA_RXP0_C<25>
ICH_AC_BITCLK<26>
SATA_RXN0_C<25>
ICH_AC_SDIN0<26>
IDE_DCS3# <25>
CLK_PCIE_SATA#<6>
LPC_LDRQ1# <34>
ICH_RST_AUDIO#<26>
ICH_SYNC_AUDIO<26>
ICH_SDOUT_AUDIO<26>
ICH_SYNC_MDC<29>
ICH_RST_MDC#<29>
ICH_SDOUT_MDC<29>
SATA_TXP0 <25>
SATA_TXN0 <25>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
ICH6(2/4)
22 51Monday, October 18, 2004
Compal Electronics, Inc.
Package9.6X4.06 mm
Place closely pin C10
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near ICH6 side.
R37833_0402_5%~D
1 2
C4012P_0402_50V8J~D 12
R12756_0402_5%~D
12R371
33_0402_5%~D
1 2
R276100K_0402_5%~D
12
R11856_0402_5%~D
12
R36110_0402_5%~D@
12
C340 3900P_0402_50V7K~D1 2
X1
32.768KHZ_12.5P_MC-306~D
12
C3480.1U_0402_16V4Z~D
1 2
R297180K_0402_5%~D
1 2
R8333_0402_5%~D
1 2
C36210P_0402_50V8J~D @1
2
R115 75_0402_5%~D1 2
RTC
LAN
SATA
AC-97/AZALIA
LPC
CPU
IDE
U3A
ICH6_BGA609~D
RTCX1Y1RTCX2Y2
RTCRST#AA2
INTRUDER#AA3INTVRMENAA5
EE_CSD12EE_SHCLKB12EE_DOUTD11EE_DINF13
LAN_CLKF12
LAN_RSTSYNCB11
LANRXD[0]E12LANRXD[1]E11LANRXD[2]C13
LANTXD[0]C12LANTXD[1]C11LANTXD[2]E13
ACZ_BIT_CLKC10ACZ_SYNCB9
ACZ_RST#A10
ACZ_SDIN[0]F11ACZ_SDIN[1]F10ACZ_SDIN[2]B10
ACZ_SDOC9
SATALED#AC19
SATA[0]RXNAE3SATA[0]RXPAD3SATA[0]TXNAG2SATA[0]TXPAF2
SATA[2]RXNAD7SATA[2]RXPAC7SATA[2]TXNAF6SATA[2]TXPAG6
SATA_CLKNAC2SATA_CLKPAC1
SATARBIAS#AG11SATARBIASAF11
IORDYAF16IDEIRQAB16DDACK#AB15DIOW#AC14DIOR#AE16
LAD[0]/FWH[0] P2LAD[1]/FWH[1] N3LAD[2]/FWH[2] N5LAD[3]/FWH[3] N4
LDRQ[0]# N6LDRQ[1]#/GPI[41] P4
LFRAME#/FWH[4] P3
A20GATE AF22A20M# AF23
CPUSLP# AE27
DPRSLP#/TP[4] AE24DPSLP#/TP[2] AD27
FERR# AF24
CPUPWRGD/GPO[49] AG25
IGNNE# AG26INIT3_3V# AE22
INIT# AF27INTR AG24
RCIN# AD23
NMI AF25SMI# AG27
STPCLK# AE26
THRMTRIP# AE23
DA[0] AC16DA[1] AB17DA[2] AC17
DCS1# AD16DCS3# AE17
DD[0] AD14DD[1] AF15DD[2] AF14DD[3] AD12DD[4] AE14DD[5] AC11DD[6] AD11DD[7] AB11DD[8] AE13DD[9] AF13
DD[10] AB12DD[11] AB13DD[12] AC13DD[13] AE15DD[14] AG15DD[15] AD13
DDREQ AB14
R414
8.2K_0402_5%~D
12
R8133_0402_5%~D 1 2
R8433_0402_5%~D
1 2
R438 0_0402_5%~D@12
R120 56_0402_5%~D12
C3812P_0402_50V8J~D 12
R8233_0402_5%~D
1 2
CMOS_CLR@SHORT PADS~D
11 2 2
C346 3900P_0402_50V7K~D1 2
R121 0_0402_5%~D 12
R36
10M
_040
2_5%
~D
12
R38024.9_0603_1%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LINKALERT#
SYS_RESET#
USB2P0_SMI#
ICH_BATLOW#
ICH_PCIE_WAKE#
SIO_THRM#
MCH_SYNC#
IRQ_SERIRQ
CLKRUN#
ICH_SMBCLK
GPI7
USB_OC0#USB_OC3#USB_OC1#
USBP3+
USB_OC7#
TP_NC9
USB_OC1#
DMI_RXN1
DMI_TXN0
ICH_BATLOW#
USB_OC0#
DMI_TXP3
SIO_THRM#
GPI7
SPKR
USB_OC7#USBP5-
DMI_TXN2
ICH_PCIE_WAKE#
USB_OC5#
USBP7-
CLK_PCIE_ICH#
SIO_EXT_SCI#
USB_OC6#
USB_OC2#
USBP5+
USB_OC3#
DMI_RXN0
TP_NC8
CLK_ICH_48M
PM_BMBUSY#
CLK_ICH_14M
USB_OC6#
USB_OC4#
CLK_PCIE_ICH
PLTRST#
H_STP_PCI#
MCH_SYNC#
ICH_PWRGD
USBP2+
USBP4-
ICH_SUSCLK
USBP6-
USB_OC5#
SIO_EXT_WAK#
ICH_SMLINK0
DMI_TXP1
H_STP_CPU#
DMI_RXP0
TP_NC10
IMVP_PWRGD
SIO_SLP_S3#
SYS_RESET#
LINKALERT#
CLK_ICH_48M
ICH_SMLINK1
USBP3-
DMI_RXN2
DMI_TXN1
CLK_ICH_14M
ICH_RI#
SUSPWROK
USBP6+
DMI_RXP2
DMI_TXP0
IRQ_SERIRQ
SIO_EXT_SMI#
ICH_SMLINK1
USB_OC4#
USBP2-
SIO_PWRBTN#
ICH_SMBDATA
DMI_RXP1
SIO_SLP_S5#
ICH_SMLINK0
ICH_SMBDATA
USBP4+
USB_OC2#
ICH_SMBCLK
USBP7+
DMI_TXP2
USB2P0_SMI#
DPRSLPVR
LCD_TST
CLKRUN#
TP_NC11
USBRBIAS
DMI_IRCOMP
DMI_TXN3DMI_RXP3DMI_RXN3
PLTRST_DELAY#
GPIO12
SIO_EXT_WAK# GPIO24
IDE_UAOIDE_UAI
LCD_TST_ICH
+3VSUS
+3VSUS
+3VSUS
+3VRUN
+3VRUN
+3VSUS +3VSUS
+1.5VRUN
SIO_EXT_SMI#<34>
SIO_EXT_SCI#<34>SIO_EXT_WAK#<34>
H_STP_PCI#<6>
H_STP_CPU#<6,45>
IMVP_PWRGD<10,38,45>
USBP4+ <28>USBP5- <28>
USBP3+ <31>
USBP5+ <28>
USBP4- <28>
USBP3- <31>USBP2+ <28>USBP2- <28>
USB_OC6# <28>
DMI_TXN0 <10>
DMI_TXN1 <10>
DMI_TXP0 <10>
DMI_TXP1 <10>
DMI_RXN0 <10>
DMI_RXN1 <10>DMI_RXP1 <10>
DMI_RXP0 <10>
IRQ_SERIRQ<31,34>
SIO_SLP_S3#<34>
SIO_SLP_S5#<34>
ICH_PWRGD<38>
SIO_PWRBTN#<34>
SUSPWROK<15,38>
CLK_PCIE_ICH# <6>CLK_PCIE_ICH <6>
PM_BMBUSY#<10>
SIO_THRM#<34>
ICH_PCIE_WAKE#<18,34>
USBP6+ <28>USBP7- <28>USBP7+ <28>
USBP6- <28>
USB_OC7# <28>
USB_OC5# <28>USB_OC4# <28>PLTRST#<10,21,25,34>
SPKR<26>
DMI_TXN2 <10>DMI_TXP2 <10>
DMI_TXP3 <10>
DMI_RXN2 <10>
DMI_RXN3 <10>DMI_RXP3 <10>
DMI_RXP2 <10>
CLK_ICH_14M<6>
CLK_ICH_48M<6>
DPRSLPVR<45>
ICH_SMBCLK<6>ICH_SMBDATA<6>
CLKRUN#<30,31,33,34>
LCD_TST<19,34>DMI_TXN3 <10>PLTRST_DELAY#<18>
IDE_UAI<25>IDE_UAO<25>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
ICH6(3/4)
23 51Wednesday, November 03, 2004
Compal Electronics, Inc.
(PCI Express Wake Event)
Place closely pin A27Place closely pin E10
May need pulldown for DPRSLPVR in casethe ICH6m does not set this value in timefor boot.
KAPALUA system can't boot issueDELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R12610_0402_5%~D @
12
C380
4.7P_0402_50V8C~D@
1
2
R26810K_0402_5%~D
1 2
R43
310
0K_0
402_
5%~D
12
T39 PAD~DR425
33_0402_5%~D
12
R427 24.9_0603_1%~D
1 2
R30
38.
2K_0
402_
5%~D
12
R34
110
K_04
02_5
%~D
12
T42 PAD~D
R112 10K_0402_5%~D
1 2
R11322.6_0603_1%~D
1 2
T41 PAD~D
R432 10K_0402_5%~D
1 2
R37310K_0402_5%~D
1 2
R36
310
K_04
02_5
%~D
12
R111 8.2K_0402_5%~D1 2
C1244.7P_0402_50V8C~D@
1
2
R318680_0402_5%~D
1 2
R527 0_0402_5%~D
@ 12
R29
610
K_04
02_5
%~D
12
T36PAD~D
@
R37210K_0402_5%~D
1 2
R429 10K_0402_5%~D
1 2
R35
22.
2K_0
402_
5%~D
12
R28
010
K_04
02_5
%~D
12
R2698.2K_0402_5%~D
1 2
R526 0_0402_5%~D
12
R35
12.
2K_0
402_
5%~D 1
2
RN110K_1206_8P4R_5%~D
1 82 73 64 5
PCI-EXPRESS
DIRECT MEDIA INTERFACE
USB
CLOCK
GPIO
POWER MGT
U3C
ICH6_BGA609~D
RI#T2
SATA[0]GP/GPI[26]AF17SATA[1]GP/GPI[29]AE18SATA[2]GP/GPI[30]AF18SATA[3]GP/GPI[31]AG18
SMBCLKY4SMBDATAW5LINKALERT#Y5SMLINK[0]W4SMLINK[1]U6MCH_SYNC#AG21SPKRF8
SUS_STAT#/LPCPD#W3
SYS_RESET#U2
BM_BUSY#/GPI[6]AD19
GPI[7]AE19GPI[8]R1
STP_PCI#/GPO[18]AC21
GPO[19]AB21
STP_CPU#/GPO[20]AD22
GPO[21]AD20GPO[23]AD21
GPIO[24]V3
GPIO[25]P5GPIO[27]R3GPIO[28]T3CLKRUN#/GPIO[32]AF19GPIO[33]AF20GPIO[34]AC18
WAKE#U5
SERIRQAB20
THRM#AC20
CLK14E10
CLK48A27
SUSCLKV6
SLP_S3#T4SLP_S4#T5SLP_S5#T6
PWROKAA1
DPRSLPVR/TP[1]AE20
LAN_RST#V5
BATLOW#/TP[0]V2
PWRBTN#U1
VRMPWRGDAF21
RSMRST#Y3
PERn[1] H25PERp[1] H24PETn[1] G27PETp[1] G26
PERn[2] K25PERp[2] K24PETn[2] J27PETp[2] J26
SMBALERT#/GPI[11]W6
GPI[12]M2GPI[13]R6
PERn[3] M25PERp[3] M24PETn[3] L27PETp[3] L26
PERn[4] P24PERp[4] P23PETn[4] N27PETp[4] N26
DMI[0]RXN T25DMI[0]RXP T24DMI[0]TXN R27DMI[0]TXP R26
DMI[1]RXN V25DMI[1]RXP V24DMI[1]TXN U27DMI[1]TXP U26
DMI[2]RXN Y25DMI[2]RXP Y24DMI[2]TXN W27DMI[2]TXP W26
DMI[3]RXN AB24DMI[3]RXP AB23DMI[3]TXN AA27DMI[3]TXP AA26
DMI_CLKN AD25DMI_CLKP AC25
DMI_ZCOMP F24
DMI_IRCOMP F23
OC[4]#/GPI[9] C23OC[5]#/GPI[10] D23OC[6]#/GPI[14] C25OC[7]#/GPI[15] C24
OC[0]# C27OC[1]# B27OC[2]# B26OC[3]# C26
USBP[0]N C21USBP[0]P D21USBP[1]N A20USBP[1]P B20USBP[2]N D19
USBP[3]N A18USBP[3]P B18USBP[4]N E17USBP[4]P D17
USBP[5]P A16USBP[5]N B16
USBP[6]N C15USBP[6]P D15USBP[7]N A14USBP[7]P B14
USBP[2]P C19
USBRBIAS# A22USBRBIAS B22
R428 10K_0402_5%~D@1 2
RN2910K_1206_8P4R_5%~D
1 82 73 64 5
R43
1
1K_0
402_
5%~D
@
12
R539 0_0402_5%~D@1 2
R37910_0402_5%~D@
12
T40 PAD~D
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH6_VCCPLL
ICH6_VCCPLL
ICH_V5REF_SUS
ICH_V5REF_SUS
ICH_V5REF_RUN
ICH_V5REF_RUN
ICH_V5REF_RUN
+1.5VRUN_L
ICH_V5REF_SUS
+3VSUS
+1.5VRUN
+1.5VRUN
+VCCP
+3VSUS
+1.5VRUN
+1.5VRUN
+3VRUN
+1.5VSUS
+1.5VRUN
+1.5VRUN
+1.5VRUN+3VSUS
+1.5VRUN
+3VRUN
+3VSUS
+RTC_CELL
+3VRUN
+3VRUN
+RTC_CELL+3VRUN
+5VSUS
+5VALW
+1.5VRUN
+1.5VSUS
+1.5VRUN
+2.5VRUN
+3VRUN
+3VRUN+5VRUN
+3VSUS+5VSUS
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
ICH6(4/4)
24 51Monday, October 18, 2004
Compal Electronics, Inc.
Near PIN AG5
Near PIN AG9
Near PIN AE1
Near PINE26, E27
Near PINAB27
Near PIN AG10
Near PIN F27(C453),P27(C459), AB27(C454)
Near PIN A25
Near PIN U7
Near PIN A24
Near PIN AA19
Near PIN AG23
Near PIN AB18
Near PINA2-A6, D1-H1
Near PINAG13, AG16
Near PIN A17
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C33
8
0.1U
_040
2_16
V4Z~
D
1
2
C41
2
0.1U
_040
2_16
V4Z~
D
1
2
R42610_0402_5%~D @
1 2
C4080.1U_0402_16V4Z~D
1 2
C36
9
0.1U
_040
2_16
V4Z~
D
1
2
R442
1_0603_5%~D
1 2
C46
10.
1U_0
402_
16V4
Z~D
1
2
C4220.1U_0402_16V4Z~D
1 2
C32
80.
1U_0
402_
16V4
Z~D
1
2
D16RB751V_SOD323~D
21
C3700.1U_0402_16V4Z~D
1
2
C4360.1U_0402_16V4Z~D
1
2
C3820.1U_0402_16V4Z~D
@
1 2
C3860.1U_0402_16V4Z~D
1 2
C3940.1U_0402_16V4Z~D
1 2
C45
4
0.1U
_040
2_16
V4Z~
D
1
2
R535100_0402_5%~D
12
C3751U_0603_10V4Z~D
1
2
L42BLM11A601S_0603~D
1 2
C33
70.
1U_0
402_
16V4
Z~D
1
2
C40
5
0.1U
_040
2_16
V4Z~
D
1
2
C45
3
0.1U
_040
2_16
V4Z~
D
1
2
C4440.1U_0402_16V4Z~D
1 2
C34
70.
1U_0
402_
16V4
Z~D
1
2
C3780.1U_0402_16V4Z~D
1 2
C4070.1U_0402_16V4Z~D
1 2
C42
30.
1U_0
402_
16V4
Z~D
1
2
C4100.1U_0402_16V4Z~D
1 2
C38
8
0.1U
_040
2_16
V4Z~
D
1
2
R40710_0402_5%~D@
1 2
C36
50.
1U_0
402_
16V4
Z~D
1
2
PCIE
CORE
IDE
PCI
USB
SATA
USB CORE
PCI/IDE RBP
U3E
ICH6_BGA609~D
VCC1_5[1]AA22VCC1_5[2]AA23VCC1_5[3]AA24VCC1_5[4]AA25VCC1_5[5]AB25VCC1_5[6]AB26VCC1_5[7]AB27VCC1_5[8]F25VCC1_5[9]F26VCC1_5[10]F27VCC1_5[11]G22VCC1_5[12]G23VCC1_5[13]G24VCC1_5[14]G25VCC1_5[15]H21VCC1_5[16]H22VCC1_5[17]J21VCC1_5[18]J22VCC1_5[19]K21VCC1_5[20]K22VCC1_5[21]L21VCC1_5[22]L22VCC1_5[23]M21VCC1_5[24]M22VCC1_5[25]N21VCC1_5[26]N22VCC1_5[27]N23VCC1_5[28]N24VCC1_5[29]N25VCC1_5[30]P21VCC1_5[31]P25VCC1_5[32]P26VCC1_5[33]P27VCC1_5[34]R21VCC1_5[35]R22VCC1_5[36]T21VCC1_5[37]T22VCC1_5[38]U21VCC1_5[39]U22VCC1_5[40]V21VCC1_5[41]V22VCC1_5[42]W21VCC1_5[43]W22VCC1_5[44]Y21VCC1_5[45]Y22
VCC1_5[46]AA6VCC1_5[47]AB4VCC1_5[48]AB5VCC1_5[49]AB6VCC1_5[50]AC4VCC1_5[51]AD4VCC1_5[52]AE4VCC1_5[53]AE5VCC1_5[54]AF5VCC1_5[55]AG5
VCC1_5[56]AA7VCC1_5[57]AA8VCC1_5[58]AA9VCC1_5[59]AB8VCC1_5[60]AC8VCC1_5[61]AD8VCC1_5[62]AE8VCC1_5[63]AE9VCC1_5[64]AF9VCC1_5[65]AG9
VCCDMIPLLAC27VCC3_3[1]E26
VCCSATAPLLAE1VCC3_3[22]AG10
VCCLAN3_3/VCCSUS3_3[1]A13VCCLAN3_3/VCCSUS3_3[2]F14VCCLAN3_3/VCCSUS3_3[3]G13VCCLAN3_3/VCCSUS3_3[4]G14
VCCSUS3_3[1]A11VCCSUS3_3[2]U4VCCSUS3_3[3]V1VCCSUS3_3[4]V7VCCSUS3_3[5]W2VCCSUS3_3[6]Y7
VCCSUS3_3[7]A17VCCSUS3_3[8]B17VCCSUS3_3[9]C17VCCSUS3_3[10]F18VCCSUS3_3[11]G17VCCSUS3_3[12]G18
VCC1_5[98] F9VCC1_5[97] U17VCC1_5[96] U16VCC1_5[95] U14
VCC1_5[93] U11VCC1_5[94] U12
VCC1_5[92] T17VCC1_5[91] T11VCC1_5[90] P17VCC1_5[89] P11VCC1_5[88] M17VCC1_5[87] M11VCC1_5[86] L17VCC1_5[85] L16VCC1_5[84] L14VCC1_5[83] L12VCC1_5[82] L11VCC1_5[81] AA21VCC1_5[80] AA20VCC1_5[79] AA19
VCC3_3[21] AA10VCC3_3[20] AG19VCC3_3[19] AG16VCC3_3[18] AG13VCC3_3[17] AD17VCC3_3[16] AC15VCC3_3[15] AA17VCC3_3[14] AA15VCC3_3[13] AA14VCC3_3[12] AA12
VCC3_3[11] P1VCC3_3[10] M7
VCC3_3[9] L7VCC3_3[8] L4VCC3_3[7] J7VCC3_3[6] H7VCC3_3[5] H1VCC3_3[4] E4VCC3_3[3] B1VCC3_3[2] A6
VCCSUS1_5[3] U7VCCSUS1_5[2] R7
VCCSUS1_5[1] G19
VCC1_5[78] G20VCC1_5[77] F20VCC1_5[76] E24VCC1_5[75] E23VCC1_5[74] E22VCC1_5[73] E21VCC1_5[72] E20VCC1_5[71] D27VCC1_5[70] D26VCC1_5[69] D25VCC1_5[68] D24
VCC1_5[67] G8
VCC2_5[2] P7VCC2_5[4] AB18
V5REF[2] AA18V5REF[1] A8
V5REF_SUS F21
VCCUSBPLL A25VCCSUS3_3[20] A24
VCCRTC AB3
VCCLAN1_5/VCCSUS1_5[2] G11VCCLAN1_5/VCCSUS1_5[1] G10
V_CPU_IO[3] AG23V_CPU_IO[2] AD26V_CPU_IO[1] AB22
VCCSUS3_3[19] G16VCCSUS3_3[18] G15VCCSUS3_3[17] F16VCCSUS3_3[16] F15VCCSUS3_3[15] E16VCCSUS3_3[14] D16VCCSUS3_3[13] C16
R53710_0402_5%~D
12
C44
90.
1U_0
402_
16V4
Z~D
1
2
C41
10.
01U
_040
2_16
V7K~
D
1
2
C44
20.
1U_0
402_
16V4
Z~D
1
2
C33
9
0.1U
_040
2_16
V4Z~
D
1
2
C37
2
0.1U
_040
2_16
V4Z~
D
1
2
+
C15
1
150U
_D2_
2VM
_R15
~D
1
2
D17RB751V_SOD323~D
21
C4090.1U_0402_16V4Z~D
1 2
U3D
ICH6_BGA609~D
VSS[86] F4VSS[85] F22VSS[84] F19VSS[83] F17
VSS[81] E19VSS[82] E25
VSS[80] E18VSS[79] E15VSS[78] E14
VSS[76] D22VSS[75] D20VSS[74] D18VSS[73] D14VSS[72] D13VSS[71] D10VSS[70] D1VSS[69] C4VSS[68] C22VSS[67] C20VSS[66] C18VSS[65] C14VSS[64] B25VSS[63] B24VSS[62] B23VSS[61] B21VSS[60] B19VSS[59] B15VSS[58] B13VSS[57] AG7VSS[56] AG3VSS[55] AG22VSS[54] AG20VSS[53] AG17VSS[52] AG14VSS[51] AG12VSS[50] AG1VSS[49] AF7VSS[48] AF3VSS[47] AF26VSS[46] AF12VSS[45] AF10VSS[44] AF1VSS[43] AE7VSS[42] AE6VSS[41] AE25VSS[40] AE21VSS[39] AE2VSS[38] AE12VSS[37] AE11VSS[36] AE10VSS[35] AD6VSS[34] AD24VSS[33] AD2VSS[32] AD18VSS[31] AD15
VSS[29] AD1VSS[30] AD10
VSS[28] AC6VSS[27] AC3VSS[26] AC26VSS[25] AC24VSS[24] AC23VSS[23] AC22VSS[22] AC12VSS[21] AC10VSS[20] AB9VSS[19] AB7VSS[18] AB2VSS[17] AB19VSS[16] AB10VSS[15] AB1VSS[14] AA4VSS[13] AA16VSS[12] AA13VSS[11] AA11VSS[10] A9
VSS[9] A7VSS[8] A4VSS[7] A26VSS[6] A23VSS[5] A21VSS[4] A19VSS[3] A15VSS[2] A12VSS[1] A1
VSS[172]E27VSS[171]Y6VSS[170]Y27VSS[169]Y26VSS[168]Y23VSS[167]W7VSS[166]W25VSS[165]W24VSS[164]W23VSS[163]W1VSS[162]V4VSS[161]V27VSS[160]V26VSS[159]V23VSS[158]U25VSS[157]U24VSS[156]U23VSS[155]U15VSS[154]U13VSS[153]T7VSS[152]T27VSS[151]T26VSS[150]T23VSS[149]T16VSS[148]T15VSS[147]T14VSS[146]T13VSS[145]T12VSS[144]T1VSS[143]R4VSS[142]R25VSS[141]R24VSS[140]R23VSS[139]R17VSS[138]R16VSS[137]R15VSS[136]R14VSS[135]R13VSS[134]R12VSS[133]R11VSS[132]P22VSS[131]P16VSS[130]P15VSS[129]P14VSS[128]P13VSS[127]P12VSS[126]N7VSS[125]N17VSS[124]N16VSS[123]N15VSS[122]N14VSS[121]N13VSS[120]N12VSS[119]N11VSS[118]N1VSS[117]M4VSS[116]M27VSS[115]M26VSS[114]M23VSS[113]M16VSS[112]M15VSS[111]M14VSS[110]M13VSS[109]M12VSS[108]L25VSS[107]L24VSS[106]L23VSS[105]L15VSS[104]L13VSS[103]K7VSS[102]K27VSS[101]K26VSS[100]K23VSS[99]K1VSS[98]J4VSS[97]J25VSS[96]J24VSS[95]J23VSS[94]H27VSS[93]H26VSS[92]H23VSS[91]G9VSS[90]G7VSS[89]G21VSS[88]G12
VSS[77] D7
VSS[87]G1C3930.1U_0402_16V4Z~D
1 2
C3760.1U_0402_16V4Z~D
1 2
C36
1
0.1U
_040
2_16
V4Z~
D
1
2
L41
BLM21PG600SN1D_0805~D1 2
C4520.01U_0402_16V7K~D
1 2
C45
9
0.1U
_040
2_16
V4Z~
D
1
2
C3920.1U_0402_16V4Z~D
1 2
C3710.1U_0402_16V4Z~D
1
2C387
0.1U_0402_16V4Z~D
1 2
C40
6
0.1U
_040
2_16
V4Z~
D
1
2
C374
0.1U_0402_16V4Z~D
1 2
C4201U_0603_10V4Z~D
1
2
C3770.1U_0402_16V4Z~D
1 2
C4240.01U_0402_16V7K~D
1 2
C45
80.
01U
_040
2_16
V7K~
D
1
2
C35
3
0.1U
_040
2_16
V4Z~
D
1
2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
IDE_HDD0IDE_HDD1IDE_HDD2IDE_HDD3IDE_HDD4IDE_HDD5IDE_HDD6IDE_HDD7IDE_HDD8IDE_HDD9IDE_HDD10IDE_HDD11IDE_HDD12IDE_HDD13IDE_HDD14IDE_HDD15
IDE_HDA0IDE_HDA1IDE_HDA2IDE_HCS0#IDE_HCS1#
IDE_HINTRQIDE_HDMACK#IDE_HIORDYIDE_HDIOR#IDE_HDIOW#IDE_HDREQIDE_R_HRESET#
IDE_XTLINIDE_XTLOUT_R
CNFG2CNFG1CNFG0IDE_HDD7 IDE_HDD8
IDE_HDD6IDE_HDD5IDE_HDD4 IDE_HDD11IDE_HDD3 IDE_HDD12IDE_HDD2 IDE_HDD13IDE_HDD1 IDE_HDD14IDE_HDD0 IDE_HDD15
IDE_HDA1IDE_HDA0 IDE_HDA2IDE_HCS0#
IDE_HDMACK#
IDE_HDREQ
IDE_HRESET#
IDE_HDIOW#IDE_HDIOR#IDE_HIORDY
IDE_HINTRQ
SEC_CSEL
IDE_HDD10IDE_HDD9
IDE_HCS1#
CNFG2CNFG1
ATAIOSEL
PLTRST#
ATAIOSEL
T0
IDE_HIORDY
SATA_RXP0SATA_RXN0SATA_TXP0SATA_TXN0
T3
IDE_HINTRQ
SATA_RXN0
SATA_RXP0 SATA_RXP0_C
SATA_RXN0_C
IDE_DA2IDE_DA0IDE_DCS3#IDE_DCS1#
IDE_DA1IDE_IRQ
IDE_DIOW#IDE_DIORDY
IDE_DIOR#IDE_DDREQ
IDE_RST_MOD
RPDDACK#
PDIAG#
PRI_CSEL
IDE_DD[0..15]
IDE_DIORDY
RPDDACK#
IDE_LED#
IDE_DD14
IDE_DD12IDE_DD11IDE_DD10
IDE_DD13
IDE_DD15
IDE_DD7IDE_DD6
IDE_DD9
IDE_DD4
IDE_DD8
IDE_DD5
IDE_DD3
IDE_DD1IDE_DD2
IDE_DD0
IDE_ACT#
IDE_HIOCS16#
IDE_HIOCS16#
IDE_HDREQ
T1T2
T5T6
T0
T3
T2
T6
T1
IDE_HRESET#
IDE_XTLOUTIDE_XTLIN
CNFG0
IDE_XTLOUT_R
PWR_VAA
PWR_VAAIDE_DD[0..15]<22>
+1.8VRUN
+5VHDD+5VHDD
+3VRUN +3VRUN +3VRUN
+5VHDD+3VRUN
+5VMOD
+5VMOD+5VMOD
+3VRUN
+5VMOD
+5VMOD
+1.8VRUN
+5VHDD
+5VMOD
+3VRUN
+3VRUN +3VRUN
PLTRST# <10,21,23,34>
SATA_TXP0 <22>SATA_TXN0 <22>
SATA_RXN0_C <22>
SATA_RXP0_C <22>IDE_DCS1#<22> IDE_DCS3# <22>IDE_DA0<22>IDE_DA1<22>
IDE_DA2 <22>
IDE_DDACK#<22>
IDE_IRQ<22>
IDE_DIOW#<22>IDE_DIORDY<22>
IDE_DIOR# <22>IDE_DDREQ <22>
IDE_RST_MOD<34>
IDE_UAO<23>IDE_UAI<23>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
SATA Bridge
25 51Monday, October 18, 2004
Compal Electronics, Inc.
HDD Connector
CNFG0CNFG2 CNFG1Sets maximum transfer rate and UDMA mode
Device Mode 100MB/s
Device Mode 133MB/s
Device Mode 150MB/s
Host Mode 100MB/s
Host Mode 133MB/s
Host Mode 150MB/s
0 1 1 Reserved
1 1 1 Reserved
Place near connector side.
CD-ROM Connector
NOTE
0 0 0
0 0 1
0 1 0
1 0 01 10
1 1 0
INT PDINT PD
*
Pleace near HD CONN Pleace near U178
25MHz reference clock T[4:3] = 01
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C545
1U_0603_10V4Z~D
1
2
Parallel ATA
UART
SATA
Config & Debug
Power
U11
88SA8040_TQFP64~D
HDD062HDD164
HDD35 HDD22
HDD47HDD511HDD613HDD715HDD814HDD912HDD1010HDD116HDD123
TX_P 32TX_M 31RX_P 27
HDD1463
RX_M 28
HDD1561
RST# 17T0 33T1 34T2 35T3 36T4 37T5 38T6 39T7 40
CNFG2 20CNFG1 19CNFG0 18
ATAIOSEL 21
XTLIN/OSC 22XTLOUT 23
ISET 26VDDIO_0 4VDDIO_1 44
VDD_0 9VDD_1 41VDD_2 56
VAA1 24VAA2 29
VSS2 30GND_0 8GND_1 42GND_2 57
HDA050HDA151HDA249HCS0#48HCS1#47
HIOCS16#52HINTRQ53HDMACK#54HIORDY55HDIOR#58HDIOW#59HDMARQ60HRESET#16HPDIAG#46
UAO45UAI43
VSS1 25
HDD131
C559
1U_0603_10V4Z~D
1
2
R2041M_0402_5%~D@
12
R513100K_0402_5%~D
1 2
R512 4.7K_0402_5%~D1 2
C28
20.
1U_0
402_
16V4
Z~D1
2
R18310K_0402_5%~D
12
C274
10U_0805_10V4M~D
1
2
C5560.1U_0402_16V4Z~D
1 2
C544
0.1U_0402_16V4Z~D
1
2
C27
10.
1U_0
402_
16V4
Z~D
1
2
C551
1U_0603_10V4Z~D
1
2
R210 5.6K_0402_5%~D12
Y3
25MHZ_30P_1XSA025000AVH~D
OUT3
GND2
VDD 4
OE 1
R179 10K_0402_5%~D@1 2
C28
14.
7U_0
805_
10V4
Z~D
1
2
C25
80.
1U_0
402_
16V4
Z~D1
2
R21110K_0402_5%~D@
12
R21210K_0402_5%~D
12
C555
0.1U_0402_16V4Z~D
1
2
C25
64.
7U_0
805_
10V4
Z~D 1
2
R177 10K_0402_5%~D 1 2
C27
912
P_0
402_
50V8
J~D
@
1
2
R180 10K_0402_5%~D@1 2
R203 10K_0402_5%~D@1 2
PJP19
@PAD-OPEN 4x4m
1 2
R508 10K_0402_5%~D @
1 2
C26
02.
2U_0
805_
6.3V
6K~D
1
2
C2623900P_0402_50V7K~D12
R18210K_0402_5%~D
1 2
C54
310
00P_
0402
_50V
7K~D
1
2
R214 33_0402_5%~D
1 2
C55047P_0402_50V8J~D
1 2
C278
0.1U_0402_16V4Z~D
1
2
R192 4.7K_0402_5%~D1 2
R20510K_0402_5%~D@
12
R50
551
0_04
02_5
%~D
@
12
R21310K_0402_5%~D @
12
C2703900P_0402_50V7K~D12
R20710K_0402_5%~D@
12
R516470_0402_5%~D
12
C28012P_0402_50V8J~D@
1
2
PJP20
@PAD-OPEN 4x4m
1 2
R514 510_0402_5%~D1 2
R191 10K_0402_5%~D12
JHDD
FOX_HH99223-SA_REVERS~D
113355779911111313151517171919212123232525272729293131333335353737393941414343
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 44
R181 10K_0402_5%~D@1 2
C553
0.1U_0402_16V4Z~D
1
2
R20610K_0402_5%~D@
12
R19
00_
0402
_5%
~D
@
12
C54
20.
1U_0
402_
16V4
Z~D
1
2
R511470_0402_5%~D1 2
R178 10K_0402_5%~D 1 2
R186
12.1K_0603_1%~D12
C552
1000P_0402_50V7K~D
1
2
JMOD
SUYIN_80095AR-050G1T~D
113355779911111313151517171919212123232525272729293131333335353737393941414343454547474949
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 50
L20
BLM31A260SPT_1206~D1 2
C554
1000P_0402_50V7K~D
1
2
Y1
25MHZ_20P_1BG25000CK1A
@1 2
C259
0.1U_0402_16V4Z~D
1
2
C27
710
00P_
0402
_50V
7K~D
1
2
R509 10K_0402_5%~D
1 2
C557
10U_0805_10V4M~D
1
2
C27
20.
01U
_040
2_16
V7K~
D
1
2
R187 10K_0402_5%~D1 2
R510 22_0402_5%~D1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_SDOUT_AUDIO
ICH_RST_AUDIO#
AC97VREFI
R_ICH_AC_BITCLK
CAP2
SPK_SHUTDOWN#
HP_OUT_R
R_ICH_AC_SDIN0
EAPD
HP_COMM
VREFOUT
ICH_SDOUT_AUDIO
AFLT2
ICH_SYNC_AUDIO
AUDIO_AVDD_ON TPS793475_BYPASS
AFLT1
XTL_24M+
HP_OUT_L
9750_PHONE
PC_BEEP
XTL_24M-
CLK_CODEC_14M
Z2402
Z2401
Z2404Z2403 PC_BEEP
ICH_RST_AUDIO#
ICH_SDOUT_AUDIO
ICH_SYNC_AUDIO
LINE_IN_L
CNB_MICIN
LINE_IN_R
+3VRUN
+VDDA
+VDDA+5VSUS
+3VRUN
+3VRUN
+VDDA
+VDDA
ICH_RST_AUDIO#<22>
AUD_LINE_OUT_L <27>
SPK_SHUTDOWN#<27>
ICH_AC_SDIN0<22>
EAPD<27>
ICH_SDOUT_AUDIO<22>
MDC_AC_BITCLK<29>
EMICIN <27>
ICH_SYNC_AUDIO<22>
AUD_LINE_OUT_R <27>
AUDIO_AVDD_ON<35>
HP_OUT_R <27>
ICH_AC_BITCLK<22>
HP_OUT_L <27>
CLK_CODEC_14M<6>
BEEP<34>
SPKR<23>
EMICIN <27>
EXTMIC_BIAS <27>
CBS_SPK<31>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
AC97 Codec
26 51Monday, October 18, 2004
Compal Electronics, Inc.
PACKAGE : 8X4.5X1.5mm
W=30 mil
+VDDA=3.3V
Pin46CID1
Pin3XTL_OUTCLOCK SOURCE
Pin45CID0
GND
GND
GND
GND
OPENOPEN
OPEN
OPEN
1K
1K1K
1K
14.318 MHz
27 MHz
48 MHz
24.576 MHz
Place closely pin 5
Pop C491 for Crystal,Pop R153 for CLK input
Place closely pin 2
Noise Concem, pop it.
TRACE>15 mil
45
2
single gate TTL
31
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C48
61U
_060
3_10
V4Z~
D@
1
2
C49
80.
1U_0
402_
16V4
Z~D
@
1
2
C50110P_0402_50V8J~D@
1 2
R49610K_0402_5%~D 1 2
C510 1U_0603_10V4Z~D@1 2
C5110.33U_0603_10V7K~D
1 2
C49522P_0402_50V8J~D @
1
2
C18
11U
_060
3_10
V4Z~
D
1
2
C49
20.
01U
_040
2_16
V7K~
D @
1
2
C48422P_0402_50V8J~D @
1
2
C5181000P_0402_50V7K~D @1
2
R16033_0402_5%~D
1 2
R1530_0402_5%~D
12
R4760_0402_5%~D
1 2
C17
60.
1U_0
402_
16V4
Z~D
1
2
L47
BLM31A260SPT_1206~D
1 2
C512 1U_0603_10V4Z~D@ 1 2
R5280_0402_5%~D@
1 2
C491
22P_0402_50V8J~D@
12
C490
22P_0402_50V8J~D@
12
C1891000P_0402_50V7K~D
1
2
R47233_0402_5%~D @
12
R4851K_0402_5%~D@1 2
C5250.1U_0402_16V4Z~D
1 2R48610K_0402_5%~D
1 2
C50
50.
047U
_040
2_16
V4Z~
D
1
2
C1791000P_0402_50V7K~D
1
2
C194 1000P_0402_50V7K~D 1 2
U28ASN74LVC2G86DCTR_SSOP8~D
1A1
1B2 G4
1Y 7
P8
X524.576MHz_16P_3XG-24576-43E1@1
2
C20
00.
1U_0
402_
16V4
Z~D
1
2
R150
0_0402_5%~D
12
C196 0.1U_0402_16V4Z~D
@ 1 2
R4841K_0402_5%~D@
1 2R
529
0_04
02_5
%~D
1
2
C52
40.
1U_0
402_
16V4
Z~D
1
2
C191 1000P_0402_50V7K~D 1 2
C16
90.
1U_0
402_
16V4
Z~D
1
2
U28BSN74LVC2G86DCTR_SSOP8~D
2A5
2B6 G4
2Y 3
P8
C5260.1U_0402_16V4Z~D
1 2
C49
9
27P_
0402
_50V
8J
@
1
2
C20
12.
2U_0
805_
6.3V
6K~D
1
2
U30
NC7SZ04P5X_SC70-5~D
A2 Y 4
P5
NC
1
G3
C5390.1U_0402_16V4Z~D
1
2
C50
3
27P_
0402
_50V
8J
@
1
2
C50
60.
1U_0
402_
16V4
Z~D
1
2
C50710P_0402_50V8J~D@
1 2
L48BLM11A121S_0603~D
12
R53
00_
0402
_5%
~D
12
C50
02.
2U_0
805_
6.3V
6K~D
1
2
STAC9751
U10
STAC9751TG_TQFP48~D
PC_BEEP 12
PHONE 13
AUX_L 14
AUX_R 15
VIDEO_L 16
VIDEO_R 17
CD_L 18
CD_GND 19
CD_R 20
MIC1 21
MIC2 22
LINE_IN_L 23
LINE_IN_R 24SDATA_OUT5
BIT_CLK6
SDATA_IN8
SYNC10 RESET#11
XTL_IN2
XTL_OUT3
LOUT_L 35
LOUT_R 36
MONO_OUT 37
CID045 CID146
GPIO0/NC43
GPIO1/NC44
HP_OUT_L 39
HP_COMM 40
HP_OUT_R 41
EAPD47
NC/FLTOUT34
NC/FLTIN33
CAP232
NC/BPCFG31
AFLT230
AFLT129
VREFOUT28
VREF27D
VDD
11
DVD
D2
9
AVD
D1
25AV
DD
238
DVS
S14
DVS
S27
AVSS
126
AVSS
242
SPDIF48
C52
30.
1U_0
402_
16V4
Z~D
@
1
2
C51
3
27P_
0402
_50V
8J
@
1
2
C48
72.
2U_0
805_
6.3V
6K~D
1
2
R1628.2K_0402_5%~D@
12
R48847_0402_5%~D @
12
R15533_0402_5%~D
1 2
C51610P_0402_50V8J~D@
1 2
U22
TPS793333DBVR_SOT23-5~D@
IN1 OUT 5
GND2
EN3 BYPASS 4
C5290.1U_0402_16V4Z~D
1 2
R15733_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AUD_GAIN0
AUD_GAIN1
HP_NB_SENSE
SPK_SHUTDOWN#
HP_NB_SENSE
AUD_LINE_IN_R
AUD_LINE_IN_L
HP_SPK_L1
HP_SPK_R1
INT_SPK_R2INT_SPK_L1
INT_SPK_R1
INT_SPK_L2
+5VAMPVCC
BYPASS
AUD_GAIN0
AUD_GAIN1
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
EXTMIC_BIAS
EMICIN_R
HP_SPK_L2
EMIC_IN
HP_SPK_R2
+5VAMPVCC
+3VRUN
+VDDA
+VDDA
+5VRUN
+5VSUS
+5VAMPVCC
NB_MUTE<34>
SPK_SHUTDOWN#<26>
EAPD<26>
HP_OUT_L<26>
HP_OUT_R<26>
AUD_LINE_OUT_R<26>
AUD_LINE_OUT_L<26>
EMICIN<26>
HP_NB_SENSE<34>
EXTMIC_BIAS<26>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
AMP and PHONE JACK
27 51Monday, October 18, 2004
Compal Electronics, Inc.
LINE OUT
Gain Setting
GAIN0 INPUTAV(inv)GAIN1
21.6dB
15.6dB
6dB
1
0
10dB
25K ohm
45K ohm
70K ohm
90K ohm
IMPEDANCE
11
0
0
0
*
1
Speaker Connector
15 mils trace
W=40mils
Will Change to 3W per channel device (TPA2008D2)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C10
9
100P
_040
2_50
V8J~
D
1
2
R132100K_0402_5%~D
12
C1472.2U_0603_6.3V6K~D
1 2
L15BLM11A121S_0603~D
12
C17
710
0P_0
402_
50V8
J~D
1
2
R17010K_0402_5%~D@
12
L45
BLM21AF121SN1D_0805~D
1 2
L17BLM11A121S_0603~D
12
C1482.2U_0603_6.3V6K~D 1 2
C48510U_0805_10V4M~D
1
2
C1461U_0603_10V4Z~D
1
2
C537
0.47U_0603_16V4Z~D
1
2
JAUDIO
FOX_JA8333L-2ST-FR~D
A2
A3
A4
A5
A6
B2B6
B3
B4
B5
7 8 9 10
A1
B1
11
G
D
S Q152N7002_SOT23~D
2
13
C1141U_0603_10V4Z~D
1
2
C56
80.
1U_0
402_
16V4
Z~D
@
1
2
C5330.1U_0402_16V4Z~D@
1
2
R136100_0402_5%~D
1 2R149
2K_0402_5%~D 1 2
R156
100K_0402_5%~D
12
L16BLM11A121S_0603~D
12
U5
MAX4411ETP-T_TQFN20~D
C1P1
PGN
D2
C1N3
NC-4 4
PVss
5
NC-6 6
SVss
7
NC-8 8
OUTL 9
SVD
D10
INR15
SHDNR#14
INL13
NC-12 12
OUTR 11
NC-20 20
PVD
D19
SHDNL#18
SGN
D17
NC-16 16
C15
310
0P_0
402_
50V8
J~D
1
2
C56
50.
1U_0
402_
16V4
Z~D
@
1
2
C536
0.1U_0603_50V4Z~D
1 2
C4940.1U_0402_16V4Z~D
1
2
R17110K_0402_5%~D@
12
C1131U_0603_10V4Z~D
1
2
C15
74.
7U_0
805_
10V4
Z~D
1
2
C199
0.1U_0805_25V7K~D
1 2
R1431K_0402_5%~D
12
U27
TPA6017A2PWPR_TSSOP20~D
GN
D4
1G
ND
311
GN
D2
13G
ND
120
VDD
16PV
DD
115
RIN-17
BYPASS 10
NC 12
LOUT- 8
LOUT+ 4
ROUT- 14
ROUT+ 18
RIN+7
LIN-5
LIN+9
GAIN0 2
GAIN1 3
PVD
D2
6
SHUTDOWN19
C206
0.1U_0805_25V7K~D
1 2
G
D
S Q422N7002_SOT23~D
2
13
C535
0.1U_0603_50V4Z~D
1 2
C56
60.
1U_0
402_
16V4
Z~D
@
1
2
C56
70.
1U_0
402_
16V4
Z~D
@
1
2
C15
410
0P_0
402_
50V8
J~D
1
2
C10
8
100P
_040
2_50
V8J~
D
1
2
G
D
S Q432N7002_SOT23~D
2
13
L19BLM11A121S_0603~D
12
C5340.1U_0402_16V4Z~D
1
2
R16510K_0402_5%~D
12
R16410K_0402_5%~D
12
JSPK
MOLEX_53398-0490~D
112233445566
C16
310
0P_0
402_
50V8
J~D
1
2
C5020.1U_0402_16V4Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CBS_CAD15_L
USBP2_D-
USBP2_D+
USBP4_D-
USBP4_D+
USBP5_D-
USBP5_D+
USBP6_D-
USBP6_D+
USBP7_D-
USBP7_D+
USBP4_D+USBP4_D-
USBP5_D-USBP5_D+
USBP4_GND
USBP5_VCC
USBP5_GND
USBP4_VCC
USBP6_GND
USBP7_GND
USBP6_VCC
USBP7_VCC
USB_OC4#
USB_OC7#
USB_OC6#
USB_OC5#
USB_SIDE_EN#
USB_BACK_EN#
CBS_CAD13_L
USBP7_D-USBP7_D+
USBP6_D+USBP6_D-
USBP4_PWR
USBP5_PWR
USBP4_PWR USBP5_PWR
+5VSUS
+5VSUS
USBP6_PWRUSBP7_PWR
USBP6_PWR
USBP7_PWR
USBP2-<23>
USBP5-<23>
USBP5+<23>
USBP4-<23>
USBP4+<23>
USBP2+<23>
USBP6-<23>
USBP6+<23>
USBP7-<23>
USBP7+<23>
USB_OC4# <23>
USB_OC7# <23>
USB_OC6# <23>
USBP2_D+ <29>
USBP2_D- <29>
USB_OC5# <23>USB_BACK_EN#<34>
USB_SIDE_EN#<34>
CBS_CAD15_L <32>
CBS_CAD13_L <32>CBS_CAD13<31>
CBS_CAD15<31>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
USB 2.0 Port
28 51Monday, October 18, 2004
Compal Electronics, Inc.
23 NEW Connector
BlueTooth1
4
Reserve
JUSB1(UP)
USB PORT#
0
DESTINATION
JUSB1(LOW)5
7 JUSB2(UP)6 JUSB2(LOW)
Reserve
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R5200_0402_5%~D 1 2
JUSB1
FOX_UB11123-8Z1-TR~D
A_VCCA1A_D-A2A_D+A3A_GNDA4
B_VCCB1B_D-B2B_D+B3B_GNDB4
G19G210G311G412
R14
0_0805_5%~D
1 2
+
C78
150U
_D_6
.3V
M_R
55~D
@
1
2
R280_0402_5%~D 1 2
R2180_0402_5%~D 1 2
C34210U_0805_10V4M~D
1
2
C90
0.1U
_040
2_16
V4Z~
D
1
2
R550_0402_5%~D 1 2
+
C66
150U
_D_6
.3V
M_R
55~D
1
2
R560_0402_5%~D 1 2
+
C18
150U
_D_6
.3V
M_R
55~D
1
2
+
C28
815
0U_D
_6.3
VM
_R55
~D
@
1
2
R96
0_0805_5%~D
1 2
R270_0402_5%~D 1 2
C29
20.
1U_0
402_
16V4
Z~D
1
2
R290_0402_5%~D 1 2
U14
TPS2062DR_SO8~D
GND1IN2EN1#3EN2#4
OC1# 8OUT1 7OUT2 6OC2# 5
L7 DLW21SN900SQ2_0805~D@11
44 3 3
2 2
R109
0_0805_5%~D
1 2
R660_0402_5%~D 1 2
L51 DLW21SN900SQ2_0805~D@ 11
44 3 3
2 2
L8 DLW21SN900SQ2_0805~D@11
44 3 3
2 2
R5190_0402_5%~D 1 2
C1310U_0805_10V4M~D
1
2
PJP
21P
AD
-OP
EN
4x4
m 12
C19
0.1U
_040
2_16
V4Z~
D
1
2
L21 DLW21SN900SQ2_0805~D@ 11
44 3 3
2 2
R22
0_0805_5%~D
1 2
C76
0.1U
_040
2_16
V4Z~
D
1
2
U17
TPS2062DR_SO8~D
GND1IN2EN1#3EN2#4
OC1# 8OUT1 7OUT2 6OC2# 5
C90.1U_0402_16V4Z~D
1
2
JUSB2
FOX_UB11123-8Z1-TR~D
A_VCCA1A_D-A2A_D+A3A_GNDA4
B_VCCB1B_D-B2B_D+B3B_GNDB4
G19G210G311G412
PJP
22P
AD
-OP
EN
4x4
m 12
L14 DLW21SN900SQ2_0805~D@11
44 3 3
2 2
L13 DLW21SN900SQ2_0805~D@11
44 3 3
2 2
R620_0402_5%~D 1 2
C3430.1U_0402_16V4Z~D
1
2
R2170_0402_5%~D 1 2
R260_0402_5%~D 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MDC_AC_BITCLK
ICH_SDOUT_MDC
ICH
_AC
_SD
OU
T_M
DC
TER
M
ICH_SDOUT_MDC
MD
C_A
C_B
ITC
LK_T
ERM
MDC_SDIN
MDC_AC_BITCLK
DAT_SM2
CLK_SM2
ICH_SYNC_MDC
ICH_SDOUT_MDC
ICH_RST_MDC#
COEX2_WLAN_ACTIVE
TP_DATA
TP_CLKTP_DATATP_CLK
KSI0
KSI3KSI4
KSI1KSI2
KSI5KSI6
KSO17M_LED_AM_LED_BM_LED_C
COEX1_BT_ACTIVECOEX3
USBP2_D+USBP2_D-
HW_RADIO_DIS#
LID_CL#
+3VSUS
+5VRUN
+5VRUN
+3VRUN
+5VALW
ICH_RST_MDC#<22>
ICH_SYNC_MDC<22>ICH_AC_SDIN1<22>
MDC_AC_BITCLK<26>
KSI0 <35,36>
KSI6 <35,36>
KSI3 <35,36>
KSI5 <35,36>
KSI2 <35,36>
CLK_SM2 <35>
KSI1 <35,36>
KSI4 <35,36> DAT_SM2 <35>
ICH_SDOUT_MDC<22>
COEX2_WLAN_ACTIVE<33>
COEX1_BT_ACTIVE<33>
LID_CL#<34>
M_LED_A<35>M_LED_B<35>M_LED_C<35>
KSO17<34>
BT_ACTIVE<39>
HW_RADIO_DIS#<33,35>
USBP2_D-<28>USBP2_D+<28>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
BT PORT and MDC
29 51Monday, October 18, 2004
Compal Electronics, Inc.
1
3
5
7
9
11 12
10
8
6
4
2GND
IAC_SDATA0
IAC_SYNC
IAC_SDATAIN
IAC_RESET#
RES
RES
3.3V
GND
GND
IAC_BITCLK
GND
New MDC connector.
W=20 mil
LCM & Direct play SW & T PAD
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near BT
0402 Resistor reserve for ESD
C86
10P
_040
2_50
V8J~
D@
1
2
JLCM
JST_BM20B-SRDS-G-TFC
11 2 233 4 455 6 677 8 899 10 10
12 1214 141111
13131515 16 1617171919 18 18
20 20
C56
010
P_0
402_
50V8
J~D
1
2
C8210P_0402_50V8J~D@
1 2
C57
0
33P
_040
2_50
V8J~
D
1
2
C56
210
P_0
402_
50V8
J~D
1
2
C9310P_0402_50V8J~D@
1 2
JBT
JST_BM10B-SRSS-TB~D
1122334455667788991010
11 1112 12
Connector for MDC Rev1.5
JMDC
TYCO_1-179373-2~D
GND11IAC_SDATA_OUT3GND25IAC_SYNC7IAC_SDATA_IN9IAC_RESET#11
RES0 2RES1 43.3V 6
GND3 8GND4 10
IAC_BITCLK 12
1313
1414
1515
1616
1717
1818
1919
2020
R98
10_0
402_
5%~D
@
12
C56
310
P_0
402_
50V8
J~D
1
2
C39
610
P_0
402_
50V8
J~D
@
1
2
R9133_0402_5%~D 1 2
L49BLM11A601S_0603~D
12
T31 PAD~D@
R40
610
_040
2_5%
~D@
12
C5610.1U_0402_16V4Z~D
1
2
C2750.1U_0402_16V4Z~D
1
2
R51
74.
7K_0
402_
5%~D
12
R51
810
K_04
02_5
%~D 1
2
C55
810
P_0
402_
50V8
J~D
1
2
C59
610
0P_0
402_
50V8
J~D
@
1
2
C5640.1U_0402_16V4Z~D
1
2
C89
0.1U
_040
2_16
V4Z~
D
1
2
L50BLM11A601S_0603~D
12
C40
34.
7U_0
805_
10V4
Z~D
1
2
C7310P_0402_50V8J~D@
1 2
R51
54.
7K_0
402_
5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XI
LAN_AD16PCI_AD16
XO
LAN_RX-
LAN_TX+
EPHY_PLLVDD
LINK_LED100#
LAN_TX-
LINK_LED10#
SPROM_CLK
LAN_RX+
CLK_PCI_LOM
ACTLED#
LAN_TX+
LAN_RX+LAN_RX-
LAN_TX-
EPHY_PLLVDD
PCI_AD[0..31]
PCI_AD25
PCI_AD30
PCI_AD28
PCI_AD22
PCI_AD31
PCI_AD23
PCI_AD27PCI_AD26
PCI_AD21
PCI_AD24
PCI_AD29
LAN_AD16
PCI_AD14
PCI_AD19
PCI_AD17
PCI_AD11
PCI_AD20
PCI_AD12
PCI_AD16PCI_AD15
PCI_AD10
PCI_AD13
PCI_AD18
PCI_AD3
PCI_AD8
PCI_AD6
PCI_AD0
PCI_AD9
PCI_AD1
PCI_AD5PCI_AD4
PCI_AD2
PCI_AD7
SPROM_DOUT
SPROM_CS
SPROM_DI
LAN_TX+
LAN_TX-
LAN_RX+
LAN_RX-
ACTLED#
LINK_LED10#LINK_LED100#
SPROM_CLK
SPROM_DI
SPROM_CS
SPROM_DOUT
+1.8VLAN
+3VLAN
+1.8VLAN
+1.8VLAN
+3VLAN
+3VLAN
+3VLAN
+3VLAN+3VSUS
+1.8VLAN
+3VLAN
+3VLAN
+3VLAN
+3VLAN
+3VLAN
+1.8VLAN
+3VLAN
+3VLAN
+3VLAN
+3VLAN
PCI_AD[0..31]<21,31,33>
PCI_C_BE1#<21,31,33>
PCI_PAR<21,31,33>PCI_SERR#<21,31,33>
PCI_IRDY#<21,31,33>
PCI_PERR#<21,31,33>
PCI_C_BE3#<21,31,33>PCI_C_BE2#<21,31,33>
PCI_DEVSEL#<21,31,33>PCI_TRDY#<21,31,33>
PCI_C_BE0#<21,31,33>
PCI_STOP#<21,31,33>
PCI_FRAME#<21,31,33>
PCI_PIRQC#<21,31>
PCI_GNT4#<21>PCI_REQ4#<21>
CLK_PCI_LOM<6>
SYS_PME#<31,33,34>
CLKRUN#<23,31,33,34>
PCI_RST#<21,31,33>LAN_LOW_PWR <35>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
BROADCOM 4401L LAN
30 51Monday, October 18, 2004
Compal Electronics, Inc.
Place closeto pin 69
Place closeto pin 57
WLAN LOM
ORANGE (100M)
GREEN (10M)
YELLOW
LINK_LED100#
LINK_LED10#
ACTLED#
WLAN_LINK_10_LDE
WLAN_ACT_LED
LED (JP28)
Place closely pin 118
15 mil
16Kb
None
10K Pullup
None
None
WLAN_LINK_80211A
ORANGE/GREENWLAN_LINK_80211A
WLAN_LINK_10_LDENC
Place close to LAN chip
None
10K Pullup4Kb
1Kb
SPROM_CLKSPROM_DOUT
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R32 49.9_0603_1%~D12
C600.1U_0402_16V4Z~D
1
2
C355
0.1U_0402_16V4Z~D
1
2
R43
010
0K_0
402_
5%~D
@
12
L12
220n_LCN0603T-R22J-S_5%_0603~D
1 2
C399
0.1U_0402_16V4Z~D1
2
C33
0.01U_0402_16V7K~D
1
2
R22
520
0_04
02_5
%~D
12
C41722P_0402_50V8J~D @
1
2
R30 49.9_0603_1%~D12
R89
10K_
0402
_5%
~D
@
12
C40110U_0805_10V4M~D
1
2
C254.7U_0805_10V4Z~D
1
2
C32
0.01U_0402_16V7K~D
1
2
R22
620
0_04
02_5
%~D
12
R319 1.27K_0402_1%~D1 2
C630.1U_0402_16V4Z~D
1
2
C3000.1U_0402_16V4Z~D
1
2
C42
10.
1U_0
402_
16V4
Z~D
1
2
1000pF 2KV
4 X 75 OHMS
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
TRP1P
TRP1N
TRP2P
TRP2N
TRP3P
TRP3N
TRP4P
TRP4N
JLOM
TYCO_1368398-1~D
TRD1P11
TRCT112
TRD1N10
TRD2P4
TRCT26
TRD2N5
TRD3P3
TRCT31
TRD3N2
TRD4P8
TRCT47
TRD4N9
YELLOW13
COMMON014
COMMON116
GREEN17ORANGE15
SHIE
LD0
18SH
IELD
119
2020
2121
C373
0.1U_0402_16V4Z~D
1
2
R6810K_0402_5%~D
12
C30
0.01U_0402_16V7K~D
1
2
C31227P_0402_50V8J~D
1
2
C327
0.1U_0402_16V4Z~D1
2
R781K_0402_5%~D
12
R87
10K_
0402
_5%
~D
@
12
C550.1U_0402_16V4Z~D
1
2
C31
0.01U_0402_16V7K~D
1
2
C397
10U_0805_10V4M~D
1
2
R40833_0402_5%~D@
12
C391000P_0402_50V7K~D
1
2
Y2
25MHZ_20PF_1BG25000CK1A~D
1 2
R33 49.9_0603_1%~D12R31 49.9_0603_1%~D12 C20 0.1U_0402_16V4Z~D
1 2
C3071000P_0402_50V7K~D
1
2
C21 0.1U_0402_16V4Z~D1 2
BroadcomBCM 4401L
U19
BCM4401_LQFP128
PCI_AD31122PCI_AD30123PCI_AD29124PCI_AD28126PCI_AD27127PCI_AD26128PCI_AD251PCI_AD243PCI_AD236PCI_AD228PCI_AD219PCI_AD2010PCI_AD1911PCI_AD1814PCI_AD1715PCI_AD1616PCI_AD1533PCI_AD1434PCI_AD1336PCI_AD1237PCI_AD1138PCI_AD1039PCI_AD941PCI_AD842PCI_AD745PCI_AD648PCI_AD549PCI_AD450PCI_AD351PCI_AD253PCI_AD154PCI_AD055
PCI_CBE3_L4PCI_CBE2_L18PCI_CBE1_L32PCI_CBE0_L43PCI_FRAME_L20PCI_IRDY_L21PCI_TRDY_L23PCI_DEVSEL_L26PCI_STOP_L27PCI_PERR_L28PCI_SERR_L29PCI_PAR31PCI_INT_L116
PCI_RST_L117PCI_CLK118PCI_GNT_L119PCI_REQ_L121PCI_PME_L113PCI_IDSEL5
PCI_CLKRUN_L22
XTAL_IN67XTAL_OUT66
LED0_L 75LED1_L 76LED2_L 77LED3_L 78
EPHY_AGND 58EPHY_AVDD 57
EPHY_BIAS_AVDD 69EPHY_BIAS_AVSS 70
EPHY_PLLVDD 64EPHY_PLLGND 63
EPHY_VREF 71EPHY_RDAC 72
EPHY_TESTMODE 88
EPHY_TDP 62EPHY_TDN 61EPHY_RDP 59EPHY_RDN 60
NC0 104NC1 105NC2 103NC3 108NC4 102NC5 109NC6 110NC7 107
VAUX_AVAIL 87NC8 86NC9 85
BOOTROM_SCL 90BOOTROM_SDA 93
SPROM_CS 98SPROM_CLK 95
SPROM_DOUT 101SPROM_DIN 99
EXT_POR_L 89
JTAG_TDO 83JTAG_TCK 80JTAG_TDI 82
JTAG_TRST_L 73JTAG_TMS 81
VSS0
12VS
S146
VSS2
111
VSS3
100
VSS4
84VS
S52
VSS6
24VS
S774
VSS8
13VS
S947
VSS1
012
0VS
S11
35
VDD
CO
RE1
112
VDD
CO
RE2
17VD
DC
OR
E344
VDD
BUS1
115
VDD
BUS2
125
VDD
BUS3
19VD
DBU
S430
VDD
BUS5
40VD
DBU
S652
VDD
BUS7
7
NC
1010
6V
DD
IO1
79V
DD
IO2
94
REG
_AVD
D1
96R
EG_A
VDD
297
RE
G_V
OU
T191
RE
G_V
OU
T292
VESD
111
4VE
SD2
25VE
SD3
56
XTAL
_AVD
D65
XTAL
_AVS
S68
C32127P_0402_50V8J~D
1
2
C295
0.1U_0402_16V4Z~D1
2
R7110K_0402_5%~D
12
R7410K_0402_5%~D
12
C350
0.1U_0402_16V4Z~D1
2
R383 100_0402_5%~D1 2
C4000.1U_0402_16V4Z~D
1
2
C34
1000
P_04
02_5
0V7K
~D
@
1
2
C356
1000P_0402_50V7K~D
1
2
R304 10K_0402_5%~D@
1 2
L27
BLM11A121S_0603~D
12
C334
0.1U_0402_16V4Z~D
1
2
C398
0.1U_0402_16V4Z~D1
2
R26
482
0_04
02_5
%~D
12
U1
AT93C46-10SI-2.7_SO8~D
CS1SK2DI3DO4
VCC 8NC 7
ORG 6GND 5
C700.1U_0402_16V4Z~D
1
2
C3604.7U_0805_10V4Z~D
1
2C301
0.1U_0402_16V4Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R5C841XIR5C841XO
R5C841XI
R5C841XO
CBS_CSTSCHNGCBS_CCLKRUN#CBS_CCLK_INTERNAL
CBS_CINT#
CBS_CAUDIO
IEEE1394_TPAN0
CBS_RSVD/A18
IEEE1394_TPAP0
IEEE1394_TPBP0IEEE1394_TPBN0
IEEE1394_TPBIAS0
CBS_RSVD/D14CBS_RSVD/D2
CBS_CCD2#_INTERNALCBS_CCD1#_INTERNAL
CBS_CVS2CBS_CVS1
PCI_AD29PCI_AD30
PCI_AD28
PCI_AD31
PCI_AD26PCI_AD25
PCI_AD27
PCI_AD22PCI_AD23
PCI_AD20
PCI_AD24
PCI_AD21
PCI_AD18PCI_AD17
PCI_AD19
PCI_AD14
PCI_AD16
PCI_AD13
PCI_AD15
PCI_AD12PCI_AD11PCI_AD10PCI_AD9
PCI_AD7PCI_AD6
PCI_AD8
PCI_AD4PCI_AD5
PCI_AD1PCI_AD2PCI_AD3
PCI_AD0
PCI_C_BE3#
PCI_C_BE0#
PCI_C_BE2#PCI_C_BE1#
PCI_PAR
PCI_FRAME#
PCI_STOP#PCI_DEVSEL#
PCI_TRDY#PCI_IRDY#
PCI_AD17 CBS_IDSEL
PCI_REQ1#PCI_GNT1#
PCI_PERR#PCI_SERR#
CBS_GRST#PCI_RST#
IEEE1394_TPBIAS0
IEEE1394_TPAP0IEEE1394_TPAN0IEEE1394_TPBP0IEEE1394_TPBN0
CK3
3M_C
BS_T
ERM
TPA0+
TPB0+TPA0-
TPB0-
Z3008
CLK_PCI_PCM
CBS_CC/BE3#CBS_CC/BE2#
CBS_CC/BE0#CBS_CC/BE1#
CBS_CPAR
CBS_CDEVSEL#
CBS_CTRDY#CBS_CFRAME#
CBS_CIRDY#CBS_CSTOP#
CBS_CPERR#CBS_CSERR#CBS_CREQ#CBS_CGNT#
CBS_CBLOCK#
CBS_GRST#
CBS_SPK
SD_EN
CBS_CRST#
SD_CLK
SD_EN
+3VSUS
+3V_PHY
+3VSUS
+3VSUS
+3VSUS
+3VSUS +SD_VCC
VPPEN0<32>VPPEN1<32>
VCC5EN#<32>VCC3EN#<32>
SD_CLK <32>SD_CMD <32>
CLKRUN#<23,30,33,34>
SD_DATA0 <32>SD_DATA1 <32>SD_DATA2 <32>SD_DATA3 <32>
CBS_CCLKRUN# <32>CBS_CSTSCHNG <32>
CBS_CCLK <32>
CBS_CRST# <32>
CBS_CINT# <32>
CBS_CAUDIO <32>
CBS_RSVD/D2 <32>CBS_RSVD/D14 <32>
CBS_RSVD/A18 <32>
CBS_CCD2# <32>CBS_CCD1# <32>
CBS_CVS1 <32>CBS_CVS2 <32>
PCI_AD[0..31]<21,30,33>
PCI_C_BE3#<21,30,33>
PCI_C_BE1#<21,30,33>PCI_C_BE0#<21,30,33>
PCI_C_BE2#<21,30,33>
PCI_PAR<21,30,33>
SYS_PME#<30,33,34>
PCI_TRDY#<21,30,33>PCI_FRAME#<21,30,33>
PCI_IRDY#<21,30,33>PCI_STOP#<21,30,33>PCI_DEVSEL#<21,30,33>
PCI_GNT1#<21>PCI_REQ1#<21>
PCI_PERR#<21,30,33>PCI_SERR#<21,30,33>
PCI_RST#<21,30,33>CLK_PCI_PCM<6>
CBS_CAD0 <32>
CBS_CAD19 <32>
CBS_CAD17 <32>CBS_CAD18 <32>
CBS_CAD15 <28>
CBS_CAD12 <32>
CBS_CAD14 <32>
CBS_CAD11 <32>CBS_CAD10 <32>CBS_CAD9 <32>CBS_CAD8 <32>CBS_CAD7 <32>CBS_CAD6 <32>CBS_CAD5 <32>CBS_CAD4 <32>CBS_CAD3 <32>CBS_CAD2 <32>CBS_CAD1 <32>
CBS_CAD31 <32>
CBS_CAD29 <32>
CBS_CAD27 <32>
CBS_CAD23 <32>CBS_CAD24 <32>
CBS_CAD28 <32>
CBS_CAD26 <32>
CBS_CAD21 <32>CBS_CAD20 <32>
CBS_CAD30 <32>
CBS_CAD25 <32>
CBS_CAD13 <28>
CBS_CAD16 <32>
CBS_CAD22 <32>
CBS_CC/BE3# <32>
CBS_CC/BE1# <32>CBS_CC/BE2# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CREQ# <32>CBS_CGNT# <32>
CBS_CSERR# <32>CBS_CPERR# <32>
CBS_CFRAME# <32>CBS_CTRDY# <32>
CBS_CSTOP# <32>CBS_CIRDY# <32>
CBS_CBLOCK# <32>CBS_CDEVSEL# <32>
PCI_PIRQC#<21,30>PCI_PIRQD#<21,33>
IRQ_SERIRQ<23,34>
USBP3+<23>USBP3-<23>
PCI_PIRQB#<21,33>
CB_HWSPND#<34>CBS_SPK<26>
SD_DET# <32>
SD_WP <32>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
CardBus Controller(R5C841)
31 51Monday, October 18, 2004
Compal Electronics, Inc.DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R245 0_0402_5%~D
12
R163 0_0402_5%~D@1 2
R154 10K_0402_5%~D
1 2
R490
100K_0402_5%~D
12
R244 0_0402_5%~D
12
J1394
AMP_440168-2
1234
X4
24.576MHz_16P_1BG24576CKIA~D
12
C477
22P_0402_50V8J~D
12
R152
0_0402_5%~D 1
2
L29
857CM-0009~D@
11
22 33
44 5 5
6 67 7
8 8
R138
56.2_0603_1%~D
12
R243 0_0402_5%~D
12
C478
22P_0402_50V8J~D
12
R477 10K_0402_5%~D
1 2
C208
270P_0402_50V7K~D@
1
2
C504
1U_0603_10V4Z~D
1
2
R5C841U25B
R5C841_CSP208~D
CPSD11
TPAP1B10
TPAP0B12TPAN0A12
TPBP0B13TPBN0A13
TPBIAS0D12
XOB16 XIA16
TPAN1A10
TPBP1B11TPBN1A11
VREFD13REXTB14
MDIO00 B1MDIO01 A2MDIO02 A3MDIO03 B3MDIO04 B4MDIO05 A5MDIO06 B5MDIO07 D5MDIO08 A6MDIO09 B6MDIO10 D6MDIO11 E6MDIO12 A7MDIO13 B7MDIO14 D7MDIO15 E7MDIO16 A8MDIO17 B8MDIO18 D8MDIO19 E8
FIL0A14
TPBIAS1D10
USBDPV14USBDMW14
VPPEN0V13VPPEN1W13
VCC5EN#R13VCC3EN#T13
REGEN#R7
R5C841
U25A
R5C841_CSP208~D
AD31M2AD30M1AD29N5AD28N4AD27N2AD26N1AD25P5AD24P4AD23R4AD22R2AD21R1AD20T2AD19T1AD18U2AD17U1AD16V1AD15T7AD14V7AD13W7AD12R8AD11T8AD10V8AD9W8AD8R9AD7V9AD6W9AD5T11AD4V11AD3W11AD2T12AD1V12AD0W12
PARV6
DEVSEL#T5
FRAME#V3
GNT#M5
IDSELP1
IRDY#V4
PERR#W5
REQ#M4
SERR#T6
STOP#V5
TRDY#W4
CCLK/CADR16 L19CCLKRUN#/WP(IOIS16#) A18
CRST#/RESET H19
RESERVED/CDATA2 C19RESERVED/CDATA14 W18
RESERVED/CADR18 N16
CAD31/CDATA10 B19CAD30/CDATA9 C18CAD29/CDATA1 D19CAD28/CDATA8 D18CAD27/CDATA0 E19
CAD26/CADR0 E16CAD25/CADR1 F18CAD24/CADR2 F15CAD23/CADR3 G18CAD22/CADR4 G15CAD21/CADR5 H18CAD20/CADR6 H15
CAD19/CADR25 J18CAD18/CADR7 J16
CAD17/CADR24 J15CAD16/CADR17 P16
CAD15/IOWR# P19CAD14/CADR9 R19CAD13/IORD# P18
CAD12/CADR11 R18CAD11/OE# T19
CAD10/CE2# T18CAD9/CADR10 U19
CAD8/CDATA15 U18CAD7/CDATA7 W17
CAD6/CDATA13 V17CAD5/CDATA6 W16
CAD4/CDATA12 V16CAD3/CDATA5 W15
CAD2/CDATA11 V15CAD1/CDATA4 T15CAD0/CDATA3 R14
CC/BE3#/REG# F16CC/BE2#/CADR12 K18
CC/BE1#/CADR8 P15CC/BE0#/CE1# V19
CPAR/CADR13 N15
CAUDIO/BVD2(SPKR#/LED) F19
RESERVED/CADR19 N19
CCD1#/CD1# T14CCD2#/CD2# D15
CDEVSEL#/CADR21 L18
CFRAME#/CADR23 K16
CGNT#/WE# M15
CINT#/RDY(IREQ#) M18
CIRDY#/CADR15 K15
CREQ#/INPACK# G19
CSTOP#/CADR20 M16
CSTSCHG/BVD1(STSCHG#/RI#) E18
CTRDY#/CADR22 L16
CVS1/VS1# R16CVS2/VS2# H16
PCICLKK1PCIRST#L4GBRST#G2
CPERR#/CADR14 N18CSERR#/WAIT# G16
HWSPND#F2
CLKRUN#L5
INTA#J2
C/BE3#P2C/BE2#W2C/BE1#W6C/BE0#T9
INTB#K4INTC#K2
UDIO0/SERIRQ#J4UDIO1H1UDIO2H2UDIO3H4UDIO4H5UDIO5G1
RI_OUT#/PME#G4SPKROUTF1
TESTF4
R495 22_0402_5%~D 12
C162 0.01U_0402_16V7K~D
1 2
C13
31U
_060
3_10
V4Z~
D
1
2
C475
270P_0402_50V7K~D
1
2
C13
50.
01U
_040
2_16
V7K~
D
1
2
R1660_0402_5%~D
12
R172
100K_0402_5%~D
12
R169100_0402_5%~D
1 2
C187 0.01U_0402_16V7K~D
1 2
C188
270P_0402_50V7K~D
@
1
2
R450
5.1K_0603_1%
~D
12
R491
10_0402_5%~D
@
12
C515
4.7P_0402_50V8C
~D
@
1
2
R487 100K_0402_5%~D
1 2
R459
56.2_0603_1%~D
12
R168 10K_0402_5%~D
1 2
R161 10K_0402_5%~D
1 2
R137
10K_0603_1%~D
12
R139
56.2_0603_1%~D
12
R246 0_0402_5%~D
12
R460
56.2_0603_1%~D
12
U6
RT9701CB_SOT25~D
VIN3VIN/CE4 VOUT 1
VOUT 5
GND2
C149
0.33U_0603_10V7K~D
1
2
R135
10K_0402_5%~D
12
C152
0.01U_0402_16V7K~D
1
2
R146
100K_0402_5%~D
12
R167
100K_0402_5%~D
12
C185
0.01U_0402_16V7K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CBS_CAD18
CBS_CAD29
CBS_CAD6
CBS_CAD24
CBS_CAD12
CBS_CAD5
CBS_CAD14
CBS_CAD3
CBS_CAD20
CBS_CAD31
CBS_CAD4
CBS_CAD8
CBS_CAD27
CBS_CAD30
CBS_CAD1
CBS_CAD7
CBS_CAD26
CBS_CAD2
CBS_CAD22
CBS_CAD25
CBS_CAD28
CBS_CAD19
CBS_CAD11
CBS_CAD21
CBS_CAD16
CBS_CAD10CBS_CAD9
CBS_CAD0
CBS_CAD17
CBS_CAD23
CBS_RSVD/D14
CBS_CVS1
CBS_CAD0
CBS_CVS2
CBS_CAD1
CBS_CRST#
CBS_CINT#
CBS_CAD2
CBS_CCLK
CBS_CAD3
CBS_CCLKRUN#
CBS_CAD4CBS_CAD5
CBS_CCD1#
CBS_CAD6
CBS_CCD2#
CBS_CAD7CBS_CAD8
CBS_CSTSCHNGCBS_CAUDIO
CBS_CAD9 CBS_CAD10CBS_CAD11CBS_CAD12 CBS_CAD13_LCBS_CAD14 CBS_CAD15_L
CBS_CAD16
CBS_CAD17CBS_CAD18 CBS_CAD19CBS_CAD20CBS_CAD21CBS_CAD22CBS_CAD23CBS_CAD24CBS_CAD25CBS_CAD26CBS_CAD27 CBS_CAD28CBS_CAD29 CBS_CAD30
CBS_CAD31
CBS_CC/BE0#
CBS_CC/BE1#
CBS_CC/BE2#
CBS_CC/BE3#
CBS_CPAR
CBS_CFRAME#CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#CBS_CDEVSEL#
CBS_CBLOCK#CBS_CPERR#
CBS_CSERR#CBS_CREQ#
CBS_CGNT#
CBS_RSVD/A18
CBS_RSVD/D2
CBS_VCCCBS_VPP
CBS_VCCCBS_VPP
CBS_VPP
CBS_VCC+3VSUS
+5VSUS
+3V_PHY
+3VSUS
+3VSUS
+3V_PHY
+3VRUN
+3VSUS
+3VSUS
+2.5V_CORE
+SD_VCC
+SD_VCC
CBS_CAD0 <31>CBS_CAD1 <31>CBS_CAD2 <31>CBS_CAD3 <31>CBS_CAD4 <31>CBS_CAD5 <31>CBS_CAD6 <31>CBS_CAD7 <31>CBS_CAD8 <31>CBS_CAD9 <31>CBS_CAD10 <31>CBS_CAD11 <31>CBS_CAD12 <31>CBS_CAD14 <31>CBS_CAD16 <31>CBS_CAD17 <31>
CBS_CAD31 <31>CBS_CAD30 <31>
CBS_CAD18 <31>CBS_CAD19 <31>CBS_CAD20 <31>
CBS_CAD29 <31>CBS_CAD28 <31>
CBS_CAD21 <31>
CBS_CAD27 <31>CBS_CAD26 <31>CBS_CAD25 <31>CBS_CAD24 <31>CBS_CAD23 <31>CBS_CAD22 <31>
CBS_RSVD/D14 <31>
CBS_CVS1 <31>
CBS_CVS2 <31>CBS_CRST# <31>
CBS_CINT#<31>
CBS_CCLK<31>
CBS_CCLKRUN#<31>
CBS_CCD1# <31>
CBS_CCD2# <31>
CBS_CAUDIO <31>CBS_CSTSCHNG <31>
CBS_CC/BE0#<31>
CBS_CC/BE1#<31>
CBS_CC/BE2#<31>
CBS_CC/BE3# <31>
CBS_CPAR<31>
CBS_CFRAME# <31>CBS_CTRDY# <31>
CBS_CIRDY#<31>
CBS_CSTOP# <31>CBS_CDEVSEL# <31>
CBS_CBLOCK# <31>CBS_CPERR#<31>
CBS_CSERR# <31>CBS_CREQ# <31>
CBS_CGNT#<31>
CBS_RSVD/A18 <31>
CBS_RSVD/D2<31>
VPPEN0<31>VPPEN1<31>
VCC3EN#<31>VCC5EN#<31>
CBS_CAD15_L <28>CBS_CAD13_L <28>
SD_WP<31>
SD_DET#<31>
SD_DATA1<31>
SD_DATA2<31>SD_DATA3<31>
SD_DATA0<31>
SD_CMD<31>
SD_CLK<31>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
CardBus/SD card Socket
32 51Monday, October 18, 2004
Compal Electronics, Inc.DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C532
0.01U_0402_16V7K~D
1
2
C174
0.01U_0402_16V7K~D
1
2
R5C841
U25C
R5C841_CSP208~D
VCC_3V1F5VCC_3V2G5VCC_3V3J19VCC_3V4K19
VCC_PCI3V1W3VCC_PCI3V2R11VCC_PCI3V3R12
VCC_MD3VA4
VCC_RIN1R6VCC_RIN2E13
VCC_ROUT1L1
AGND1A9AGND2B9AGND3D9
VCC_ROUT2E14
AVCC_PHY1E10AVCC_PHY2E11AVCC_PHY3A17
GND1J1GND2J5GND3K5GND4E9GND5R10GND6T10GND7V10GND8W10GND9L15GND10M19
NC1 L2NC2 C1NC3 D1NC4 E1NC5 C2NC6 D2NC7 E2NC8 E4NC9 E12
AVCC_PHY4B17
AGND4D14AGND5A15AGND6B15
C211
0.01U_0402_16V7K~D
1
2
C48
90.
1U_0
402_
16V4
Z~D
1
2 Part Number Description
DC025072400 H-CON SET DAL30MB-MDC
MDC wire set cable
C521
0.01U_0402_16V7K~D
1
2
C183
0.01U_0402_16V7K~D
1
2
C193
10U_0805_10V4M
~D
1
2 C184
0.1U_0402_16V4Z~D
1
2
L44
BLM21A601SPT_0805~D
1 2
C517
0.1U_0402_16V4Z~D
1
2
Part Number Description
GC20323MX00 BATT CR2032 3V220MAH MAXELL
RTC BATT
C51
910
U_0
805_
10V4
M~D
1
2
JCBUS
FOX_WZ21131-G2-P4_LT
GND1S1_D32S1_D43S1_D54S1_D65S1_D76S1_CE1#7S1_A108S1_OE#9S1_A1110S1_A911S1_A812S1_A1313S1_A1414S1_WE#15S1_RDY#16S1_VCC17S1_VPP18S1_A1619S1_A1520S1_A1221S1_A722S1_A623S1_A524S1_A425S1_A326S1_A227S1_A128S1_A029S1_D030S1_D131S1_D232S1_WP33GND34GND69GND71GND73GND75GND77GND79GND81GND83
GND 35S1_CD1# 36
S1_D11 37S1_D12 38S1_D13 39S1_D14 40S1_D15 41
S1_CE2# 42S1_VS1 43
S1_IORD# 44S1_IOWR# 45
S1_A17 46S1_A18 47S1_A19 48S1_A20 49S1_A21 50
S1_VCC 51S1_VPP 52S1_A22 53S1_A23 54S1_A24 55S1_A25 56S1_VS2 57S1_RST 58
S1_WAIT# 59S1_INPACK# 60
S1_REG# 61S1_BVD2 62S1_BVD1 63
S1_D8 64S1_D9 65
S1_D10 66S1_CD2# 67
GND 68GND 70GND 72GND 74GND 76GND 78GND 80GND 82GND 84
C173
10U_0805_10V4M
~D
1
2
C18
610
00P_
0402
_50V
7K~D
1
2
C531
0.1U_0402_16V4Z~D
1
2
Part Number Description
DC00F001700 PCMCIA FOXCONN1CA415M1-TA 68P
PCMCIA BODY
C197
10U_0805_10V4M
~D
1
2
Part Number Description
NBX08001000 FFC 6P F P1.0PAD=0.7 23mm
T/P FFC cable
C192
0.47U_0603_16V4Z~D
1
2
C195
0.01U_0402_16V7K~D
1
2
C508
0.1U_0402_16V4Z~D
1
2
C190
0.01U_0402_16V7K~D
1
2
C48
10.
1U_0
402_
16V4
Z~D
1
2
C47
622
U_1
206_
10V4
Z~D
1
2
R445 100_0402_5%~D
12
JSD
MOLEX_48141-0001
SDC18SDC07VSS26CLK5VDD4VSS13CMD2SDC3/CD1SDC29
CD#10COM11WP12
CGND 13CGND 14
C203
0.01U_0402_16V7K~D
1
2
R439 100K_0402_5%~D
12
Part Number Description
DC025072500 H-CON SET DAL30MB-MEDIA-TP
Media wire set cable
C198
10U_0805_10V4M
~D
1
2
C202
0.01U_0402_16V7K~D
1
2
C205
0.01U_0402_16V7K~D
1
2
C204
0.01U_0402_16V7K~D
1
2
C522
0.01U_0402_16V7K~D
1
2
Part Number Description
DC025072300 H-CON SET DAL30MB-B/T-RTC
Bluetooth wire set cable
U23
R5531V002-E2-FA_SSOP16~D
VCC3IN11
NC 10
VCC5_EN1
EN03EN14
FLG5
VCCOUT 12VCCOUT 14
VCC5IN15
VCC3_EN2
VPPOUT 8
NC 7NC 6GND16
VCC5IN13
VCCOUT 9
C514
0.01U_0402_16V7K~D
1
2
Part Number Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
FAN
C18
010
00P_
0402
_50V
7K~D
1
2
C530
0.47U_0603_16V4Z~D
1
2
Part Number Description
PK230007700 SPK PACK DAQ20 2W 4OHM 18MM FG
Speak
C527
0.01U_0402_16V7K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_AD19
CLK_PCI_MINI
LED_WLAN5LED_WLAN_OUT
LED_WLAN24
PCI_STOP#
PCI_C_BE3#
PCI_AD25
PCI_AD30
PCI_GNT3#
PCI_AD11
PCI_AD19
PCI_AD3
PCI_AD16
LED_WLAN5
PCI_AD21
PCI_AD0
PCI_AD0
PCI_AD6
PCI_AD13
PCI_C_BE1#
LED_WLAN24
PCI_AD17
PCI_C_BE0#
PCI_PERR#
PCI_AD20
PCI_PIRQB#
PCI_AD24
PCI_AD5
PCI_AD7
PCI_AD31
PCI_AD12
PCI_AD7
PCI_AD15
PCI_SERR#
PCI_AD17
PCI_REQ3#
PCI_AD16
PCI_AD25
PCI_AD5
PCI_AD26
PCI_AD29
HW_RADIO_DIS#
PCI_AD3
PCI_AD21
PCI_AD6
PCI_AD13
PCI_AD10
MPCIACT#
PCI_DEVSEL#
PCI_AD28
SYS_PME#
PCI_AD18
PCI_AD28
PCI_PAR
PCI_AD4
PCI_AD11
PCI_TRDY#
MINIDSELPCI_AD24
PCI_AD20
PCI_AD23
PCI_AD2
PCI_AD10
PCI_FRAME#
PCI_AD22
PCI_AD26
PCI_AD14
CLK_PCI_MINI
PCI_AD22
PCI_AD2PCI_AD1
PCI_AD9
PCI_AD12
CLKRUN#
PCI_AD31
PCI_AD30
PCI_AD27
PCI_AD15
PCI_AD8
PCI_AD19
PCI_AD27
PCI_RST#
PCI_PIRQD#
PCI_AD29
PCI_AD4
PCI_AD8
PCI_IRDY#
PCI_AD9
PCI_C_BE2#
PCI_AD14
PCI_AD23
PCI_AD18
PCI_AD1
DEBUG_ENABLE
DEBUG_OUT
+5VRUN
+3VRUN
+3VSUS
+3VSUS
+3VRUN
+3VRUN
+3VRUN
+5VRUN
+3VSUS
PCI_IRDY#<21,30,31>
PCI_PIRQD#<21,31>
HW_RADIO_DIS#<29,35>
PCI_SERR#<21,30,31>
PCI_REQ3#<21>
PCI_PERR#<21,30,31>
PCI_C_BE2#<21,30,31>
PCI_AD[0..31]<21,30,31>
CLKRUN#<23,30,31,34>
COEX1_BT_ACTIVE <29>
CLK_PCI_MINI<6>
COEX2_WLAN_ACTIVE<29>
LED_WLAN_OUT <39>
PCI_STOP# <21,30,31>
PCI_RST# <21,30,31>
PCI_DEVSEL# <21,30,31>PCI_C_BE1#<21,30,31>
PCI_PIRQB# <21,31>
PCI_C_BE3#<21,30,31>
PCI_GNT3# <21>
PCI_FRAME# <21,30,31>PCI_TRDY# <21,30,31>
SYS_PME# <30,31,34>
PCI_PAR <21,30,31>
PCI_C_BE0# <21,30,31>
DEBUG_ENABLE<34>
DEBUG_OUT <34>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
MINIPCI
33 51Monday, October 18, 2004
Compal Electronics, Inc.
Place closely pin 25
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R46210K_0402_5%~D@
12
JPCI
AMP_1318644-1~D
RING 2TIP1
8PMJ-1 48PMJ-338PMJ-2 68PMJ-658PMJ-4 88PMJ-778PMJ-5 108PMJ-89
LED2_YELP 12LED1_GRNP11LED2_YELN 14LED1_GRNN13RESERVED 16CHSGND15
5V 18INTB#17INTA# 203.3V19
RESERVED 22RESERVED213.3VAUX 24GROUND23
RST# 26CLK253.3V 28GROUND27
GNT# 30REQ#29GROUND 323.3V31
PME# 34AD3133RESERVED 36AD2935
AD30 38GROUND373.3V 40AD2739
AD28 42AD2541AD26 44RESERVED43AD24 46C/BE3#45
IDSEL 48AD2347GROUND 50GROUND49
AD22 52AD2151AD20 54AD1953PAR 56GROUND55
AD18 58AD1757AD16 60C/BE2#59
GROUND 62IRDY#61FRAME# 643.3V63
TRDY# 66CLKRUN#65STOP# 68SERR#67
3.3V 70GROUND69DEVSEL# 72PERR#71GROUND 74C/BE1#73
AD15 76AD1475AD13 78GROUND77AD11 80AD1279
GROUND 82AD1081AD9 84GROUND83
C/BE0# 86AD8853.3V 88AD787AD6 903.3V89AD4 92AD591AD2 94RESERVED93AD0 96AD395
RESERVED 985V97RESERVED 100AD199
GROUND 102GROUND101M66EN 104AC_SYNC103
AC_SDATA_OUT 106AC_SDATA_IN105AC_CODEC_ID0# 108AC_BIT_CLK107
AC_RESET# 110AC_CODEC_ID1#109RESERVED 112MOD_AUDIO_MON111
GROUND 114AUDIO_GND113SYS_AUDIO_IN 116SYS_AUDIO_OUT115
SYS_AUDIO_IN GND 118SYS_AUDIO_OUT GND117AUDIO_GND 120AUDIO_GND119
MCPIACT# 122RESERVED1213.3VAUX 124VCC5A123
VCC5A123GND127 GND 128
C1594.7P_0402_50V8C~D@1
2
C434
0.047U_0402_16V4Z~D
1
2
U7
TC7SH32FU_SSOP5~D
INB1
INA2 O 4
P5
G3
R35810K_0402_5%~D
1 2
C131
0.047U_0402_16V4Z~D
1
2
R145
200_0402_5%~D
1 2
C83
0.047U_0402_16V4Z~D
1
2
C1750.1U_0402_16V4Z~D
1
2
C440
0.047U_0402_16V4Z~D
1
2
R458 0_0402_5%~D1 2
R489 100K_0402_5%~D1 2
C170
0.047U_0402_16V4Z~D
1
2
R440100_0402_5%~D
1 2
C166
0.047U_0402_16V4Z~D
1
2
R478 100K_0402_5%~D1 2
R4430_0402_5%~D
1 2
C77
0.047U_0402_16V4Z~D
1
2C143
0.047U_0402_16V4Z~D
1
2
C3590.1U_0402_16V4Z~D 1
2
C136
0.047U_0402_16V4Z~D
1
2
R14410_0402_5%~D@
12
C5090.1U_0402_16V4Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KAGND
KSO17
SYS_PME#
LPCPD#
LID_CL#
KSO_17
HP_NB_SENSE
LID_CL_SIO#
USB_BACK_EN#
ATF_INT#
NB_MUTE
SIO_EXT_SMI#
BEEP
SIO_EXT_SCI#SIO_EXT_WAK#SIO_RCIN#
DEBUG_ENABLEDEBUG_OUT
SYS_PME#
SIO_SLP_S5#
LID_CL_SIO#
ATF_INT#
SIO_SLP_S3#
SUS_ON
RUN_ONICH_PME#SIO_THRM#
GC_BL_SUSPEND
MODC_EN#HDDC_EN#
254VCC0
KPLLVCC
LPC_LFRAME#
IRQ_SERIRQCLKRUN#
LPC_LAD1LPC_LAD0
LPC_LAD2LPC_LAD3
PLTRST_SIO#
LPC_LDRQ1#
CLK_PCI_SIO CLK_SIO_14M
LPC_LDRQ0#
CLK_SIO_14MCLK_PCI_SIO
5V_CAL_SIO#
USB_SIDE_EN#
RUN_ON_D
SATA_DET#
SATA_DET#
CB_HWSPND#
TXD0 DEBUG_TXD0
TXD0
ICH_PCIE_WAKE#
SIO_PWRBTN#
LCD_TST LCD_TST_SIOIDE_RST_MOD
+3VALW
+3VALW
+RTC_CELL
+3VRUN
+3VRUN+3VALW
+3VRUN
+3VALW
+3VALW
+3VALW
+3VRUN
+3VALW
+3.3VX
+5VSUS
KSO17<29>USB_BACK_EN#<28>
LID_CL# <29>
HP_NB_SENSE<27>
SIO_EXT_WAK#<23>
SIO_EXT_SMI#<23>
NB_MUTE<27>SIO_RCIN#<22>
SIO_EXT_SCI#<23>
BEEP<26>
ATF_INT#<15>
SIO_SLP_S3#<23>
SIO_SLP_S5#<23>
SYS_PME#<30,31,33>
SUS_ON<38,42>
ICH_PME#<21>SIO_THRM#<23>
RUN_ON<19,37,38,42,44>
MODC_EN#<37>
GC_BL_SUSPEND<18>
HDDC_EN#<37>
CLKRUN# <23,30,31,33>
LPC_LFRAME# <22>
IRQ_SERIRQ <23,31>
LPC_LAD[0..3] <22>
PLTRST# <10,21,23,25>
LPC_LDRQ1# <22>LPC_LDRQ0# <22>
CLK_SIO_14M<6>CLK_PCI_SIO<6>
5V_CAL_SIO#<15>
USB_SIDE_EN#<28>
RUN_ON_D<37,41,43>
DEBUG_ENABLE<33>
DEBUG_OUT<33>
CB_HWSPND#<31>
ICH_PCIE_WAKE#<18,23>
SIO_PWRBTN#<23>
LCD_TST<19,23>IDE_RST_MOD<25>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
SIO (1/2)
34 51Monday, October 18, 2004
Compal Electronics, Inc.
Place closely pin L3 Place closely pin L4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
T14PAD~D
R48
010
K_04
02_5
%~D
12
R461 10K_0402_5%~D
1 2
T13PAD~D
R540 0_0402_5%~D
1 2
R1034.7K_0402_5%~D
1 2
T17PAD~D
T22PAD~D
C12
70.
1U_0
402_
16V4
Z~D
1
2
R116
0_0402_5%~D
1 2
R421 10K_0402_5%~D
1 2
R13310_0402_5%~D
@
12
R13010_0402_5%~D
@
12
T16PAD~D
R456
10K_0402_5%~D
1 2
T5 PAD~D@
C11
00.
1U_0
402_
16V4
Z~D
1
2
R451 10K_0402_5%~D
1 2
R1140_0402_5%~D
@
1 2
T11PAD~D
T3 PAD~D@
T6 PAD~D@
L46BLM11A121S_0603~D
1 2
C1344.7P_0402_50V8C~D
@
1
2
U9
NC7SZ04P5X_SC70-5~D@
A2 Y 4
P5
NC
1
G3
T21PAD~D@
T2PAD~D@
T25PAD~D
C47
910
U_0
805_
10V4
M~D
1
2
T9PAD~D
T28
PAD
@
C1444.7P_0402_50V8C~D
@
1
2
T15PAD~D
T27PAD~D
C4820.047U_0402_16V4Z~D
1
2
C4880.1U_0402_16V4Z~D 1
2
C15
00.
1U_0
402_
16V4
Z~D
1
2
C14
50.
1U_0
402_
16V4
Z~D
1
2
T20PAD~D
T24PAD~D
C12
10.
1U_0
402_
16V4
Z~D
1
2
J13971.5mm SMT~D
@ 1 12 23 3
L43BLM11A121S_0603~D
1 2
T23PAD~D
R454 10K_0402_5%~D
1 2
T18PAD~DR473
10_0402_5%~D 12
R482100K_0402_5%~D
12
LPC47N354
256 - LBGA
GPIO
COM1
LPT
GND
MACALLEN III
LPC
8051GPIO
VCC
LPC INTERFACE
IR
CLOCK
U20A
LPC47N354_LBGA256~D
SGPIO30F13SGPIO31F14SGPIO32E16SGPIO33E15SGPIO34E12SGPIO35E13SGPIO36D16SGPIO37D15
LGPIO50T5LGPIO51N6LGPIO52L6LGPIO53R6LGPIO54T6LGPIO55L7LGPIO56P7LGPIO57N7
LGPIO60/SPCLKA15LGPIO61/SPDOUTD13LGPIO62/SPDINA14LGPIO63C12LGPIO64B13LGPIO65A13LGPIO66D12LGPIO67F11
LGPIO70B12LGPIO71A12LGPIO72C11LGPIO73D11LGPIO74E11LGPIO75A11LGPIO76F10LGPIO77C10
VCCO/BATE2
EC_SCI/SPDIN J12SER_IRQ T4
CLKRUN# P5
SGPIO40C16SGPIO41B16SGPIO42C15SGPIO43A16SGPIO44D14SGPIO45C14SGPIO46C13SGPIO47B14
VCC2_5/PLLR5
VSS13/PLLP6
LAD0 M3LAD1 R1LAD2 T1LAD3 P3
LDRQ0# M6LDRQ1# R3
LFRAME# N4LRESET# L2
DLAD0 N2DLAD1 P1DLAD2 P2DLAD3 N3
DLDRQ1# R2DLFRAME# T2DSER_IRQ R4
DCLKRUN# T3
RXD1 K1TXD1 K5DSR K2RTS K4CTS K3DTR K6
RI B10DCD L1
GPIO10/WK_SE14/IRMODE/IRRX3B H15IRRX K14IRTX M4
GPIOB2/SLCTIN J4GPIOB1/INIT J5
GPIOC0/PD0 J1GPIOC1/PD1 H2GPIOC2/PD2 H1GPIOC3/PD3 H3GPIOC4/PD4 H4GPIOC5/PD5 H5GPIOC6/PD6 H6GPIOC7/PD7 H8
OUTD0/SLCT F1OUTD1/PE G5
OUTD2/BUSY G1OUTD3/ACK H7
OUTD4/ERROR J6
GPIOB0/STROBE K7GPIOB3/ALF J7
AGND F3
PCI_CLKL3CLOCKIL4GPIO83/32KHZ_OUTB2
VCC1_1M7VCC1_2B11VCC1_3R13VCC1_4H12VCC1_5E14VCC1_6B7VCC1_7A1VCC1_8L11
VCC2_1G2VCC2_2P4VCC2_3J2VCC2_4M2
VSS1 C2VSS2 G4VSS3 N5VSS4 R15VSS5 B15VSS6 G9VSS7 J3VSS8 N1VSS9 T10
VSS10 J11VSS11 G14VSS12 B6
T19PAD~D
D9RB751V_SOD323~D
2 1
T8PAD~D
R466
10K_0402_5%~D
1 2
R464 10K_0402_5%~D
1 2
C1050.1U_0402_16V4Z~D
1
2
T26PAD~D
R48
110
K_04
02_5
%~D
12
C15
60.
1U_0
402_
16V4
Z~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_SM2
PBAT_PRES#
SIO_MSCLKSIO_MSDAT
XOSEL
BAT1_LED#BAT2_LED#
HW_RADIO_DIS#
RUNPWROK
SIO_A20GATE
RESET_OUT#
FAN1_PWM
SBAT_SMBDAT
FAN1_TACH
PBAT_SMBDATSBAT_SMBCLK
PBAT_SMBCLK
EEPROM_WC
LAN_LOW_PWR
FRD#FWR#FCS#
SIO_KAH_PGM
KSO16
NUM_LED#CAP_LED#
SRL_LED#
PS_ID
THERMTRIP_SIOH_PROCHOT_SIO#
FPVCC
ALWON
VCC1RST#
ACAV_IN
SYSOPT1SYSOPT0
POWER_SW#POWER_SW_IN#
AUDIO_AVDD_ON
SIO_FA3
KSO1
SIO_FD6
SIO_FA0
SIO_FA6
KSO8
SIO_FD2
SIO_FD0
KSO11
KSI1
SIO_FA1
KSI0
PBAT_ALARM#
KSO2
SIO_FA12
KSO7
KSI6
KSO0
SIO_FA19
SIO_FA16
SIO_FD1
SIO_FA4
KSI5
KSO15
SIO_FA10
SIO_FD7
KSO9
CLK_32KX2
KSO6 SIO_FA11
KSO12
SIO_FA18
KSI3
KSO3KSO4
SIO_FD4
SIO_FA5
KSO10
SIO_FA9
KSO13
SIO_FA8
KSI2
SIO_FD3
KSI7
SIO_FA14SIO_FA13
CLK_32KX1
SIO_FA2KSO14
SIO_FA17
KSI4
KSO5
SIO_FA7
SIO_FA15
SIO_FD5
PBAT_ALARM#
FPVCC
CLK_SMB
DAT_SMB
SBAT_SMBDAT
SBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
LAN_LOW_PWR
CHG_PBATT
POWER_SW_IN#
CHG_PBATT
BID0BID1BID2BID3
DAT_SM2
M_LED_CM_LED_BM_LED_A
BIA_PWM
BID1
BID2
BID0
BID3
PS_ID_DISABLE#
BREATH_LED
CLK_SMB
EMCLKEMDAT
DAT_SMB
H_PROCHOT_SIO#
PROCHOT_SFTON
SIO_IN0
SIO_IN0
SIO_IN1
SIO_IN1
SIO_IN2
SIO_IN2
SIO_IN5
SIO_IN5
SIO_IN6
SIO_IN6
CLK_KBDDAT_KBD
CLK_KBD
DAT_KBD
AB1B_DATAAB1B_CLK
AB1B_DATA
AB1B_CLK
EMCLK
EMDAT
VGA_IDENTIFY
+3VALW
+3VALW
+3VALW
+5VALW
+RTC_CELL
+3VALW
+3VRUN
+3VALW
+VCCP
+VCCP
+5VALW+3VALW
+5VRUN
+3.3VX
+3VRUN
PBAT_PRES#<41>
KSI[0..7]<29,36>
KSO[0..15]<36>PBAT_ALARM#<41>
SBAT_SMBCLK <18>
EEPROM_WC <36>
FAN1_PWM <15>
FAN1_TACH <15>
SIO_FA[0..19] <36>
BAT1_LED# <39>
PBAT_SMBCLK <19,41,46>PBAT_SMBDAT <19,41,46>
SIO_FD[0..7] <36>
SIO_A20GATE <22>
BAT2_LED# <39>
FCS# <36>
FRD# <36>
RUNPWROK <18,38,43,45>
HW_RADIO_DIS# <29,33>
FWR# <36>
RESET_OUT# <38>
SBAT_SMBDAT <18>
LAN_LOW_PWR <30>
KSO16<36>
PS_ID<40>
SRL_LED#<39>NUM_LED#<39>CAP_LED#<39>
ALWON <42>
VCC1RST# <36>
ACAV_IN <40,46>
THERMTRIP_SIO<15>
POWER_SW# <15,39>
AUDIO_AVDD_ON <26>
CHG_PBATT <46>
CLK_SM2<29>DAT_SM2<29>
M_LED_C<29>M_LED_B<29>M_LED_A<29>
PS_ID_DISABLE#<40>
BREATH_LED <39>
CLK_SMB <15,36>
DAT_SMB <15,36>
H_PROCHOT# <7>
BIA_PWM <12,18>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
SIO (2/2)
35 51Monday, October 18, 2004
Compal Electronics, Inc.
3.8X12.1mm
1
0
BID0BID3
X01
X00
REVBID2 BID1
0
0
0 0
0
Level shifter
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VGA_IDENTIFY
LOW = Integrated
High = Discrete
1
0
0 0 0 X02
X030 10 1
X040 1 0 0
R95
10K_
0402
_5%
~D
12
C13
01U
_060
3_10
V4Z~
D 1
2
R468 4.7K_0402_5%~D
1 2
R418 10K_0402_5%~D
1 2
R128100K_0402_5%~D@
12
R102 10K_0402_5%~D
1 2
R123 10K_0402_5%~D
1 2
R47410K_0402_5%~D
12
R452 10K_0402_5%~D1 2
R469 4.7K_0402_5%~D
1 2
T4 PAD~D@
LPC47N354
256 - LBGA
GPIO
K/B
MISC
MACALLEN III
FLASH
U20B
LPC47N354_LBGA256~D
IN0 (WK_EE4)A9IN1 (WK_EE2)B9IN2 (WK_EE3)B8IN3 (GPWKUP)A8IN5 (WK_SE01)C8IN6 (WK_SE05)D8IN7 (WK_EE1)E8
FPGM L10
TEST_PIN K12
XOSEL E4
GPIO0 (WK_SE02)H13GPIO1 (WK_SE03)H11GPIO2 (WK_SE04)H10GPIO3 (TRIGGER)G10GPIO7 (WK_SE06)G13GPIO8 (WK_SE12)/IRRX2J14GPIO9 (WK_SE13)/IRTX2J16GPIO17 (WK_SE23)/A20MG11GPIO20 (WK_SE25)/PS2CLK/8051RXF15GPIO21 (WK_SE26)/PS2DAT/8051TXF12
GPIO84B5GPIO85E5GPIO86D5GPIO87A4GPIO90B4GPIO91C5GPIO92A3GPIO93A2GPIO96C3GPIO97D3
GPIOA0B1GPIOA1D4GPIOA2C1
MSCLK/SPCLKD10MSDATA/SPDOUTE10
EMCLKG6EMDATG3
GPIO94/IMCLKB3GPIO95/IMDATC4
KCLKM1KDATM5
GPIO6 (WK_SE11)/IRMODE/IRRX3AG15GPIO5 (WK_SE10)/KSO15G12GPIO4 (WK_SE07)/KSO14G16KSO13/GPIO18(WK_SE27)R7KSO12/OUT8/KBRSTT7KSO11K8KSO10J8KSO9L8KSO8M8KSO7N8KSO6P8KSO5T8KSO4R8KSO3R9KSO2T9KSO1P9KSO0N9
KSI7M9KSI6L9KSI5K9KSI4K10KSI3M10KSI2R10KSI1N10KSI0P10
XTAL1E1
XTAL2D1
SYSOPT0/GPIO80 K15SYSOPT1/GPIO81 K16
BAT_LED J9PWR_LED J10
GPIOA3/WINDMON E3TESTA F2
VCC1RST# D2RESET_OUT L5
PWRGD K13
ACAV_IN F4POWER_SW_IN# F5
ALWON F6
OUT0 D7OUT1/IRQ8 C7OUT2/FRD F7
OUT3/FWR A6OUT4 E6
OUT5/KBRST D6OUT6 C6
OUT7/SMI E7OUT8/KBRST A7OUT9/PWM2 G7
OUT10/PWM0 G8OUT11/PWM1 F8
AB1A_CLK C9AB1B_DATA F9
AB1B_CLK E9AB1A_DATA D9
GPIO11 (WK_SE15)/AB2A_DATA H16GPIO12 (WK_SE16)/AB2A_CLK H14
GPIO13 (WK_SE17)/AB2B_DATA J15GPIO14 (WK_SE20)/AB2B_CLK J13
GPIO15 (WK_SE21)/FAN_TACH1 A10GPIO16 (WK_SE22)/FAN_TACH2 H9
GPIO82/FAN_TACH3 A5GPIO19 (WK_SE24) F16
FA0 N12FA1 T13FA2 P12FA3 T14FA4 T15FA5 R16FA6 N13FA7 P16FA8 M14FA9 N15
FA10 N16FA11 M13FA12 L12FA13 M15FA14 M16FA15 L14FA16 L13FA17 L15FA18 L16FA19 K11FA20 R14FA21 T16FA22 P13FRD P14
FWR N14FCS P15FD7 M12FD6 R12FD5 T12FD4 P11FD3 N11FD2 M11FD1 R11FD0 T11
R409 10K_0402_5%~D
12
R119100K_0402_5%~D
12
R40
410
K_04
02_5
%~D
@
12
R10610K_0402_5%~D1 2
C45622P_0402_50V8J~D
1 2
X332.768KHZ_12.5P_MC-306~D
12
EB
C Q11
MMBT3904_SOT23~D
2
31
R419 10K_0402_5%~D 1 2
R1318.2K_0402_5%~D
1 2
R410 4.7K_0402_5%~D
1 2
R10510K_0402_5%~D1 2
T10 PAD~D@
R4498.2K_0402_5%~D
1 2
R101 4.7K_0402_5%~D
1 2 R4831K_0402_5%~D@
12
R10
433
0_06
03_5
%~D
12
R412 100K_0402_5%~D
1 2
R40
510
K_04
02_5
%~D
@
12
R4448.2K_0402_5%~D
1 2
R125 100_0402_5%~D
1 2
R448 4.7K_0402_5%~D
1 2
T12 PAD~D@
C44322P_0402_50V8J~D
1 2
R47010K_0402_5%~D2@
12
R117 10K_0402_5%~D
12
R122 4.7K_0402_5%~D 1 2
R110
56_0402_5%~D
1 2
R108 10K_0402_5%~D@1 2
R411 100K_0402_5%~D
1 2
R446 4.7K_0402_5%~D
1 2
R107 10K_0402_5%~D 1 2
R52110K_0402_5%~D 1@
12
R9910K_0402_5%~D
12
R420 10K_0402_5%~D12
R94
10K_
0402
_5%
~D
@
12
R9356_0402_5%~D
1 2
R455 10K_0402_5%~D1 2
R4478.2K_0402_5%~D
1 2
T7 PAD~D@
R10010K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI4
KSO7
KSI6
KSO9
KSO5
KSO14
DAT_SMB
KSO8
KSO10
KSO2
KSI3
KSO9
KSI5
KSO5
KSO13VCC1RST#
KSO6
KSI1
KSO12
KSI5
KSO13
KSO2
KSO11
KSO8
FRD#
KSO1
KSO10
KSO3
KSO15
KSI4
KSI7
KSO16
CLK_SMB
KSO7
KSI6
FWR#
KSO1
KSO14
FCS#
KSO0
KSO12
KSI1
KSI7
KSI2
KSO11
KSO4
KSI0
KSO6
KSO0
KSO4
KSI0
KSI2
KSI3
FWH_RST
EEPROM_WC
KSO15
KSO3
SIO_FA3
SIO_FD2
SIO_FD0
SIO_FA7
SIO_FA12
SIO_FA2
SIO_FA10
SIO_FA19
SIO_FA4SIO_FD1
SIO_FA17
SIO_FD6
SIO_FA6
SIO_FA16
SIO_FA8
SIO_FA0
SIO_FA18
SIO_FA14
SIO_FA5
SIO_FA11
SIO_FA15
SIO_FD3
SIO_FA1
SIO_FA9SIO_FD4
SIO_FA13
SIO_FD5
SIO_FD7
+3VALW
+3VALW +3VALW
FCS#<35>
DAT_SMB <15,35>
FWR#<35>
KSI[0..7]<29,35>
VCC1RST# <35>
FRD#<35>
CLK_SMB <15,35>EEPROM_WC <35>
KSO[0..15]<35>
KSO16<35> SIO_FD[0..7] <35>
SIO_FA[0..19]<35>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
INT KB
36 51Monday, October 18, 2004
Compal Electronics, Inc.
SUB_6782USMbus address A2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C58
110
0P_0
402_
50V8
J~D
1
2
C58
710
0P_0
402_
50V8
J~D
1
2
C58
210
0P_0
402_
50V8
J~D
1
2
C58
310
0P_0
402_
50V8
J~D
1
2
C57
410
0P_0
402_
50V8
J~D
1
2
U8
MX29LV008BTC-70R_TSOP40~D
A021A120A219A318A417A516A615A714A88A97A1036A116A125A134A143A152A161
A1813
CE#22OE#24
D0 25D1 26D2 27D3 28D4 32D5 33D6 34D7 35
GND 39
A1740
WE#9
VCC 30VCC 31
GND 23
A1937
NC 29NC 38
NC 11
RESET# 10RY/BY# 12
C17
80.
1U_0
402_
16V4
Z~D
1
2
C58
810
0P_0
402_
50V8
J~D
1
2
C57
310
0P_0
402_
50V8
J~D
1
2
C59
210
0P_0
402_
50V8
J~D
1
2
C58
910
0P_0
402_
50V8
J~D
1
2
C3950.1U_0402_16V4Z~D
1
2
C57
610
0P_0
402_
50V8
J~D
1
2
JKYBRD
JAE_FK2S030W11~D
1
3
5
7
11
9
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
3132
3334
C59
310
0P_0
402_
50V8
J~D
1
2
R1510_0402_5%~D
12
C59
010
0P_0
402_
50V8
J~D
1
2
C18
20.
1U_0
402_
16V4
Z~D
1
2
C57
710
0P_0
402_
50V8
J~D
1
2
C58
410
0P_0
402_
50V8
J~D
1
2
C59
410
0P_0
402_
50V8
J~D
1
2
C59
110
0P_0
402_
50V8
J~D
1
2
C20
710
0P_0
402_
50V8
J~D
1
2
C57
810
0P_0
402_
50V8
J~D
1
2
C58
510
0P_0
402_
50V8
J~D
1
2
C57
510
0P_0
402_
50V8
J~D
1
2
C59
510
0P_0
402_
50V8
J~D
1
2
C57
910
0P_0
402_
50V8
J~D
1
2
C58
010
0P_0
402_
50V8
J~D
1
2
C57
210
0P_0
402_
50V8
J~D
1
2
R3960_0402_5%~D
12
C58
610
0P_0
402_
50V8
J~D
1
2
U2
AT24C04N-10SI-2.7_SO8~D
NC1A12A23VSS4
VCC 8WP 7
SCL 6SDA 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MOD_EN
HDD_EN
Z400
5
RUN_D_ENABLE
Z400
6
RUN_ON__D_5V#
RUN_ON_5V#
RUN_ENABLE
RUN_ON_5V#
+5VSUS
+5VHDD
+3VSUS +VCC_CORE
+3VRUN
+5VALW
+15V
+15V
+5VSUS
+5VMOD
+0.9V_DDR_VTT +3VRUN +VCCP+15V
+1.5VRUN
+5VRUN
+5VRUN
+15V+5VALW
+5VSUS
+1.5VSUS
+5VRUN
+1.8VRUN
+1.8VSUS
+1.5VRUN
MODC_EN#<34>
RUN_ON_D<34,41,43>
HDDC_EN#<34>
RUN_ON<19,34,38,42,44>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
POWER CONTROL
37 51Monday, October 18, 2004
Compal Electronics, Inc.
+5HDD Source
2
+5VMOD Source2
+3VRUN Source
Run Planes Enable
1
2
1
2
1 1
2
1
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.5VRUN Source
+5VRUN Source
+1.8VRUN Source
R507100K_0402_5%~D@
12
47K
47K
Q19DTC144EKA_SOT23~D
2
13
R201100K_0402_5%~D 1@
12
G
D
S
Q202N7002_SOT23~D
@2
13
S
GD
Q24SI3456DV-T1_TSOP6~D
3
6
245
1
S
GD Q21
SI3456DV-T1_TSOP6~D
3
624
51
G
D
SQ22
2N7002_SOT23~D
2
13
R49347_0805_5%~D@
12
R198100K_0402_5%~D
12
R47910K_0402_5%~D
12
C54
70.
01U
_040
2_16
V7K~
D
@
1
2
R21
60_
0402
_5%
~D
2@
12
G
D
S
Q462N7002_SOT23~D
@2
13
C28
34.
7U_0
805_
10V4
Z~D
1
2
47K
47K
Q51DTC144EKA_SOT23~D
@
2
13
C28
54.
7U_0
805_
10V4
Z~D
1
2
R1990_0805_5%~D
@1 2
C49
34.
7U_0
805_
10V4
Z~D
1
2
Q23SI4810DY_SO8~D
365
78
2
4
1
G
D
SQ17
2N7002_SOT23~D
2
13
R2190_0402_5%~D
1@
1 2
R18522_0805_5%~D@
12
R53
610
0K_0
402_
5%~D
1
2
C27
30.
01U
_040
2_16
V7K~
D
1
2
R202100K_0402_5%~D
12
R13422_0805_5%~D@
12
R50322_0805_5%~D@
12
R5060_0805_5%~D
1 2
R14810K_0402_5%~D
12
C57
10.
022U
_060
3_50
V4Z~
D 1
2
G
D
SQ18
2N7002_SOT23~D
1@
2
13
R223100K_0402_5%~D
12
R184100K_0402_5%~D1@
12
G
D
S
Q452N7002_SOT23~D
@2
13
G
D
S
Q132N7002_SOT23~D
@2
13
C27
64.
7U_0
805_
10V4
Z~D
1
2
C17
24.
7U_0
805_
10V4
Z~D
1
2
S
GD Q50
SI3456DV-T1_TSOP6~D
@ 3
624
51
C28
447
00P_
0402
_25V
7K~D
1
2
R49222_0805_5%~D@
12
C54
64.
7U_0
805_
10V4
Z~D
1
2
G
D
SQ16
2N7002_SOT23~D
1@
2
13
R22210K_0402_5%~D
12
R21510K_0402_5%~D
12
G
D
S
Q492N7002_SOT23~D
@ 2
13
R200100K_0402_5%~D
12
C25
747
00P_
0402
_25V
7K~D
1@
1
2
R50
410
0K_0
402_
5%~D
12
Q14SI4810DY_SO8~D
365
78
2
4
1
Q44SI4810DY_SO8~D
365
78
2
4
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RUNPWROK
IMVP_PWRGD
5VRUNRC
1.5VSUS_PWRGD
1.5VSUS_PWRGD
Z401
2
RJ_TIPRJ_RING
ICH_PWRGD
ICH_PWRGD#
+COINCELL
+3VSUS+3VRUN
+3VSUS
+3VSUS
+1.5VSUS +3VALW +3VALW
+3VSUS
+3VSUS
+COINCELL
+3.3VX
+RTC_CELL
+COINCELL
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+COINCELL
RUN_ON<19,34,37,42,44>
SUSPWROK <15,23>
RUNPWROK <18,35,43,45>ITP_DBRESET#<7>
RESET_OUT#<35>
IMVP_PWRGD<10,23,45>
SUS_ON<34,42>
ICH_PWRGD# <15>
ICH_PWRGD <23>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Power Good
38 51Monday, October 18, 2004
Compal Electronics, Inc.DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RTC BATT CONN
RJ11 Connector
U26D74VHC08MTC_TSSOP14~D
IN113
IN212 OUT 11
P14
G7
JPHON
SUYIN_100002FR006G202ZL~D
1122
GND13GND24
D15BAT54C_SOT23~D
23
1
EB
CQ28MMBT3904_SOT23~D
2
31
R453100K_0402_5%~D
12
U24A
SN74LVC3G14DCTR_SSOP8~D
P8
A1 Y 7
G4
C5281U_0603_10V4Z~D
1
2
U26A74VHC08MTC_TSSOP14~D
IN11
IN22 OUT 3
P14
G7
R22710K_0402_5%~D
12
R4630_0402_5%~D
1 2
C5200.01U_0402_16V7K~D
1
2
U24B
SN74LVC3G14DCTR_SSOP8~D
P8
A6 Y 2
G4
R4711K_0402_5%~D
12
C23
80.
1U_0
402_
16V4
Z~D1
2
C4830.1U_0402_16V4Z~D
1 2
R230
10K_0402_5%~D
12
U21A
74VHC08MTC_TSSOP14~D
IN11
IN22 OUT 3
P14
G7
G
D
S
Q252N7002_SOT23~D
2
13
U26C74VHC08MTC_TSSOP14~D
IN110
IN29 OUT 8
P14
G7
U21B74VHC08MTC_TSSOP14~D
IN14
IN25 OUT 6
P14
G7
JRTC
SUYIN_060003FA002TX00NL~D
+ 1-2
G
D
S
Q412N7002_SOT23~D
2
13
R224330_0603_5%~D
12
U26B74VHC08MTC_TSSOP14~D
IN14
IN25 OUT 6
P14
G7
C4800.1U_0402_16V4Z~D 1 2
C2870.1U_0402_16V4Z~D
1
2
R494100K_0402_5%~D
12
JCOIN
ACES_85204-0200 @
12
U24C
SN74LVC3G14DCTR_SSOP8~D
P8
A3 Y 5
G4
JWIRE
ACES_85204-0200
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GREEN_LED
SATA_ACT#
BREATH_LED_B
BAT1_LED#
R_CAP
R_NUM
R_SRL
CAP_LED
NUM_LED
SRL_LED
R_MPCI_ACT
SRL_LEDNUM_LEDR_BT_ACT
CAP_LED
R_MPCI_ACT
BAT2_LED#
AMBER_LED
R_BT_ACT
+3VRUN
+5VALW
+3VSUS
+3VRUN
+3VALW
+5VALW
+5VALW
BREATH_LED<35>
BAT1_LED#<35>
SATA_ACT#<22>
SRL_LED#<35>
CAP_LED#<35>
NUM_LED#<35>
BT_ACTIVE<29>
LED_WLAN_OUT<33>
POWER_SW#<15,35>
BAT2_LED#<35>
Title
Size Document Number R ev
Date: Sheet o fTOBAGO-LA2151 0.6
PAD and Standoff
39 51Wednesday, November 03, 2004
Compal Electronics, Inc.
Fiducial Mark
ON/OFF Button
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
For VGA Board
BLUE TOOTH LED POWER SOURCE
H22@H_C315D118
1
10K
47K
Q26DTA114YKA_SC59~D
2
13
EB
CQ5MMBT3904_SOT23~D
2
31
H20H_C102BC236D87
1
PAD4
@PAD-2.5X3
1
FD5
@FIDUCIAL MARK~D
1
R310K_0402_5%~D
1 2
H122@H_C619D63
1
FD6
FIDUCIAL MARK~D
1FD13
FIDUCIAL MARK~D
1
R21330_0603_5%~D
12
R610K_0402_5%~D
1 2
H19H_C260D165
1
R5
220_0603_5%~D
1 2
H13@H_C433D118
1H21
@H_C335O118X142
1
FD4
FIDUCIAL MARK~D
1
H102@H_C291C315D165
1
H4@H_C433D118
1
H23H_C291S252D165
1
R156_0603_5%~D
12
10K
47K
Q30DTA114YKA_SC59~D
2
13
10K
47K
Q2DTA114YKA_SC59~D
2
13
H2@H_C315D98
1
10K
47K
Q35DTA114YKA_SC59~D
2
13
PAD5
@PAD-2.5X3
1
FD3
@FIDUCIAL MARK~D
1
H9@H_C354D110
1
PAD7
@PAD-2.5X3
1
R237330_0603_5%~D
12
FD18
@FIDUCIAL MARK~D
1
H3@H_C433D118
1
H18@H_C433D110
1
R265
330_0603_5%~D1 2
PAD1
@PAD-2.5X3
1
FD1
@FIDUCIAL MARK~D
1
FD8
@FIDUCIAL MARK~D
1
R83.3K_0603_5%~D
12
H15H_C315D165
1
H24H_C291C252D165
1
FD15
FIDUCIAL MARK~D
1
10K
47K
Q1DTA114YKA_SC59~D
2
13
PAD2
@PAD-2.5X3
1
PAD6
@PAD-2.5X3
1
D3
LTST-C155KGKFKT_GRN/ORG~D
2 1
4 3
10K
47K
Q6DTA114YKA_SC59~D
2
13
FD2
@FIDUCIAL MARK~D
1
H16@H_C433D118
1
FD14
@FIDUCIAL MARK~D
1
H1@H_C315D98
1
EB
CQ4MMBT3904_SOT23~D
2
31
H8@H_C354D98
1
R2
56_0603_5%~D
1 2
D1HT-190YG-DT_0603~D
21
FD10
@FIDUCIAL MARK~D
1
FD16
@FIDUCIAL MARK~D
1
H5@H_C315D98
1
PAD3
@PAD-2.5X3
1
R410K_0402_5%~D
1 2
H17@H_C433D118
1
JPSW
SUYIN_127183MA010G211ZR
11 2 233 4 455 6 677 8 899 10 10
D2HT-190YG-DT_0603~D
2 1
FD9
@FIDUCIAL MARK~D
1
FD12
FIDUCIAL MARK~D
1
R231330_0603_5%~D
12
H6@H_C315D98
1
H142@H_C252S315D165
1
R15330_0603_5%~D 1 2
FD11
@FIDUCIAL MARK~D
1
DAL30LA-2151 R EV 0M/B
PCB
FD17
FIDUCIAL MARK~D
1
EB
CQ3MMBT3904_SOT23~D
2
31
FD7
@FIDUCIAL MARK~D
1
H11@H_C315D118
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DCIN+
DOCK DC_IN
PS_ID_IN
PWR_ID
PQ_G
PS_ID_IN
RTC_SHDN#
+DC_IN
+3VALW
+5VALW
+5VALW
+3VALW
PWR_SRC
+3.3VX
DOCK_DC_IN
PS_ID <35>
PS_ID_DISABLE# <35>
ACAV_IN <35,46>
PS_ID_IN
PS_ID_IN
Title
Size Document Number R ev
Date: Sheet o fTOBAGO-LA2151 0.6
+DCIN
40 51Monday, October 18, 2004
Compal Electronics, Inc.
THESE CAPS MUST BENEXT TO JCHG
DC_IN+ Source
Z-series AC AdaptorConnctor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+3.3VX Source
DELL CONFIDENTIAL/PROPRIETARY
PR
124.
7K_0
603_
5%~D
12
PC
20.
47U
_181
2_50
V7M
~D
12
PL1FBM-L11-160808-601LMT 0603~D
12
PR
710
0K_0
402_
1%~D
1
2
PR1840_0402_5%~D
1 2
PR1850_0402_5%~D
1 2
PC
40.
1U_0
805_
50V
7M~D
12
PL3@ OC8070-A301~D
3
1 4
2
PL2FBM-L11-453215-900LMAT_1812~D
1 2
PC
610
U_1
210_
25V
7K~D
12
PR510K_0402_1%~D
1 2
PR
22.
2K_0
402_
5%~D
12
PQ3FDS6679Z_SO8~D
3 6
5
78
24
1
MAX1615EUK_SOT23-5~D
PU1
IN1
GN
D2
OUT 3
5/3+ 4#SHDN5
PR
610
0K_0
402_
1%~D
12
PC
30.
01U
_040
2_25
V7K
~D
12
G
D S
PQ1BSS138_SOT23~D
2
1 3
CB
E
PQ2
MMBT3904_SOT23~D
2
31
HRS_HR33-DL-7~DPJPDC1
Low_PWR 1
DC+_1 2
DC+_2 3
DC-_1 4
DC-_2 5GND_16
GND_27
GND_38
GND_49
MH
1M
H2
PD
2@
DA
204U
_SO
T323
~D 231
PR
11
150K
_040
2_1%
~D
12
PC
11U
_060
3_10
V6K
~D
12
PC
50.
1U_0
805_
50V
7M~D
12
PR
183
@ 4
.7K
_040
2_5%
~D1
2
PR186@0_0402_5%~D
1 2
PC
70.
1U_0
603_
25V
7K~D
12
PR
1015
K_0
402_
1%~D
12
PR
1310
0K_0
402_
1%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Z4304Z4305Z4306
PBATT+
+3VALW
+3VALW
+2.5VRUN+2.5VRUNP
+5VSUS
+3VSUS +2.5VRUNP
+VCHGR
PBAT_SMBDAT <19,35,46>PBAT_PRES# <35>
PBAT_SMBCLK <19,35,46>
PBAT_ALARM# <35>
2P5V_PWRGD
RUN_ON_D<34,37,43>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Battery Conn./+2.5V
41 51Monday, October 18, 2004
Compal Electronics, Inc.
Primary Battery Connector
ESD Diodes
1
2
3
4
5
6
7
8
9
SUYIN_20175A-09G1TOP view
R1=R2* (Vo/ 0.8 -1), R2:25K~100K.+2.5VRUN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DELL CONFIDENTIAL/PROPRIETARY
PR18.2K_0402_5%~D
12
PC
121U
_060
3_10
V6K~
D
12
PC90.1U_0805_50V7M~D
12
PD9@ DA204U_SOT323~D
231
PC
80.
1U_0
603_
25V7
K~D
12
PR23100_0402_5%~D
1 2PC
1022
00P_
0402
_50V
7K~D
12
PC
110.
1U_0
603_
25V7
K~D
12
PC
140.
1U_0
603_
25V7
K~D
12MAX1806EUA25_8UMAX~D
PU2
IN1
IN2
POK3
SHDN#4 GND1 5
SET 6
OUT 7
OUT 8
GND2 9
PR
25@
10K_
0402
_1%
~D 12
PR
2630
.9K_
0402
_1%
~D
12
PR20100_0402_5%~D
1 2
PL6FBM-L11-453215-900LMAT_1812~D
1 2
PR
1910
K_04
02_1
%~D
12
PR
2466
.5K
_040
2_1%
~D
12
PD12@ DA204U_SOT323~D
231
PC
1310
U_1
206_
6.3V
7K~D
12
PD11@ DA204U_SOT323~D
231PD10
@ DA204U_SOT323~D
231
PR22100_0402_5%~D
1 2
PR21100_0402_5%~D
1 2
PJP2
SUYIN_200275MR009G516ZL~D
BATT1+ 1
SMB_CLK 3SMB_DAT 4
BATT_PRES# 5SYSPRES# 6
BATT2- 9GND10GND11
BATT2+ 2
BATT_VOLT 7BATT1- 8
PJP3
PAD-OPEN 4x4m
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
15V
S
MAX
1999
_SKI
P#
PWR_SRC
+5VSUSP
+5VALW
+3VALW
VCC_MAX1999
+3VSUSP
VCC_MAX1999
+3VSUSP
+5VSUS
+15V
+3VSUSP
+15VP
+5VSUSP
+3VSUS
VCC_MAX1999
+15VP
SUS_ON<34,38>
THERM_STP#<15>
SUS_ON<34,38>
SUSPWROK_5V <44>
ALWON<35>RUN_ON <19,34,37,38,44>
Title
Size Document Number R ev
Date: Sheet o fTOBAGO-LA2151 0.6
+3.3V/+5V/+15V
42 51Monday, October 18, 2004
Compal Electronics, Inc.
Place these CAPsclose to FETs
Place these CAPsclose to FETs
(150mA,Via NO.= 2)
(6A,240mils ,Via NO.= 12)
(4A,160mils ,Via NO.= 8)
Design current 3.4A for +3.3VSUSP Design current 4A for +5VSUS
DC/DC +3V/ +5V/ +15V
Peak current 4.758A for +3VSUSP Peak current 5.7A for +5VSUSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
OCP point is from 5A to 8A OCP point is from 6A to 9A
DELL CONFIDENTIAL/PROPRIETARY
+
PC
2933
0U_D
3L_6
.3V
_R25
~D
1
2
PL22FBM-L11-453215-900LMAT_1812~D
1 2
PR50@ 0_0402_5%~D
12
PR
34@
0_0
603_
5%~D 1
2
PJP6
PAD-OPEN 4x4m
1 2
PR
400_
0402
_5%
~D1
2
PR480_0402_5%~D
12
PC
210.
1U_0
805_
50V
7M~D
12
PU3
MAX1999EEI_QSOP28~D
SHDN6
BST328
DH326
LX327
DL324
OUT322
LX5 15
DL5 19
FB5 9PRO 10
ILIM5 11ILIM3 5REF 8
V+20
VCC17
LDO5 18
BST5 14
DH5 16
OUT5 21N.C. 1
TON 13GND 23
SK
IP12
LDO325
FB37
ON33ON54
PGOOD 2
PJP4
PAD-OPEN 4x4m
1 2
PD
14R
B71
7F_S
OT3
23~D
2 31
PR
450_
0402
_5%
~D
12
PR
350_
0603
_5%
~D
12
PR412K_0402_1%~D
1 2
PC
180.
1U_0
805_
50V
7M~D
12
PC
331U
_060
3_10
V6K
~D
12
PL84.7uH +-30% STQB1252-4722A_7A~D
14
32
PJP5
PAD-OPEN 4x4m
1 2
PR
3749
.9K
_040
2_1%
~D
12
PR
360_
0603
_5%
~D
12
PC
36@
100
0P_0
402_
50V
7K~D
12
PC
300.
1U_0
603_
25V
7K~D
12
PR
31@
0_0
603_
5%~D1
2
PD
13E
C11
FS2_
SO
D10
6~D
21
PC
224.
7U_1
206_
25V
6K~D
12
PC
2522
00P
_040
2_50
V7K~
D
12
PQ
4S
I480
0DY
-T1_
SO
8~D
365 7 8
2
4
1
PR330_0603_5%~D
12
PR
211
10_1
206_
5%~D
12
PR290_0603_5%~D
1 2
PC
241U
_060
3_10
V6K
~D
12
PQ6SI4810DY_SO8~D
365 7 8
2
4
1
PR
4724
0K_0
402_
5%~D
12
PL94.7U_SPC-1205P-4R7B_+40-20%~D
1 2
+
PC
3133
0U_D
3L_6
.3V
_R25
~D
1
2
PC
344.
7U_1
206_
10V
7K~D
12
PR2847_0603_5%~D
12
FDS6994S_SO8~DPQ5
G22D2 8
S13 D1 5
S21 D2 7
G14D1 6
PR
3868
K_0
402_
1%~D
12
PC
320.
1U_0
603_
25V
7K~D
12
PR
46@
0_04
02_5
%~D
12
PR320_0603_5%~D
1 2
PR
51@
0_0
402_
5%~D 1
2
PC
156
2.2U
_120
6_25
V7K
~D
12
PR
188
150K
_040
2_1%
~D
12
PR203100_0805_5%~D
1 2
PR
39@
0_0
402_
5%~D
12
PC
260.
1U_0
805_
50V
7M~D
12
PC270.1U_0603_25V7K~D
1 2
PR491K_0402_1%~D
1 2
PR300_0603_5%~D
1 2
PC
204.
7U_1
206_
25V
6K~D
12
PC
1710
U_1
206_
25V
6M~D
1
2
PC
1922
00P
_040
2_50
V7K~
D
12
PR
4460
.4K
_040
2_1%
~D
12
PC
231U
_060
3_10
V6K
~D
12
PC280.1U_0603_25V7K~D
12
PC
1610
U_1
206_
25V
6M~D
1
2
PC
152.
2U_1
206_
25V
7K~D
12
PR
4210
0K_0
402_
1%~D
12
PD
35M
MB
Z524
5B_S
OT2
3~D
1
2 3
PR
2710
_120
6_5%
~D
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
MAX
1845
_VC
C
MAX1845_VCC
VCCP_PWRGD
+VCCP_1P05VP
PWR_SRC
+5VSUS
+1.5VSUSP
+1.5VSUSP
+VCCP
+1.5VSUS
+VCCP_1P05VP
+3VRUN
SUSPWROK_1P8V<44>
RUNPWROK<18,35,38,45>
RUN_ON_D<34,37,41>
VCCP_PWRGD<45>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
+1.5VSUSP /+VCCP_1P05VP
43 51Monday, October 18, 2004
Compal Electronics, Inc.
+1.5VSUSP / +VCCP_1P05VP
Design current 3A for +1.5VSUSP
Design current 5A for +VCCP_1P05VPPeak current 4.034A for +1.5VSUSP
Peak current 7.124A for +VCCP_1P05VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
OCP point is from 4.5A to 7A
OCP point is from 7.5A to 11A
DELL CONFIDENTIAL/PROPRIETARY
PR530_0603_5%~D
1 2
PR21711K_0402_1%~D
12
PC
8310
00P_
0402
_50V
7K~D
12
PR
6320
K_06
03_1
%~D
12
PD19
RB751V-40_SOD323~D
2 1
PC
4210
U_1
206_
25V6
M~D
1
2
PJP7
PAD-OPEN 4x4m
1 2
PR
216
33K_
0402
_5%
~D
12
PC
531U
_060
3_10
V6K~
D
12
PR600_0402_5%~D
12
PD
15R
B75
1V-4
0_SO
D32
3~D
21
PR
6520
K_06
03_1
%~D
12
PC
520.
1U_0
603_
25V7
K~D
12
PC
3710
U_1
206_
25V6
M~D
1
2
PC
54@
100
0P_0
402_
50V7
K~D
12
PC
3922
00P_
0402
_50V
7K~D
12
PC
50@
1U_0
603_
10V6
K~D
12
PC
4310
U_1
206_
25V6
M~D
1
2
PR
5220
_060
3_1%
~D
12
PR540_0603_5%~D
12
PC
460.
1U_0
603_
25V7
K~D
12
PQ9FDS6676S_SO8~D
365 7 8
2
4
1
+
PC
4822
0U_D
2_4V
M~D
1
2
G
D
S
PQ372N7002_SOT23~D
2
13
PR
6880
.6K_
0402
_1%
~D
12
PC
444.
7U_0
805_
6.3V
6K~D
12
PC
490.
1U_0
603_
25V7
K~D
12
PR80@ 0_0402_5%~D
12
PR
570_
0603
_5%
~D
12
PC
470.
1U_0
603_
25V7
K~D
12
PR810_0402_5%~D
12
PC
4022
00P_
0402
_50V
7K~D
12
PL114.4UH_CDRH125-4R4NC_5A_+30%-20%~D
13
24
PR55
0_0603_5%~D
1 2
PR
61@
0_0
402_
5%~D
12
PJP1
PAD-OPEN 4x4m
1 2
PR
6790
.9K_
0402
_1%
~D
12
PR
64
150K
_040
2_1%
~D
12
PR
6210
0K_0
402_
1%~D
12
FDS6994S_SO8~DPQ8
G22D2 8
S13 D1 5
S21 D2 7
G14D1 6
PD
18R
B75
1V-4
0_SO
D32
3~D
21
PL23FBM-L11-453215-900LMAT_1812~D
1 2
PD
16R
B75
1V-4
0_SO
D32
3~D
21
PC
451U
_060
3_10
V6K~
D
12
PR560_0603_5%~D
1 2
PJP8
PAD-OPEN 4x4m
1 2
PC
380.
1U_0
805_
50V7
M~D
12
PR
591K
_060
3_1%
~D
12
PD
17R
B75
1V-4
0_SO
D32
3~D
21
PR6610K_0402_5%~D
12
+
PC
5133
0U_D
2E_2
.5VM
_R9~
D
1
2
PU5
MAX1845EEI_QSOP28~D
OUT215
BST219
FB214
CS216
VDD
21
UVP9
SKIP6
V+4
GN
D23
ON111
DH1 26
LX1 27
ILIM2 13
DL1 24
VCC
22
PGOOD7
FB1 2
ON212
ILIM1 3OVP8
REF 10
LX217
DL220
TON 5
CS1 28
BST1 25
DH218
OUT1 1
PQ7IRF7811AV_SO8~D
365 7 8
2
4
1
PL121.5uH_SIL104-1R5_10A_30%~D
1 2
PR
5810
.5K_
0603
_1%
~D
12
PC
410.
1U_0
805_
50V7
M~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TP0
TP0
+1.8VSUSP
+0.9V_DDR_VTTP +0.9V_DDR_VTT
+1.8VSUS
+5VSUS
PWR_SRC
+5VSUS
+0.9V_DDR_VTTP
+3VSUS
+1.8VSUSP
+1.8VSUSP
+1.8VSUSP
+1.5VSUS
SUSPWROK_1P8V <43>
SUSPWROK_5V <42>
V_DDR_MCH_REF <10,16,17>
RUN_ON <19,34,37,38,42>
+0.9V_PWRGD
SUSPWROK_5V <42>
SUSPWROK_5V<42>
Title
Size Document Number R ev
Date: Sheet o fTOBAGO-LA2151 0.6
44 51Monday, October 18, 2004
Compal Electronics, Inc.(3A,200mils ,Via NO.=6)
(10A,320mils ,Via NO.=20)
DDR2 Termination +1.8VSUSP/ +0.9V_DDR_VTT
Design current 7A for +1.8V_SUSPPeak current 10.1A for +1.8VSUSP
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
+1.8VSUSP/ +0.9V_DDR_VT
Design current 1.05A for +0.9V_DDR_VTTPPeak current 1.5A for +0.9V_DDR_VTTP
OCP point is 12.7A for +1.8VSUSP
IC
MAX8550
MAX8550A
Pop Un-pop
PR197,PQ36
PR212
PR212 PR197, PQ36
PR
194
100K
_040
2_1%
~D
12
PJP17
PAD-OPEN 4x4m
1 2
PC
5610
U_1
206_
25V
6M~D
1
2
PR
193
10_1
206_
5%~D
12
PR20420_0603_1%~D
12
PJP16
PAD-OPEN 4x4m
1 2
PC14610U_1206_6.3V7K~D
12
+
PC
7033
0U_D
3L_6
.3V
_R25
~D
1
2
PD
20R
B75
1V-4
0_S
OD
323~
D
21
PL141.4UH_CEP125-1R4_15.5A_20%~D
1 2
PQ
34IR
F782
1_S
O8~
D
S1
S2
S3
G4
D8
D7
D6
D5
PJP11
PAD-OPEN 4x4m
1 2
PC
158
1000
P_0
402_
50V7
K~D
12
PJP9PAD-OPEN 4x4m1 2
PR
8217
.4K
_060
3_1%
~D
12
PR84@ 0_0402_5%~D
12
PC
740.
1U_0
603_
25V
7K~D
12
PR
7827
.4K
_060
3_1%
~D
12
PR730_0603_5%~D
12
PQ
11FD
S77
88_S
O8~
D
36 578
2
4
1
PC1550.22U_0603_10V7K~D
12
PC680.1U_0603_25V7K~D
12
PC
152
10U
_120
6_6.
3V7K
~D
12
PC
6610
00P
_040
2_50
V7K~
D
12
PR2150_0402_5%~D
1 2
PJP10PAD-OPEN 4x4m1 2
PR20248.7K_0402_1%~D
12
PC
5510
U_1
206_
25V
6M~D
1
2
PC
641U
_060
3_10
V6K
~D
12
PC770.1U_0603_25V7K~D
12
PL24FBM-L11-453215-900LMAT_1812~D
1 2
PR212@0_0402_5%~D
12
PR213@ 0_0402_5%~D
12
PC
631U
_060
3_10
V6K
~D
12
PR
195
100K
_040
2_1%
~D
12
PU6MAX8550ETI_TQFN28~D
SK
IP25
VD
D22
PGND123
LX19
AV
DD
26
REF3
TON1
OV
P/ U
VP
2
SS
8
GN
D24
POK1 5
POK2 6
VTT 12
STBY 7
SH
DN
B28
VOUT16 REFIN 14
FB15
VTTR 10
ILIM
4
PGND2 11
DH18
DL21
VTTS 9
SHDNA 27
VIN 17BST20
VTTI 13
G
D
S
PQ362N7002_SOT23~D
2
13
PC
153
10U
_120
6_6.
3V7K
~D
12
PC
720.
1U_0
603_
25V
7K~D
12
PR
200
100K
_040
2_1%
~D
12
PC
570.
1U_0
805_
50V
7M~D
12
PR
197
100K
_040
2_1%
~D1
2
PC
157
10U
_120
6_6.
3V7K
~D 12
PC
624.
7U_1
206_
10V
7K~D
12
PC
5822
00P
_040
2_50
V7K~
D
12
PC
154
10U
_120
6_6.
3V7K
~D
12
+
PC
7133
0U_D
3L_6
.3V
_R25
~D
1
2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
MAX1987_REF
MAX1987_VCC
CPU_PWR_SRC
MAX1987_REF
VID0
VID4VID3
VID1
VID5
VID2
MAX1987_REF
MA
X1987_R
EF
MA
X1987_R
EF
PWR_SRC
CPU_PWR_SRC
+VCC_CORE
+VCC_CORE
CPU_PWR_SRC
+VCC_CORE
+5VRUN
+3VRUN
+3VRUN
+3VRUN
+5VRUN
+5VRUN
MAX1987_VCC
MAX1987_VCC
MAX1987_VCC
MAX1987_VCC
CLK_ENABLE#<6,11>
CLK_ENABLE#<6,11>
DPRSLPVR<23>
VCCP_PWRGD<43>
CLK_ENABLE#<6,11>
VID4<8>VID3<8>
VID1<8>
IMVP_PWRGD<10,23,38>
VID2<8>
H_STP_CPU#<6,23>
DPRSLPVR<23>
H_PSI#<8>
RUNPWROK<18,35,38,43>
VID0<8>
VID5<8>
Title
Size Document Number R ev
Date: Sheet o fTOBAGO-LA2151 0.6
+VCORE
45 51Monday, October 18, 2004
Compal Electronics, Inc.
VID 0VID 5
0
VID 4 VID 2
V I D
1
VID 1
1
11
0 1
1
0
0
1
VID 3
1
00
1
Vcore
0.748
V
1.484
1 0
0.956
1.308
1 0
11 0 1 1
1
The C4 Mode voltageis 0.748V, S2 open
PBOOT voltage seeting up on 1.212V
Output Capatitors in H/W, ESR=3m ohms
(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/us(c): EXIT SUSPEND (SUS=LOW, RUNPWROK=HIGH): 24.7mV/us
TRANSITION TIMING:
Change PR130:30.9k. Delete PR128/PR129/PR132/PR133/PR136/PQ21/PQ22/PQ23/PQ24 for BANIAS and DOTHANPR128/PR129/PR132/PR133/PR136/PQ21/PQ22/PQ23/PQ24 are only for YONAH CPU.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Remote Vcore sense
DELL CONFIDENTIAL/PROPRIETARY
PC
8510
U_1
206_
6.3V
7K~D
12
PR
124
2.2_
0603
_5%
~D
12
PC
9210
U_1
210_
25V
7K~D
12
+
PC
138
@ 1
5U_D
2_25
M_R
90~D
1
2
PQ
20@
IRF7
832_
SO
8~D
365 7 8
2
4
1
G
D
S
PQ23@2N7002_SOT23~D
2
13
PR103@0_0402_5%~D
12
PR
128
@15
K_0
402_
1%~D 1
2
PR111 0_0402_5%~D
12
PC
82@
10U
_121
0_25
V7M
~D1
2
PL21FBM-L11-453215-900LMAT_1812~D
1 2
PQ
15@
IRF7
832_
SO
8~D
365 7 8
2
4
1
PC
841U
_060
3_10
V6K
~D
12
PR206 0_0603_5%~D
12
PR1021K_0402_1%~D
1 2
PR135@0_0402_5%~D
12
+
PC
159
220U
_25V
_M
1
2
PR1210_0402_5%~D
12
PL180.36U_ETQP4LR36WFC_24A_20%~D
1 2
PR105 @0_0402_5%~D12
PR209 0_0603_5%~D
12
+
PC
137
@ 1
5U_D
2_25
M_R
90~D
1
2
PC
93@
10U
_121
0_25
V7M
~D1
2PC
890.
1U_0
805_
50V
7M~D
12
PR
972.
2_06
03_5
%~D
12
PC
960.
1U_0
603_
25V
7K~D
12
PC
9427
0P_0
402_
50V7
K~D
12
PR960.001_2512_5%~D
1 2
PR
9510
K_0
402_
1%~D
12
PR
127
20.5
K_0
402_
1%~D
12
PR207 0_0603_5%~D
12
PU7
MAX1987ETM_TQFN48
TIME1
TON2
B03 B14 B25
S06 S17 S28
SHDN#9
REF10
ILIM11
VC
C12
GND 13
CCV14
PO
S15
NE
G16
CCI 17
FB 18
OAIN- 19
OAIN+ 20
PSI#21
SYSOK22
IMVPOK23
CLKEN#24
D525D426D327D228D129D030
DD0# 31
BSTM 32
LXM 33DHM 34
DLM 35
VD
D36
PGND 37
DLS 38
DHS 39LXS 40
BSTS 41
SUS43
DPSLP#44
CMN 46
CSN 47
V+ 42
CMP 45
CSP 48
PQ
19IR
F783
2_S
O8~
D
365 7 8
2
4
1
G
D
S
PQ24@BSS138_SOT23~D
2
13
PR
130
30.9
K_0
402_
1%~D
12
PC
950.
22U
_060
3_10
V7K
~D
12
PC88470P_0402_50V7K~D 1 2
PR
123
@0_
0402
_5%
~D 12
PR107@0_0402_5%~D
12
PR1250.001_2512_5%~D
1 2
+
PC
135
@ 1
5U_D
2_25
M_R
90~D
1
2
PR136@100K_0402_1%~D
1 2
PR
120
100K
_040
2_1%
~D
12
PR116 0_0402_5%~D
12
PC
7922
00P
_040
2_50
V7K~
D
12
PR208 0_0603_5%~D
12
PR
114
@0_
0402
_5%
~D 12
PR
110
3.01
K_0
402_
1%~D
12
PQ
14@
IRF7
821_
SO
8~D
S1
S2
S3
G4
D8
D7
D6
D5
PC
9110
U_1
210_
25V
7K~D
12
PC
9710
0P_0
402_
50V8
K~D
12
PC
870.
01U
_040
2_25
V7K
~D
12
PR
9110
_080
5_5%
~D
12
PR
126
@0_
0402
_5%
~D 12
PD
23@
EC
31Q
S04
~D
21
PR
189
@0_
0402
_5%
~D
12
PR
129
@36
K_0
402_
5%~D 1
2
PR1151M_0402_1%~D
1 2
PQ
13IR
F782
1_S
O8~
D
S1
S2
S3
G4
D8
D7
D6
D5
PC
860.
1U_0
603_
25V
7K~D
12
PR
190
@0_
0402
_5%
~D
12
PR2180_0402_5%~D
12
PQ
17@
IRF7
821_
SO
8~D
S1
S2
S3
G4
D8
D7
D6
D5
PR1041K_0402_1%~D
1 2
PR
219
@0_
0402
_5%
~D
12
PR
122
@0_
0402
_5%
~D1
2
PR101
3.01K_0402_1%~D
12
PR210 0_0603_5%~D
12
PD
25R
B75
1V-4
0_S
OD
323~
D
21
PR
100
0_04
02_5
%~D
12
PR132@100K_0402_1%~D
1 2
PR
134
100K
_040
2_1%
~D
12
PC
9022
00P
_040
2_50
V7K~
D
12
PR1061K_0402_1%~D
1 2
PR
112
0_04
02_5
%~D
12
PR119@0_0402_5%~D
12
G
D
S
PQ21@2N7002_SOT23~D
2
13
PR205 0_0603_5%~D
12
PC
780.
1U_0
805_
50V
7M~D
12
PC
980.
01U
_040
2_25
V7K
~D
12
PR1311.24K_0402_1%~D
12
PR
9410
K_0
402_
1%~D
12
PR1081K_0402_1%~D
1 2
PR
98@
0_04
02_5
%~D
12
PR117@0_0402_5%~D
12
PQ
16IR
F783
2_S
O8~
D
365 7 8
2
4
1
PQ
18IR
F782
1_S
O8~
D
S1
S2
S3
G4
D8
D7
D6
D5
PD
22R
B75
1V-4
0_S
OD
323~
D
21
PR
220
@0_
0402
_5%
~D
12
PL170.36U_ETQP4LR36WFC_24A_20%~D
1 2
PD
24@
EC
31Q
S04
~D
21
PC
8010
U_1
210_
25V
7K~D
12
G
D
S
PQ22@2N7002_SOT23~D
2
13
PR
113
0_04
02_5
%~D
12
PC
8110
U_1
210_
25V
7K~D
12
+
PC
136
@ 1
5U_D
2_25
M_R
90~D
1
2
PR191
@0_0402_5%~D
12
PR133@0_0402_5%~D
12
PR109 0_0402_5%~D
12
PR
931.
91K
_060
3_1%
~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CHVREF
CHVREF
CHVREF
PDS
PDL
PDS
PDL
+VCHGR
+DC_IN
+VCHGR+5VALW
+SDC_IN
+VCHGR
PWR_SRC +SDC_IN
+DC_IN
PBAT_SMBDAT <19,35,41>
PBAT_SMBCLK <19,35,41>
CHG_PBATT<35>
ACAV_IN<35,40>
ACAV_IN <35,40>
ACAV_IN<35,40>
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Charger
46 51Monday, October 18, 2004
Compal Electronics, Inc.
Connect GND side of PC118,PC119, PC120 to GNDthrough 1 via.
IMAX=0.654VMaximum charger current=3.271A
VMAX=2.625VMaximum charger voltage=13.12V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+DC_IN discharge path
Adress : 12H
DELL CONFIDENTIAL/PROPRIETARY
PR155102K_0402_1%~D
12
PR1450.01_2512_1%~D
1 2
PR
153
59K_
0402
_1%
~D
12
PC
125
@0.
1U_0
603_
25V7
K~D
12
PR1380.01_2512_1%~D
1 2
PR167@0_0402_5%~D
1 2
PC
103
2200
P_04
02_5
0V7K
~D
12
PR16110K_0805_5%~D
12
PD
27@
EC
31Q
S04
~D
21
PU8
MAX1535BETJ TQFN32~D
DHI 26
CSIN 20
DLO 23
SDA 14
CCS6
CCV8
CSS
P29
PDS31
THM13
VDD12
SRC27
ACIN3
ACOK32
DCIN1
CCI7
LDO 2
VMAX 9
BATT19
DLOV 24
PDL30
DHIV 25
CSS
N28
SCL 15INT16
CSIP 21
PGND 22
DAC11
REF4G
ND
18
IMAX
10
GN
D5
I.C.17
PC110
0.01U_0402_25V7K~D
1 2
PC
113
10U
_121
0_25
V7K~
D
12
PR16210K_0402_1%~D
12
PR15852.3K_0402_1%~D
12
PC
9910
U_1
210_
25V7
K~D
12
PC
115
@10
U_1
210_
25V7
K~D
12
PR
192
16.2
K_04
02_1
%~D
12
PC
122
1U_0
603_
10V6
K~D
12
PR164@0_0402_5%~D
12
FDS
6670
S_S
O8~
DPQ
27
365 7 8
2
4
1
PC
106
10U
_121
0_25
V7K~
D
12P
C10
40.
1U_0
805_
50V7
M~D
12
PC
127
2200
P_04
02_5
0V7K
~D
12
PC
121
0.1U
_060
3_25
V7K~
D
12
PR
156
182K
_040
2_1%
~D
12
PR
141
10K_
0402
_1%
~D
12
G
D
S
PQ31
2N70
02_S
OT2
3~D
2
13
PC
100
@0.
1U_0
603_
25V7
K~D
12
PR1520_0402_5%~D
1 2
PR1470_0805_5%~D
12
PR
154
10K_
0402
_1%
~D
12
PC
118
0.01
U_0
402_
25V7
K~D
12
PL208.2U_CEP125-8R2MC_5.8A_20%~D
1 2
PR
144
33_0
603_
5%~D
12
PR
160
100K
_040
2_1%
~D
12
PD30@B540C~D
21
PR1510_0402_5%~D
1 2
PL19FBM-L11-453215-900LMAT_1812~D
1 2
PC
120
0.01
U_0
402_
25V7
K~D
12
PQ25SI4835DY_SO8~D
365 7 8
2
4
1
PR
150
10K_
0402
_1%
~D
12
PR
139
0_04
02_5
%~D
12
PC
128
0.1U
_080
5_50
V7M
~D
12
PR
148
0_04
02_5
%~D
12
PR163
100K_0402_1%~D
12
PC1091U_0603_10V6K~D
1 2
PR
142
365K
_040
2_1%
~D
12
PC
105
10U
_121
0_25
V7K~
D
12
PC
101
@0.
1U_0
603_
25V7
K~D
12
G
D
S
PQ28BSS138_SOT23~D
2
13
PR157280K_0402_1%~D
12
PC
124
@0.
1U_0
603_
25V7
K~D
12
PR14349.9K_0402_1%~D
12
PC
123
1U_0
603_
10V6
K~D
12
G
D
S
PQ302N7002_SOT23~D
2
13
PR1660_0402_5%~D
1 2
PQ33SI4825DY_SO8~D
3 65
78
2
4
1
PC
112
0.1U
_080
5_50
V7M
~D
12
PC
126
1500
P_04
02_5
0V7K
~D
12
PR
149
0_04
02_5
%~D
12
PC
116
@10
U_1
210_
25V7
K~D
12
PD28
RB751V-40_SOD323~D
2 1
PQ29SI4825DY_SO8~D
365
78
2
4
1
PR
159
10K_
0402
_1%
~D
12
PC
119
0.01
U_0
402_
25V7
K~D
12
PC1111U_0603_10V6K~D
1 2
PD29@B540C~D
2 1
PR
168
470K
_040
2_5%
~D
12
PC
102
1U_0
805_
25V4
Z~D
12
PC
117
@10
00P_
0402
_50V
7K~D
12
PC
114
10U
_121
0_25
V7K~
D
12
PC
107
@ 1
0U_1
210_
25V7
K~D
12
PR165100K_0402_1%~D
12
PR1460_0402_5%~D
1 2
PC
108
1U_0
805_
25V4
Z~D
12
PR
140
0_04
02_5
%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Changed-List History 1/2
47 51Monday, October 18, 2004
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
1 0.1
2
Title
3
Change R1251 (0_0402_5%~D) to C34(1000P_0402_50V7K~D) Roger01/19H/W30 R2151 tie +3VLAN to GND via LAN transformer
39 H/W 01/19 RogerThe light of WLAN and Blue tooth LED toodim Change R8, R15 from 330 ohm to 56 ohm
0.1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
34 H/W 01/19 Roger Add the COM port debug circuit Add U184 for COM port debug
0.1
4
ALL H/W 01/19 Roger Rename component location for manufacture Update schematic and board file component reference
0.1
5 36 H/W 01/28 Roger Rotate the Keyboard connector 180 degreeReconnect keyboard signals to CN1,CN2,CN3,CN4,CN5,C207 for layoutsmoothly 0.1
6 36 H/W 01/30 Roger Keep more spacing for VGA thermal solution Delete JP3 debug port to save spacing for ROM part placement 0.1
7 12 H/W 02/03 Roger +2.5VRUN is margin for 2N7002 Change Q7,Q27,Q31,Q33 gate voltage from +2.5VRUN to +3VRUN 0.1
8 06 H/W 02/04 RogerChange R330 and R354 to 0 ohms per Intelreview. Change R330 and R354 from 1K to 0 ohms 0.1
9 38 H/W 02/04 RogerResolves the issue where 1.5VSUS_PWRGDgoes high before +1.5VSUS Change R230 from 330 to 10K ohm and R227 from 1K to 10K ohms 0.1
0.1Change Q44 from SI3456 to SI4810 that have lower Rds on.10 Roger02/09H/W37Resolves the issue where +1.5VRUN drop100 mV from +1.5VSUS to +1.5VRUN.
11 18 H/W 02/09 Roger Add a bulk cap for G_PWR_SRC Add C569 for G_PWR_SRC placement near JVID 0.1
12 39 H/W 02/09 RogerBAT1_LED# should drive the GREEN LED,BAT2_LED# should drive the ORANGE LED Change R5 pin 2 connect to D3 pin4, R265 pin2 connect to D3 pin2 0.1
13 21 H/W 02/09 Roger Follow X01 Gerber Gate Checklist item 11Change R328 from 0 ohm to 1K ohm and add note "Pop resistor to bootfrom PCI". 0.1
14 38 H/W 02/09 RogerFollow X01 Gerber Gate Checklist item 12,ICH_PWRGD circuit match Laguna Remove R470 and no connect U21B, RESET_OUT# connector to U21A pin 2. 0.1
15 35 H/W 02/09 Roger Change Board ID to X01 Depop R419 and populate R405
16 35 H/W 02/09 RogerSystem will auto power on when AC plug inif RTC coin battery not implement Change C130 from 1U to 100P to reduce POWER_SW_IN# rising time.
0.1
0.1
17 06 H/W 02/10 RogerReserve SSC clock for internal graphicfor clock generator ICS954206
96MHz SSC clock connect to U16 pin 17,18. Add the serie damping R524,R525, pull down resistor R522, R523. 0.1
18 ALL H/W 02/11 RogerChange connector name to match the namingrule
Change JP5 to JMOD, JP6 to JWIRE, JP2 to JPSW, JP1 to JLVDS, JP4 toJCRT 0.1
19 23 H/W 02/16 Roger+1.5VRUN leakage issue at system into S3status ICH6M GPIO24 connect to SIO_EXT_WAK# for option the GPIO power plane 0.1
20 39 ME 02/17 Roger Change screw hole size for system assemblyH15 change diameter form 3 mm to 4.2 mm, H18 change diameter from 3 mmto 2.8 mm 0.1
21 34 H/W 02/22 Roger Depop R116 and pop R114, Depop R119 and pop R128 0.1
22 35 H/W 02/22 Roger 0.1C130 change from 100P 0603 to 1U 0603
Change the power source from +RTC_CELL to+3.3VXAuto power on when AC plug in issue willbe using the BIOS fix
23 39 H/W 03/12 Roger LED_WLAN_OUT should drive green LED Change R15 from 56 ohms to 330 ohms 0.1
24 29,39 H/W 03/12 RogerBlue tooth and meida blue LED trun onvoltage Vf is 2.7 to 3.9V. +3.3V have riskdon't trun on LED.
Change Q4 pin 1 and JLCM pin19 power source from +3VALW to +5VALW 0.1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Changed-List History 1/2
48 51Monday, October 18, 2004
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
25 0.3
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
35 H/W 03/17 RogerSIO SM Bus EA measure issue for rising andfalling time R131, R444, R447, R449 change from 22K ohms to 8.2K ohms
26 6 H/W 03/17 RogerICH SM Bus EA measure issue for rising andfalling time R270, R275 change from 100K ohms to 2.2K ohms 0.3
27 19 H/W 03/17 RogerLCDVDD component unnecessary for externalboard
Depop Q8, Q9,Q10, Q37, R35, R54, R263, R272, C29, C315 on externalboard and pop on internal board 0.3
28 13 H/W 03/18 RogerRemove CRT, LVDS, TV DAC power beads andcaps 0.3
Depop L9, L10, L11, L25, L26, L24, C24, C291, C293, C22, C298, C299,C23, C323, C310, C297, C314, C331, C322, C37, C35, C305, C306, C36,C304 on external board and pop on internal board
29 31 H/W 03/19 RogerCard bus EA measure CBS_CCLK rising andfalling failure issue R495 change from 47 ohms to 22 ohms 0.3
30 27 H/W 03/23 Roger ME change audio jacks to combined jack Change JAUDIO symbol to combined two jacks, delete JHP 0.3
31 15 H/W 03/25 RogerPT layout issue list item 6, consistentwith other platforms Change U15 pin 10 power source from +3.3VX to +RTC_CELL
32 26 H/W 03/25 RogerLayout issue list item 16, pop issue andthe static noise during post and idle inWindows
0.3
Add a non-popped inverter U30 add a 0 ohm R528 around the inverter 0.3
33 25 H/W 03/25 RogerIssue list item 8, connect UART interfaceto ICH GPIO for debug
Connect U11 pin 45 (UAO) to ICH6 pin AC18 (GPIO34). Connect U11 pin43 (UAI) to ICH6 pin AF20 (GPIO33) 0.3
34 26 H/W 03/25 RogerIssue list item 11, allow the capabilityto disable the line in option
Connect a no popped 0 ohm R529 from LINE_IN_L to 9750_PHONE. Connect ano popped 0 ohm R530 from LINE_IN_R to 9750_PHONE 0.3
Issue list item 12, blue LED to dimLED & R58 move to collection side of BJT. Q4 pin 3 connect to GND,JPSW pin 2 change to connect +5VALW. 0.3Roger03/25H/W3935
03/25 Roger36 18 H/W Issue list item 9, C569 not require fo now Add non-popped symbol for C569 0.3
37 03/26 Roger29 H/WEMI request add a cap place near R518 forblue tooth Add C570 (33P_0402_50V8J~D) 0.3
38 03/28 Roger34 H/WIssue list item 7, swap SIO_PWRBTN# andICH_PCIE_WAKE# to fix WOL issue on Laguna
Swap SIO_PWRBTN# (U20 pin A15) andICH_PCIE_WAKE# (U20 pin A13) 0.3
39 35 03/28 RogerH/W Change board ID to (0010) for X02 board Pop R94, R419 and non-popped R107, R405 0.3
40 6 03/28 RogerH/WReserved clock gernerator pin53 for 14.318MHz for ICS 954206
Add a 12.1 ohms series resistor R531 to U16 pin 53 and connect toCLK_CODEC_14M. Isolation resistor R531 connect to CLKSEL0 0.3
41 6 H/W 04/01 Roger TV out B/W issue on UMA configurationPop C329 and C333 with 27P to fine tune the crystal frequency and clocksequence 0.3
42 15 H/W 04/02 Roger FAN RPM detect issue Change C209 to 1000P and de-popped 0.3
43 26 H/W 04/04 RogerSolve the pop issue and the static noiseduring post and idle in Windows Pop U30 inverter and depop R528 (0_0402_5%) 0.3
44 27 H/W 04/04 Roger Tune audio amplifier gain to 21.6dB Pop R164 (10K_0402_5%) and depop R107 (10K_0402_5%) 0.3
45 37 H/W 04/04 Roger For the +5VHDD power source, use +5VRUN Depop Q51, Q50, R507, C547 and pop R506 ( 0_0805_5%) 0.3
46 27 H/W 04/04 Roger Dell Audio team requestC535, C536 change from 0.47UF to 0.1UF and C199, C206 change from 2.2UFto 0.1F 0.3
47 38 H/W 04/07 RogerPCI clocks to ICH_PWRGD timing too lateissue. SPEC is at least 99 ms
Change C520 form 0.1UF to 0.01UF0.3
48 13 H/W 04/07 RogerIntel Design Guide recommend populate TVDAC & CRT DAC power inputs filtering
Change back population L9, L10, L11, L25, L26, L24, C24, C291, C293,C22, C298, C299, C23, C323, C310, C297, C314, C331, C322, C37, C35,C305, C306, C36, C304 on external board
0.3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Changed-List History 1/2
49 51Monday, October 18, 2004
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
49 0.4
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
6,10,22 H/W 04/28 RogerModify pop option for B1 stepping DothanCPU for ST build
Depop R305, R364, R438. Pop R329, R343, R88 for both UMA and discretemother board
50 Add smart dimmer function for VGA boardU20 pin E3 (BIA_PWM) connect to JVID pin4 isolate by R534 and U4 pinE25 isolate by R533
51 ICH_V5REF_RUN leakage issue
Roger05/06H/W18,35 0.4
52
RogerH/W 05/06
H/W 05/17 Roger R274 burn out issue6Change R274 (1 ohm) from 0402 to 0603 size, R273,R401(2.2 ohms) from0402 to 0603 size.
0.4
0.4
Reserve R535 for +5VRUN power source24
53 39 H/W 05/19 Roger Increase breath and HDD active LED lightBreath LED circuit change to like the bluetooth LED circuit, R1 & R2change from 330 ohms to 56 ohms 0.4
54 25 H/W 05/19 RogerX03 issue list item7, modify the SATAcrystal circuit Connect R190 pin1 to U11 pin23, connect pin2 to Y1 pin 2 0.4
55 25 H/W 05/19 RogerX03 issue list item8,reserve oscillatorfor istead of crystal for marvell 8040 Add a non-pop oscillator Y3 (25MHz) connect to U11 pin22, Pin23 0.4
55 24 H/W 05/19 Roger X03 issue list item8, ICH leakage issue Reserve R537 connect +5VSUS for ICH_5VREF_SUS power source 0.4
56 15 H/W 06/01 RogerOTP shutdown temperature varies. Offset 6degree C to 79 degree C Change R249 from 13.1K ohms to 147K ohms to set VSET to 0.25V 0.4
57 27 H/W 06/01 RogerWhen audio recorded, CPU fan noise will becovered from +5VRUN R143 change from +5VRUN to +5VSUS 0.4
58 25 H/W 06/07 Roger HDD can't detect issueC279, C280 change to 12 PF, Add a 25M oscillator reserve for Marvel8040 0.4
59 36 H/W 06/07 RogerEMC request pop keyboard matrix signalbypass caps. Change CN1~CN6 to single 100pF cap for cost saving 0.4
60 35 H/W 06/07 Roger Change board ID for X03 (R04) Pop R405 and de-pop R419 (BID : 0011) 0.4
61 6 H/W 06/07 RogerX03 issue list item 19, add pull downresistor for SRC/CLKREQ select Add R538 (0 ohm) for pull down U16 pin 56 0.4
62 39 H/W 06/07 RogerX03 issue list item 20, Bluetooth LED istoo bright Change R8 from 56 ohms to 1K ohms 0.4
63 27 H/W 06/08 RogerAudio codec and U5 (MAX4411) were unifiedinto the same power U5 pin10, 19 and R132 pin1 change connect from +3VRUN to +VDDA 0.4
64 27 H/W 06/08 RogerAudio amplifier power and gain setting pullup power were unified into the same power R164 pin1 and R165 change connect from +5VRUN to +5VAMPVCC 0.4
65 13 H/W 06/09 Roger UMA platform TV out water wave issue Add C598 (4.7U_0805_10V4Z) for +3VRUN_ATVBG bulk 0.4
66 29 H/W 06/09 RogerMedia board signal EMI resistors nonecessary now Remove R188,R189,R193,R194,R195,R196,R197,R208,R209,R220,R221 0.4
67 25 H/W 06/11 Roger X03 issue list item 28 Connect R204 pin1 to U11 (Marvel 8040) pin22 0.4
68 28 H/W 06/11 Roger X03 issue list item 29,30Add PJP21 between USBP4_PWR and USBP5_PWR, PJP22 between USBP7_PWR andUSBP8_PWR
69 34,35 H/W 06/11 Roger X03 issue list item 31,32Pop R116 and no-pop R114, pop R119 and no-pop R128 to change powersource from +3.3VX to +RTC_CELL
70 37 H/W 06/11 RogerSupply +1.8VRUN for Graphic board fromMother board Change Q14 from SI2456 to SI4810 for larger power margin.
0.4
0.4
0.4
71 38 H/W 06/11 RogerReserved option to use the Sullivan/Lagunarbatt Add JCOIN connect to +COINCELL 0.4
72 30 H/W 06/11 RogerAccording to the cystal vendor measurereport Change R264 from 200 to 820 ohms to reduce the drive level 0.4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Changed-List History 1/2
50 51Wednesday, November 03, 2004
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
73 0.4
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
37 H/W 06/11 Roger +5VRUN glitch when HDD shut down Populate Q50, Q51,R507,C547 and de-pop R506
74 26 H/W 06/14 Roger Disable the Line In MIC function for No Pop C510 and C512 & Pop R529 and R530 0.4
75 27 H/W 06/14 Roger X03 issue list item 21 Change C147 and C148 from 1uF (0603) to 3.3uF (0603) 0.4
76 12 H/W 06/15 Roger X03 issue list item 41Change Q33, Q7, Q31, and Q27 to BSS138 and use +2.5VRUN for gatevoltage 0.4
77 24 H/W 06/15 Roger X03 issue list item 40 Change R535 to 100 ohm per Intel spec 0.4
78 22 H/W 06/17 Roger Pop resistor for support deeper sleep Pop R121 (0_0402_5%) and R127 (56_0402_5%) 0.4
79 25 H/W 06/17 Roger Implement oscillator for Marvel 8040 De-pop Y1, R204, R190, C279, C280
80 28 H/W 07/21 Roger Move USB power jump to close bulk capPJP21 connect R14 pin2 and R22 pin2. PJP22 connect R96 pin2 and R109pin2
0.4
0.6
81 35 H/W 07/21 Roger Change board ID for V0.6 Depop R94, R405, R108 and pop R107, R419, R95 0.6
82 23,34 H/W 07/27 Roger LCD_TST for panel control by ICH6-M and SIOLCD_TST connect to ICH6-M pin AD20(GPO21) and Macallan pin B12 (LGPIO70)isolate by R539,R540 0.6
83 9 H/W 08/01 Roger Reduce CUP core caps for cost saving Depop C428, C446, CC448, C431, C119, C118 0.6
85 39 H/W 08/11 Roger Balance LED brightness Change R5 value from 330 ohms to 220 ohms 0.6
84 13 H/W 08/29 RogerChange +1.5VRUN_DPLLA, +1.5VRUN_DPLLB,+1.5VRUN_HPLL, +1.5VRUN_MPLL inductance Change L28, L33, L38, L39 to TDK 10U_MLZ2012E100PTAIN 10 UH inductance 0.6
86 6 H/W 09/03 RogerDell other project have issue at CLKSEL0signal Depop R532 and pop R259 0.6
87 36 H/W 09/23 RogerSST flash ROM part have crash issue, needto further clarify Change SST 39VF080 to MXIC MX29LV008BTC-70R 0.6
88 39 H/W 09/23 RogerChange the LED from non clear lens toclear lens 0.6
89
23 H/W 11/03 Roger Intel sighting report #67725 workround
Change D1, D2, D3 from HARVATEK to Lite-on
Pop R433 (100K_0402)
1.0
90
10 H/W 11/03 Roger Intel sighting report #68363 workround De-pop R435, R437
1.0
91
39 H/W 11/03 Roger Blue tooth LED is too bright Change R8 from (1K_0603) to (3.3K_0603)
1.0
92 19 H/W 11/03 Rogerfine tune G_PWR_SRC lag +3VRUN sequenceissue
1.0
Change C290 form 0.1UF to 1000PF
92
15 H/W 11/03 Roger Forcecon CPU fan acoustic issue Pop C538 (2200P_0402_25V7K)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o fTOBAGO-LA2151 0.6
Changed-List History 1/2
51 51Monday, October 18, 2004
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page#
1 0.1
2
Title
3
Change PU6 from SC1486 to MAX8550 and other component at P44Change DDR2 solution
42 Dell request to add components Change PC15 from 4.7u to 2.2u, add PR203(100 ohm) and PC156(2.2u)
0.1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
0.1
4
46 POWER 01/30 Demon Change charger current Change PR158 from 90.9K to 52.3K
44 POWER 01/30 Demon
Demon01/30POWER
40 POWER 02/06 Demon Dell request to change component Change PR2 from 1.5k to 2.2k 0.1
5 43 POWER 02/13 Demon Dell request to change component Change PC51 from 330U 25m ohm to 330U 9m ohm 0.1
6
7
40 POWER 03/17 Demon EMI request Delete PL3 and pop PL2, add PL21 FBM-L11-453215-900LMAT_1812~D
POWER 03/17 Demon EMI request45 Change PR97,PR124 from 0 ohm to 2.2 ohm
0.2
0.2
8 44 POWER 03/17 Demon Add PC158 1000PDouble Plus at high side gate 0.2
9 42
4411
POWER
POWER
POWER
03/25
03/25
03/25
Demon
Demon
Demon
EMI request
EMI request
EMI request
Add PL22 FBM-L11-453215-900LMAT_1812~D
Add PL23 FBM-L11-453215-900LMAT_1812~D
Add PL24 FBM-L11-453215-900LMAT_1812~D
0.2
0.2
0.2
12 43 POWER 03/29 DemonIncrease 1.5VSUS voltage spec of powersource for GMCH 1.5V Vcc power on Tobago
Change PR58 from 10K to 11K 0.2
13 40 POWER 04/05 Demon Change PQ1 from 2N7002 to BSS138 DELL EE request 0.2
14 42 POWER 05/10 Demon DELL power team request Change PR27 from 4.7ohm to 10ohm, and add PR211 10ohm
15 46 POWER 05/10 Demon DELL request Change PU8 from MAX1535AETJ to MAX1535BETJ
0.3
0.3Add PR212,PR215 0 ohm , and un-pop PQ36,PR197,PR213,PR214, and change PU6 from MAX8550 to MAX8550A 0.3
17 45 POWER 05/19 Demon DELL requestChange PQ13,PQ17 from IRF7811AV to IRF7821 and PQ15,PQ19 from SI4362to IRF7832 and un-pop PQ16,PQ20 0.3
18 44 POWER 05/31 Demon DELL request Change PC152, PC153, PC154,PC157 from 22uF to 10uF 0.3
19 48 POWER 05/31 Demon Modify layout Un-pop PQ15 and PQ17, pop PQ16 and PQ18
20 44 POWER 05/31 DemonModify schematic the same with Lagunaand change switching frequencies from450kHz to 300kHz
Un-pop PR84
10 43
44 For vender new version MAX8550ADemon05/14POWER16
0.3
0.3
21 43 POWER 06/07 Demon DELL request, for MAX1845 negative voltageissue.
Add PQ37 2N7002 and PR216 33k ohm. 0.3
22 41 POWER 06/07 Demon Modify 2.5V power sequence Change PR1 from 0 ohm to 8.2k ohm and add PC8 0.1u. 0.3
23 43 POWER 06/10 Demon Change 1.55V to 1.525V Change PR58 from 11K to 10.5K. 0.3
4424 POWER 06/10 Demon For MAX8550 Add PQ36 and PR197 100k ohm, and delete PR212 0 ohm. 0.3
25 43 POWER 06/15 Demon For power sequence Pop PR60 and un-pop PR80 at External and Internal M/B. 0.3
26 43 POWER 07/08 Demon For MAX1845 OVP issue Add PR217 11k ohm.
27 45 POWER 07/08 Demon For MAX1987 C4 Voltage Add PR218 0 ohm and delete PR103 0 ohm and un-popPR219,PR220
0.4
0.4
28 45 POWER 07/21 Demon For noise issue Add a un-pop component PC159 0.4
Recommended