Figures to Accompany
Design-for-Test for Digital IC’s and
Embedded Core Systems
Alfred L. Crouch
© 1999 Prentice Hall, All Rights Reserved
Contents
ii
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 1 Test and Design-for-Test Fundamentals
Figure 1-1 Cost of Product Figure 1-2 Concurrent Test Engineering Figure 1-3 Why Test? Figure 1-4 Definition of Testing Figure 1-5 Measurement Criteria Figure 1-6 Fault Modeling Figure 1-7 Types of Testing Figure 1-8 Manufacturing Test Load Board Figure 1-9 Using ATE Figure 1-10 Pin Timing Figure 1-11 Test Program Components
Chapter 2 Automatic Test Pattern Generation Fundamentals
Figure 2-1 The Overall Pattern Generation Process Figure 2-2 Why ATPG? Figure 2-3 The ATPG Process Figure 2-4 Combinational Stuck-At Fault Figure 2-5 The Delay Fault Figure 2-6 The Current Fault Figure 2-7 Stuck-At Fault Effective Circuit Figure 2-8 Fault Masking Figure 2-9 Fault Equivalence Example Figure 2-10 Stuck-At Fault ATPG Figure 2-11 Transition Delay Fault ATPG Figure 2-12 Path Delay Fault ATPG Figure 2-13 Current Fault ATPG Figure 2-14 Two-Time-Frame ATPG Figure 2-15 Fault Simulation example Figure 2-16 Vector Compression and Compaction Figure 2-17 Some Example Design Rules for ATPG Support Figure 2-18 ATPG Measurables
Chapter 3
Scan Architectures and Techniques
Figure 3-1 Introduction to Scan-based Testing Figure 3-2 An Example Non-Scan Circuit
Contents
iii
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-3 Scan Effective Circuit Figure 3-4 Flip-Flop versus Scan Flip-Flop Figure 3-5 Example Set-Scan Flip-Flops Figure 3-6 An Example Scan Circuit with a Scan Chain Figure 3-7 Scan Element Operations Figure 3-8 Example Scan Test Sequencing Figure 3-9 Example Scan Testing Timing Figure 3-10 Safe Scan Shifting Figure 3-11 Safe Scan Vectors Figure 3-12 Partial Scan Figure 3-13 Multiple Scan Chains Figure 3-14 The Borrowed Scan Interface Figure 3-15 Clocking and Scan Figure 3-16 Scan-Based Design Rules Figure 3-17 DC Scan Insertion Figure 3-18 Stuck-At Scan Diagnostics Figure 3-19 At-Speed Scan Goals Figure 3-20 At-Speed Scan Testing Figure 3-21 At-Speed Scan Architecture Figure 3-22 At-Speed Scan Interface Figure 3-23 Multiple Scan and Timing Domains Figure 3-24 Clock Skew and Scan Insertion Figure 3-25 Scan Insertion for At-Speed Scan Figure 3-26 Critical Paths for At-Speed Testing Figure 3-27 Logic BIST Figure 3-28 Scan Test Fundamentals Summary
Chapter 4 Memory Test Architectures and Techniques
Figure 4-1 Introduction to Memory Testing Figure 4-2 Memory Types Figure 4-3 Simple Memory Organization Figure 4-4 Memory Design Concerns Figure 4-5 Memory Integration Concerns Figure 4-6 Embedded Memory Test Methods Figure 4-7 Simple Memory Model Figure 4-8 Bit-Cell and Array Stuck-At Faults
Contents
iv
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-9 Array Bridging Faults Figure 4-10 Decode Faults Figure 4-11 Data Retention Faults Figure 4-12 Memory Bit Mapping Figure 4-13 Algorithmic Test Generation Figure 4-14 Scan Boundaries Figure 4-15 Memory Modeling Figure 4-16 Black Box Boundaries Figure 4-17 Memory Transparency Figure 4-18 The Fake Word Technique Figure 4-19 Memory Test Needs Figure 4-20 Memory BIST Requirements Figure 4-21 An Example Memory BIST Figure 4-22 MBIST Integration Issues Figure 4-23 MBIST Default Values Figure 4-24 Banked Operation Figure 4-25 LFSR-Based Memory BIST Figure 4-26 Shift-Based Memory BIST Figure 4-27 ROM BIST Figure 4-28 Memory Test Summary
Chapter 5 Embedded Core Test Fundamentals
Figure 5-1 Introduction to Embedded Core Test and Test Integration Figure 5-2 What is a CORE? Figure 5-3 Chip Designed with Core Figure 5-4 Reuse Core Deliverables Figure 5-5 Core DFT Issues Figure 5-6 Core Development DFT Considerations Figure 5-7 DFT Core Interface Considerations Figure 5-8 DFT Core Interface Concerns Figure 5-9 DFT Core Interface Considerations Figure 5-10 Registered Isolation Test Wrapper Figure 5-11 Slice Isolation Test Wrapper Figure 5-12 Slice Isolation Test Wrapper Cell Figure 5-13 Core DFT Connections through the Test Wrapper Figure 5-14 Core DFT Connections with Test Mode Gating
Contents
v
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-15 Other Core Interface Signal Concerns Figure 5-16 DFT Core Interface Frequency Considerations Figure 5-17 A Reuse Embedded Core’s DFT Features Figure 5-18 Core Test Economics Figure 5-19 Chip with Core Test Architecture Figure 5-20 Isolated Scan-Based Core-Testing Figure 5-21 Scan Testing the Non-Core Logic Figure 5-22 Scan Testing the Non-Core Logic Figure 5-23 Memory Testing the Device Figure 5-24 DFT Integration Architecture Figure 5-25 Test Program Components Figure 5-26 Selecting or Receiving a Core Figure 5-27 Embedded Core DFT Summary
Chapter 1 Test and Design-for-Test Fundamentals
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 1 Test and Design-for-Test Fundamentals
Figure 1-1 Cost of Product
SiliconCost
PackagingCost
TestingCost
InitialProduct
FinalProduct
IncreasingTime
The goal over time is to reduce the cost of manufacturingthe product by reducing the per-part recurring costs:
- reduction of silicon cost by increasing volume and yield,and by die size reduction (process shrinks or more
- reduction of packaging cost by increasing volume,shifting to lower cost packages if possible (e.g., from
- reduction in cost of test by:- reducing the vector data size- reducing the tester sequencing complexity- reducing the cost of the tester- reducing test time- simplifying the test program
ceramic to plastic), or reduction in package pin count
efficient layout)
TotalCost
Chapter 1 Test and Design-for-Test Fundamentals
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-2 Concurrent Test Engineering
Gate-Level Library Mapping
Behavioral Specification and Model
Test ControlTest Interface
BIST HDL
Hardware Description LanguageRegister Transfer Level
Timing Constraints
Test ArchitectureDevelopment
Functional ArchitectureDevelopment
Scan Insertion Gate-Level Synthesis
InsertScan Cells
Scan Signals Gate-Level NetlistStatic Timing Assessment
Physical Process Mapping
Scan Optimization FloorPlanning and
AlgorithmicScan SignalReOrdering
Macrocell FloorPlanningTiming Driven Cell Placement
Timing Driven RoutingClock Tree Synthesis
Place&Route
Scan Ports
JTAG HDL
Test Timing
Chapter 1 Test and Design-for-Test Fundamentals
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-3 Why Test?
WHY TEST?
Measurementof Defects &
Quality Level
Adds Complexityto Design
Methodology
Adds toSilicon
Area
IncomingInspectionContractual
PerceivedProduct Quality
by Customer
ReliabilityRequirementContractual
Reasons
Pro & Con Perceptions of DFT
ImpactsDesign Speed or
Performance
ImpactsDesign Power
& Package Pins
EasesDiagnosis
& Debugging
EasesGeneration of
Vectors
Provides aDeterministicQuality Metric
Reducesthe Costof Test
Chapter 1 Test and Design-for-Test Fundamentals
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-4 Definition of Testing
DEFINITION of TESTING
EXAMPLE
D Q
CLK
D Q
CLK
IN_A
IN_D
IN_B
IN_C
OUT_1
OUT_2
11
1^
1X1X1
?
?
with an unknown state
BroadsideParallelVector
A KNOWNEXPECTEDRESPONSE
A KNOWNSTIMULUS
DEVICE IN A
KNOWNSTATE
Device or Circuitunder test
1^
^X
0
1S
a
b
a
b
Chapter 1 Test and Design-for-Test Fundamentals
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Transistor and Gate Representation of Defects, Faults, and Failures
gate faultsabc
@@@
000
abc
@@@
111
Figure 1-5 Measurement Criteria
+
A
B
C
physical defectsopensshortsmetal bridgesprocess errors
transistor faultsSSS
222
DGSB
GGD
222
DSBSB
observed truth tableA B C failures0011
0110
1101
0010
Vdd
Vss
G
S
DS
D
G
source-to-drainshort
D is alwaysat a logic 1
Chapter 1 Test and Design-for-Test Fundamentals
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
stuck faultsabc
6 gate faults
@@@
000
abc
@@@
111
Figure 1-6 Fault Modeling
defectsopen/shortbridgemaskprocess
delay faultsabc
6 transitions
1-1-1-
000
abc
0-0-0-
111
transistor faultssss
222
dgsb
ggd
222
dsbsb
+
c
ab00011011
c1110
nand01111
11010
11100
00000
ab ca b
delay faultsAAB
path
2S2C2S
RRR
AAB
2S2C2S
FFF
B2CR B2CF1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
a
b
sg
d
R=Slow-to-RiseF=Slow-to-Fall
transition
Truth Tablewith fail modes
path
Chapter 1 Test and Design-for-Test Fundamentals
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlistabefrtsc
16 faults
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
Figure 1-7 Types of Testing
ADDER
3
5
8
0
a
b
s
c
Functional
Structural
3 + 5 = 8
/
/
/
/4
4
4
4
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
Chapter 1 Test and Design-for-Test Fundamentals
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-8 Manufacturing Test Load Board
ChipunderTest
The chip will be accessed by the tester at its pins only
A custom (load) board will be made for this purpose
Each pin has a limited number of bits available (e.g., 2 MB)
The test program (set of vectors and tester control) will be applied at tester speed (may be less than actual chip speed)
The primary goal of manufacturing test is structural verification
Chapter 1 Test and Design-for-Test Fundamentals
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-9 Using ATE
Chip
Loadboard
Power Supply 1Power Supply 2Power Supply 3
Clock Gen 1Clock Gen 2Clock Gen 3
2 MegMemory
Depth
192Channels
Socket
Chapter 1 Test and Design-for-Test Fundamentals
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-10 Pin Timing
1. Input Setup Time:
2. Input Hold Time:
time the signal must arriveand be stable before the clockedge to ensure capture
time the signal must remainstable after the clock edgeto ensure that capture is stable
1 2 3
3. Output Valid Time:
4. Output Hold Time:
time the signal takes to bevalid (or tristated) and stable onthe output after the clock edge
time that the signal remainsavailable after output validso that it can be used
NRZ
RZ
SBC
CLK
4DV
Tester Point of View
Chip Point of View
1
1
1
0
0
0
0
0
0
Chapter 1 Test and Design-for-Test Fundamentals
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 1-11 Test Program Components
DC Pin Parametrics
DC Logic Stuck-AtDC Logic Retention
AC Frequency Assessment
Memory Testing
AC Logic Delay
Memory Retention
AC Pin Specification
Idd and Iddq
Test Logic Verification
Specialty VectorsAnalog FunctionsTest Escapes
ScanStuck-At
ScanSequential
ScanPath Delay
ScanTransition
The Venn circles areexamples of DC fault coverages of some of thevector classificationsin the test program
Some of the faultcoverages overlap
Vector reduction canbe accomplished byremoving overlap orby combining vectorsets
DelayParametric
FunctionalTest Escapes
Chapter 2 Automatic Test Pattern Generation Fundamentals
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 2 Automatic Test Pattern Generation Fundamentals
Figure 2-1 The Overall Pattern Generation Process
Library Support
Netlist Conditioning
Observe Point Assessment
Vector Generation/Simulation
Vector Compression
Vector Writing
Chapter 2 Automatic Test Pattern Generation Fundamentals
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-2 Why ATPG?
WHY ATPG?
GreaterMeasurement
Ability
Adds Complexityto Design
Methodology
EasesDiagnosis
& Debugging
RequiresTool
Support
EasesGeneration of
Vectors
Reductionin Cycle
Time
PerceivedCompetitive
Methodology
MoreEfficientVectors
Reasons
Pro & Con Perceptions of ATPG
RequiresLibrarySupport
Provides aDeterministicQuality Metric
Reducesthe Costof Test
RequiresDesign-for-Test
Analysis
Good Bad
Chapter 2 Automatic Test Pattern Generation Fundamentals
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-3 The ATPG Process
Fault Selection
Fault Observe Point Assessment
Fault Excitation
Vector Generation
Fault Simulation
Fault Dropping
Chapter 2 Automatic Test Pattern Generation Fundamentals
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
GOOD CIRCUIT
X
stuck-at-0
1
0
0
0
0
01
force to a 1
a
b
c
d
e
Figure 2-4 Combinational Stuck-At Fault
detectedgood = faulty
1
1
0
0
FAULTY CIRCUIT
1
0
0
0
1
00
1
0
0
0
DIFFERENT
Chapter 2 Automatic Test Pattern Generation Fundamentals
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-5 The Delay Fault
A
B
C Z
D
E
F
Delay Model Element
Insufficient Transistor Doping
Capacitive or ResistiveWire Delay from Opens
Slow Gate Output
Slow Gate Input
Delay from Strong Driver
Delay from Extra Load
and Metal Defects
Resistive Bridge
Effect of Delay FaultDelay of Transition Occurrence
Changing of Edge-Rate
0
1
“Ideal” Signal
0
Added Rise Delay Added Fall Delay
Edge-Rate Layover
The Delay Fault Modelis an added delay
to net, nodes, wires, gatesand other circuit elements
Chapter 2 Automatic Test Pattern Generation Fundamentals
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-6 The Current Fault
A
B
C Z
D
E
F
Leakage Fault Model
Leakage from Metastability
Capacitive or ResistiveDelay Extends Current
Internal Gate Leakage
Leakage from Bridge
Leakage from Bridge
Flow Time
Resistive Bridge
Effect of a Current Faultis to add extra current
flow or to extend flow time
The Current Fault Modelis an added Leakage
to net, nodes, wires, gatesand other circuit elements
I(t)
t
Chapter 2 Automatic Test Pattern Generation Fundamentals
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
e
Figure 2-7 Stuck-At Fault Effective Circuit
1
e0
Xstuck-at-0force to a 1
a
b
c
d
e
Detectable
ab00011011
z1110
nand
c
d
ab00011011
z1000
nor
REMAP
evaluate fault againstthe gate’s truth table
evaluate change againstthe gate’s truth table
evaluate final result againstthe circuit’s whole truth table
REMAP
Chapter 2 Automatic Test Pattern Generation Fundamentals
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-8 Fault Masking
GOOD CIRCUIT
X
stuck-at-0
1
0
X
0
10
force to a 1a
b
c
e
not detectedgood = faulty
1
1
0
X
FAULTY CIRCUIT
1
0
X
1
10
0
1
1
X
SAME
Chapter 2 Automatic Test Pattern Generation Fundamentals
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlistabefrtsc
16 faults
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
Figure 2-9 Fault Equivalence Example
GOOD - 1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
Fault Equivalence Table
b
a
a
z
z
z
AND
INV
OR
a@0 = b@0 = z@0
a@1 = z@0 : a@0 = z@1
a@1 = b@1 = z@1
r
t
e
a’
a
b
1. Any fault that requires a logic 1 on the output of an AND-gate will also place 1’s on inputs
2. Similar analysis exists for all other gate-level elements
3. If one fault is detected, all equivalent faults are detected
4. Fault selection only needs to target one of the equivalent faults
Chapter 2 Automatic Test Pattern Generation Fundamentals
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlist
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
abefrtsc
16 faults
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
Figure 2-10 Stuck-At Fault ATPG
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
1
0
Exercise the Fault
Set Up the Detect and Propagation Path
1
1
0 00
1
11 1
X
1. Set up the path to pass the opposite of e S @ 0, which is e = 1
2. Exercise by setting e equal to1
3. Detect by observing S for wrong value during fault simulation
Chapter 2 Automatic Test Pattern Generation Fundamentals
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlist
S@Time 1
abefrtsc
16 faults
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
Figure 2-11 Transition Delay Fault
S@Time 2
1 BIT ADDER with CARRY
A
B
S=1
C
e
f
a
b
r
t
s
c
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
1
0
Exercise the Fault to Pass a 1
Set Up the Detect Path to Pass a 1
11
0 00
1
11 1
1 BIT ADDER with CARRY
A
B
S=0
C
e
f
a
b
r
t
s
c
0
1
Pre-Fail the Fault by Passing a 0
The Transition DelayFaultlist is identical to
the Stuck-At Faultlist butthe goal is to detect a
Logic Transition withina given time period
X
0
0
1
1
0
1
1. Set up the path to pass the opposite of e S @ 0, which is e = 1
2. Pre-fail by setting e equal to 0
3. Exercise by setting e equal to 1 some time period later
4. Detect by observing S for wrong value during timing simulation
Chapter 2 Automatic Test Pattern Generation Fundamentals
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlist
1 BIT ADDER with CARRY
A
B
S@Time1 -> S@Time2
C
e
f
a
b
r
t
s
c
abef
t
c
16 faults
@@@@
@
@
0000
0
0
abefrtsc
@@@@@@@@
11111111
Figure 2-12 Path Delay Fault
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
r
t
s
c
0->1
1->0
Exercise the Fault (Path)
Set Up the Off-Path
1->1
1->1
00
0->0
bx->x
r @ 0
s @ 0
XX
0->10->1
1->0
X
XX
x
16.0 pt
1. Set up the path to pass a transition on B-to-S through e, r, and s by setting the off-path values to be stable for 2 time periods
2. Exercise by first setting B equal to 1 and then to 0. This is known as a vector-pair
1. Detect by observing S for wrong value during fault simulation with respect to a time standard
Chapter 2 Automatic Test Pattern Generation Fundamentals
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-13 Current Fault
faultlist
1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
abefrtsc
16 faults
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
1
0
Exercise the Fault
1. Exercise by first setting e equal to1
2. Detect by measuring current and accept vector by quietness
Chapter 2 Automatic Test Pattern Generation Fundamentals
14
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-14 Two-Time-Frame ATPG
second-ordercone of logic
establishestransition andoff-path values
first-ordercombinational
contains pathand off-path
logic
DefinedCritical
Path
establishesthe legal
next-state
cone of logic
Q D
GateElements
1->0
1->1
0->0
1->1
ExpectValue
Transitionbit
End of Pathbit
establishfirst state
legalnext-next-state
legalnext-state
presetnext-state
1. Launch 1st Value:
2. Launch Transition:
establish path fail value at clock edge
provide pass value at next clock edge
3. Capture Transition: observe transition value at this clock edge
1 2 3
Propagation Delay Time
Register Setup Time
Slack Time
Solve This CombinationalCone of Logic As the First Step
Solve This CombinationalCone of Logic As Second Step
to Combinational Multipleafter Middle Register ValuesAre Established by First Cone Time Frame Analysis
1
0
0
1
Chapter 2 Automatic Test Pattern Generation Fundamentals 15
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
faultlist
16 faults
Figure 2-15 Fault Simulation example
GOOD - 1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
“t” S@1 - 1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
“t” S@0 - 1 BIT ADDER with CARRY
A
B
S
C
e
f
a
b
r
t
s
c
GND
+VDD
abefrtsc
@@@@@@@@
00000000
abefrtsc
@@@@@@@@
11111111
1. Create multiple copies of the netlist for each fault.
2. Apply same vectors to each copy.
3. Compare each copy to good simulation (expected response).
4. Fault is detected ifbad circuit and good circuit differ at a detect point.
5. Measurement is faults detected divided by total number of faults (8/16 = 50%).
Chapter 2 Automatic Test Pattern Generation Fundamentals 16
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-16 Vector Compression and Compaction
Pattern Set
0110111000101001101110101110001011101110101111111000101001100000001011010010110010100101010101010111101100101010110011100010100111100000101000000000001010
Fault Re-Simulationwith RedundantVector Dropping
This Usually DropsEarly Vectors ThatAre Fully Covered
by Later Vectors
and Eliminates LessEfficient Vectors
Simulation Post Processing Compression
1
0
1
0
X
X
X
X
X
X
Dynamic ATPG Compression
During ATPG a Vector Is NotSubmitted to Fault Simulation
until Multiple Faults havebeen Targeted — “X”s Mapped
This can Greatly IncreaseVector Generation Time
Xone targeted
fault
But Usually Results inthe Most Efficient Vectors
Chapter 2 Automatic Test Pattern Generation Fundamentals 17
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-17 Some Example Design Rules for ATPG
Transistor
D Q
CLK
SETD Q
CLK
CLRGeneralCombinational
Logic
Propagation Timing Distance Must Be LessThan One Test Clock Cycle
StructureEquivalent
GateStructure
Combinational Feedback Results inLatches, Oscillators, or Endless Loops
ATPG May Only Operateon Gate-level Elements
Chapter 2 Automatic Test Pattern Generation Fundamentals 18
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 2-18 ATPG Measurables
ATPGTOOL
DesignDescription
ATPGLibrary
FaultlistManagement Runscripts
DetectedFaults
Vectors
Sizing Complexity
Runtime
Features
SupportFiles
VectorCompression
VectorTranslation
algorithmsrule checks
Chapter 3
Scan Architectures and Techniques
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 3
Scan Architectures and Techniques
Figure 3-1 Introduction to Scan-based Testing
Chip under Test with Full-Scan
- >1,000,000 gates
- >5,000,000 faults
- >10,000 flip-flops
- < 500 chip pins
* > 2,000 gates/pin
- > 1,000 sequential depth
* > 2M = 21000
- >1,000,000 gates
- >5,000,000 faults
- > no effective flip-flops
- < 500 + 10,000 chip pins
* > 95.23 gates/pin
- > no sequential depth
* > 2M = 20 = 1
A deep sequential circuit
A combinational circuit
Chip under Test without Scan
Chapter 3
Scan Architectures and Techniques
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
QD
QD
QD
input1input2
input3
clk
input5
output2
output1
Combinational &
Figure 3-2 An Example Non-Scan Circuit
Sequential Logic
QN
input4
input6QD
1 2 3 4
Sequential Depth of 4
Combinational Width of 6
26+4 = 1024 Vectors
Chapter 3
Scan Architectures and Techniques
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
input1input2
input3
input5
output2
output1
Combinational-Only Logic
Figure 3-3 Scan Effective Circuit
input4
input6
TPO2TPI4
TPI3
TPI2
TPI1
TPO4TPO3
TPO1
TPI5A no-clock, combinational-only circuit with:
6 inputs plus 5 pseudo-inputs and2 outputs plus 4 pseudo-outputs
D D
D
D Q
Q
QN
Chapter 3
Scan Architectures and Techniques
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-4 Flip-Flop versus Scan Flip-Flop
Regular D Flip-Flop
D Q
CLK
QN
D Q
clk
DQ
SDI
SE
CLK
QN
D Q
clk
SDO
Scannable D Flip-Flop
SDO
Chapter 3
Scan Architectures and Techniques
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-5 Example Set-Scan Flip-Flops
Set-Scan D Flip-Flop
DQ
CLK
QN
D Q
clk
SDI
SE
SET
DQ
SE
SDI
CLK
QN
D Q
clk
SDO
Set-Scan D Flip-Flop
SET
SDO
with Set at Higher Priority
with Scan-Shift at Higher Priority
Chapter 3
Scan Architectures and Techniques
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
QD
QD
QD
input1input2
input3
clk
input5
output2
output1
Combinational and
Figure 3-6 An Example Scan Circuit with a Scan Chain
Sequential Logic
QN
input4
input6QD
SDI
SE
SE
SDI
SE
SDI
SE
SDI
SE
scanin
SDO
SDO SDO
SDO scanout
1 0 1 1
4-Bit Scan Vector
Chapter 3
Scan Architectures and Techniques
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-7 Scan Element Operations
The scan cell provides observability and controllability of the signal path by conducting the four transfer functions of a scan element.
Operate: D to Q through port a of the input multiplexer:allows normal transparent operation of the element.
Scan Sample: D to SDO through port a of the input multiplexer:gives observability of logic that fans into the scan element.
Scan Load/Shift: SDI to SDO through the b port of the multiplexer: used to serially load/shift data into the scan chain while simultaneously unloading the last sample.
Scan Data Apply: SDI to Q through the b port of the multiplexer:allows the scan element to control the value of the output, therebycontrolling the logic driven by Q.
Scannable D Flip-Flop
DQ
SDI
SE
CLK
QN
SDO
D Q
clk
a
b
Chapter 3
Scan Architectures and Techniques
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-8 Example Scan Test Sequencing
DQ
SDI
SE=1
CLK
QN
SDO
D Q
clk
Scan Apply Mode (Last Shift)
DQ
SDI
CLK
QN
SDO
D Q
clk
Functional Operation Mode
DQ
SDI
SE=1
CLK
QN
SDO
D Q
clk
Scan Shift Load/Unload Mode
DQ
SDI
SE=0
CLK
QN
SDO
D Q
clk
Scan Sample Mode
While the clock is low,apply test data to SDIand Place SE = 1
From normal operation:
At the rising edge of the clock,test data will be loaded
Apply clocks for scan length
When chain is loaded, the lastshift clock will apply scan data
While the clock is low,place SE = 0
Normal circuit response will beapplied to D
The next rising edge of the clock
Return to Load/Shift mode tounload circuit response sample
NOTE: unloading is simultaneouswith loading the next test
Repeat operations until all vectorshave been applied
NOTE: the chip’s primary inputsmust be applied during the scanapply mode (after the last shift)
will sample D
SE=0
Chapter 3
Scan Architectures and Techniques
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-9 Example Scan Testing Timing
The First Shift Out
The Scan Sample
The Last Shift In
CLK
SE
The Output Pin Strobe
Faults Exercised Interval
SHIFTDATA
SHIFTDATA
FAULTEXERCISE
SHIFTDATA
SHIFTDATA
SAMPLEDATA
Scan Enable De-assert Scan Enable Assert
Chapter 3
Scan Architectures and Techniques
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-10 Safe Scan Shifting
Driven ContentionDuring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or SynchronousSignals with Higher Priority
than Scan—or Non-Scan Elements
D Q
CLKCLR
HOLDSET
Gated Clock Nets
t_seB
D Q
CLK
D Q
CLKCLR
HOLDSET
f_seB
f_seB
Provide a Forced Mutual Exclusivity
Provide a Blocking Signal
Provide an Enable Signal
clock treedistribution
force the clock on
Chapter 3
Scan Architectures and Techniques
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
t_seBde-asserted
Figure 3-11 Safe Scan Vectors
The First Shift Out
The Scan Sample
The Last Shift In
CLK
SE
Faults Exercised Interval
t_seB
Driven Contentionduring the Capture Cycle
D Q
CLK
D Q
CLK
Q D
CLK
Q D
CLK
a tristate scan enable may bea separate signal that has
slightly different timing thanthe flip-flop SE
Chapter 3
Scan Architectures and Techniques
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-12 Partial Scan
input1input2
input3
input5
output2
output1
Combinational-Only Logic
input4
input6
TPI3
TPI2
TPI1
TPO4TPO3
TPO1
TPI5A clocked, sequential circuit with depth=1:
6 inputs plus 4 pseudo-inputs and2 outputs plus 3 pseudo-outputs
D D
D
D Q
Q
QN
Chapter 3
Scan Architectures and Techniques
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
One LongScan Chain
ManyVariable Length
Scan Chains
ManyBalanced
Scan Chains
One Channel
Each Vector is 1000 Bits LongSo 5 Vectors Are 5000 Bits of Tester Memory
10 Non-Balanced
Vector Data
An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors
Vector DataVector DataVector DataVector DataVector DataVector DataVector Data
10 BalancedChannels
100
Channels
100100100100100100100
100100100100100100100100
100100100100100100100100
100100100100100100100100
Each Vector Is 100 Bits Long—So 500 Bits of Tester Memory
Vector DataVector DataVector DataVector DataVector DataVector DataVector DataVector Data
Each Vector Is 180 Bits Long—So 900 Bits of Tester MemoryDifferences from Longest Chain (180) Are Full of X’s—Wasted Memory
No Wasted Memory Space
XXXXXXXX
XXX
XXXXXX
X
12080
10011090
18020
100
XXXXXXXX
XXX
XXXXXX
X
XXXXXXXX
XXX
XXXXXX
X
XXXXXXXX
XXX
XXXXXX
X
12080
10011090
18020
100
12080
10011090
18020
100
12080
10011090
18020
100
X’s on all Other Channelsnot actively used for parallel pin data
10001000 1000 1000Vector Data
XXXX
XXXX
XXXX
XXXX
100100
100100
Vector DataVector Data
100100
100100
100100
100100
100100
100100
Vector DataVector Data
Red Space Is Wasted Tester Memory
Figure 3-13 Multiple Scan Chains
Chapter 3
Scan Architectures and Techniques
14
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-14 The Borrowed Scan Interface
Pad
AnyBidir
Functional Normal Input
Parallel Scan
SEInput
Q
Borrowed DC Scan Input on Bidirectional Pin
CombinationalLogic D
SInput to Chip
to Logic
Input Scan Interface—May Resolve to Functional during Sample Interval
Output Data Path
Output Enable
Pad
SEOutput
Q
Borrowed DC Scan Output on Bidirectional Pin
D
S
Output Scan Interface—May Resolve to Functional during Sample Interval
Input Data Path Is a
CombinationalLogic Blocked during Scan Shift
with bus_se
ScanDataInput
Pin
Captures Directly fromthe Input Pin Duringthe Shift Operation
Captures through theCombinational Logic
during the Sample Operation
AnyBidirPins
a
b
Added Scan Output Mux with bus_se or scan_mode
CombinationalLogic
Functional Output Enable with bus_se or scan_mode added
ScanData
Output
CombinationalLogic
Don’t Careduring Scan Shift
Last Scan Shift Bitfrom Scan Chain
Normal Outputfrom Logic
SEInput
Q
D
S SE on InputBlocks Data
or scan_mode
SE
Chapter 3 Scan Architectures and Techniques 15
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-15 Clocking and Scan
Analog Digital 1 Digital 2
Raw VCOClock
VCO
Counters &Dividers
On-Chip Clock Generation Logic
• Scan Bypass Clocks
• Scan Testing an On-Chip Clock Source
Bypass Clocks
Chapter 3 Scan Architectures and Techniques 16
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-16 Scan-Based Design Rules
Driven Contentionduring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or SynchronousSignals with Higher Priority
than Scan—or Non-Scan Elements
D Q
CLKCLR
HOLDSET
Gated Clock Nets
t_seB
D Q
CLK
D Q
CLKCLR
HOLDSET
f_seB
f_seB
Provide a Forced Mutual Exclusivity
Provide a Blocking Signal
Provide a Blocking Signal
Chapter 3 Scan Architectures and Techniques 17
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-17 DC Scan Insertion
Basic Netlist Scan InsertionElement Substitution
Ports, Routing & Connection of SE
Ports, Routing & Connection of SDI-SDO
ExtrasTristate “Safe Shift” Logic
Asynchronous “Safe Shift” Logic
Gated-Clock “Safe Shift” Logic
Multiple Scan Chains
Scan-Bit Re-Ordering
All Scan Chains (Clocks) Shift
Last Shift
Only One Clock DomainConducts a Sample Clock
All Non-SamplingClock DomainsInhibit Sample
Clock Pulse
Clock Considerations
Chapter 3 Scan Architectures and Techniques 18
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-18 Stuck-At Scan Diagnostics
1
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
0
Scan Fail Data Presented atChip Interface AutomaticallyImplicates the Cone of Logic
at One Flip-Flop
Multiple Fails under theSingle Fault Assumption
Implicate GatesCommon to BothCones of Logic
Chapter 3 Scan Architectures and Techniques 19
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-19 At-Speed Scan Goals
Basic Purpose
• Frequency Assessment
• Pin Specifications
• Delay Fault Content
Cost Drivers
• No Functional Vectors
• Fewer Overall Vectors
• Deterministic Grade
Chapter 3 Scan Architectures and Techniques 20
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-20 At-Speed Scan Testing
The Transition Capture
The Transition Launch
The Last Shift In
CLK
Transition Generation Interval
The First Shift Out
Faults Exercised Interval
SE
T_SE
Bus_SE
F_SE
Separate Scan Enables for Tristate Drivers,Clock Forcing Functions, Logic Forcing
Functions, Scan Interface Forcing Functions,and the Scan Multiplexor Control
Because the Different Elements HaveDifferent Timing Requirements
Chapter 3 Scan Architectures and Techniques 21
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-21 At-Speed Scan Architecture
Pad
AnyBidirPin
Normal Input
Parallel Scan
SEInput
Q
Borrowed Scan Input with Scan Head Register
CombinationalLogic D
S
DInput
Q
Driven ContentionDuring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or Synchronous Signalswith Higher Priority than Scan
or Non-Scan Sequential Elements
D Q
CLK
CLR
HOLDSET
t_seB
D Q
CLK
D Q
CLK
CLR
HOLDSET
f_seB
Input to Chip
to Logic
At-Speed Assert and De-Assert
At-Speed Assert and De-Assert
At-Speed Scan Interface—Resolves to Functional During Sample Interval
Output Data Path Blocked during Scan Shift
Output Enable with bus_se
Chapter 3 Scan Architectures and Techniques 22
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-22 At-Speed Scan Interface
Pad
AnyBidir
Functional Normal Input
Parallel Scan
SEInput
Q
Borrowed AC Scan Input on Bidirectional Pin
CombinationalLogic D
SInput to Chip
to Logic
Input Scan Interface—Resolves to Functional during Sample Interval
Output Data Path
Output Enable
CombinationalLogic Blocked during Scan Shift
with at-speed bus_se
ScanDataInput
Pin
Captures Directly fromthe Input Pin Duringthe Shift Operation
Captures through theCombinational Logic
during the Sample Operation
DInput
Q
Head
Pad
SEOutput
Q
Borrowed AC Scan Output on Bidirectional Pin
D
S
Output Scan Interface—Resolves to Functional During Sample Interval
Input Data Path Is a
AnyBidirPin
a
b
Added Scan Output Mux with bus_se
CombinationalLogic
Functional Output Enable with bus_se Added
ScanData
Output
CombinationalLogic
Don’t Careduring Scan Shift
Last Scan Shift Bitfrom Scan Chain
Normal Outputfrom Logic
SEInput
Q
D
S SE on InputBlocks Data
DOutput
Q
Tails
Chapter 3 Scan Architectures and Techniques 23
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-23 Multiple Scan and Timing Domains
FastLogic
SlowLogic
Legal ATPGTransfer
Illegal ATPGTransfer
Only Fast-to-SlowLegal ATPG Transfer
AppliedSlow Clock
AppliedFast Clock
Last ScanShift Edge
Fast to SlowTransfers
Fast to SlowTransfers
Slow to FastTransfers
Fast ScannableSystem Registers
Slow ScannableSystem Registers
The Clock Domains and Logic Timingshould be crafted so that the very nextrising edge after the launch or last shift
is the legal capture edge
Clock AScan Enable A
Clock BScan Enable B
Chapter 3 Scan Architectures and Techniques 24
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-24 Clock Skew and Scan Insertion
D
SDI
Q
scannedflip-flop
D
SDI
Q D
SDI
Q
CombinationalLogic
CombinationalLogic
Cross Domain Clock Skew must be managed to less than the fastest
120 ps
165 ps
CombinationalLogic
150 ps
D
SDI
Q
scannedflip-flop
D
SDI
Q D
SDI
Q
CombinationalLogic
CombinationalLogic
Second Clock Domain—All Elements on Same Clock Tree
120 ps
165 ps
CombinationalLogic
150 ps
300ps+
First Clock Domain — All Elements on Same Clock Tree
CLK
SE
Cross DomainClock Skew
CLK
SE
flip-flop update time in the launching clock domain
If it is not, then the receiving flip-flop may receive new-newscan data before the capture clock arrives
To prevent this outcome, constrain the ATPG tool to onlysample one clock domain at a time during the sample interval
Chapter 3 Scan Architectures and Techniques 25
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-25 Scan Insertion for At-Speed Scan
Design Flow Chart
ModelSimulation
Synthesis
Timing
Place
Mask
Verification
Analysis
andRoute
andFab
SiliconTest
Scan ModeBus_SE
Tristate_SE
Scan Shift SEClock Force_SE
Scan DataSpecification
Determination
Logic Force_SEArchitectureDevelopment
SpecificationDevelopment
ConnectionInsertion
Bus_SE: Tristate_SE:
Scan Mode:
Force_SE:
Scan Enable (SE): Scan Shift
Force_SE: Clock Force States
Scan Interface Control
Fixed “Safe” Logic
Logic Forced States
Internal Tristates
Scan Chain BitRe- Ordering
Behavior
Gates
Mask
Silicon
Chapter 3 Scan Architectures and Techniques 26
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-26 Critical Paths for At-Speed Testing
In3
Static Timing Analysis Provides Path Description
Isolated Combinational LogicAll Fan-in to Endpoint Is
U35
U36
U37
U39In4
In2
In1
D QR1D QR2
Out1
A
B
A
A
B
A
B
B
of Identified Critical Path from the Q-Output of R1to the Device Output Pin—Out1
1>0
1>0
0>1
0>1
X
0
0
0
1
0
Accounted at this EndpointFanout to other Endpoints is Evaluated atThose Endpoints
U38A
B1
Period = 20ns : Output Strobe @ 15nsIncremental
DelayCumulative
DelayClk 2.2ns Skew Amb.R1.Q 0.0ns 0.0nsU35.AU35.ZU37.AU37.ZU38.AU38.ZOut1
0.1ns3.2ns0.2ns2.2ns0.1ns
2.1ns2.2ns5.4ns5.6ns7.8ns7.9ns
Dly=10.1 Slk=4.9ns
2.1ns
Path ElementDescription
Timing Analysis Report
Chapter 3 Scan Architectures and Techniques 27
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-27 Logic BIST
Chip with Full-Scan
LFSR - PRPG: pseudo-random pattern generation
D Q D Q D Q
CLK
LFSR - MISR: multiple input signature register
D Q
CLK
and X-Management
D Q D Q
1 1 1Seed
X3 X2 X1 X0
Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11
111011001100010101110111
Chapter 3 Scan Architectures and Techniques 28
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-28 Scan Test Fundamentals Summary
Direct Observability of Internal NodesDirect Controllability of Internal NodesEnables Combinational ATPG
Scan Testing Methodology
More Efficient VectorsHigher Potential Fault CoverageDeterministic Quality MetricEfficient Diagnostic Capability
Advantages
ConcernsSafe ShiftingSafe SamplingPower ConsumptionClock SkewDesign Rule Impact on Budgets
AC and DC Compliance
Chapter 4 Memory Test Architectures and Techniques
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 4 Memory Test Architectures and Techniques
Figure 4-1 Introduction to Memory Testing
Logic Embedded
JTAG Boundary Scan
PLL TAP
Chip-Level
Memory
Memory Access
Chapter 4 Memory Test Architectures and Techniques
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-2 Memory Types
6 Transistor SRAM Cell
Column/Bit-DataColumn/Bit-Data
Row/Word-Address
Column/Bit-Data
Row/Word-Address
1 Transistor DRAM Cell
Column/Bit-Data
Row/Word-Address
2 Transistor EEPROM Cell
Storage Select
SelectStorage
Select Select
Storage
Chapter 4 Memory Test Architectures and Techniques
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-3 Simple Memory Organization
Memory: Data Width by Address Depth
32 x 512
Data In
Address In
Read/WriteBar
Output Enable
Data Out
Data Bus: To Multiple Memory Arrays
Address Bus: To Multiple Memory Arrays
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Control Circuitry to Read, Write,and Data Output Enable
Control Signals: Individual Signals to This Memory Array
BusEnable
Chapter 4 Memory Test Architectures and Techniques
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-4 Memory Design Concerns
Chip FloorPlan
Memory 1
Memory2
Memory
3
Memory 4
- Aspect Ratio
- Access Time
- Power Dissipation
Chapter 4 Memory Test Architectures and Techniques
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-5 Memory Integration Concerns
Chip FloorPlan
Memory 1
Memory2
Memory
3
Memory 4
- Routing
- Placement & Distribution
- Overall Power Dissipation
Processor
LocalLogic
Chapter 4 Memory Test Architectures and Techniques
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-6 Embedded Memory Test Methods
EmbeddedMicroprocessor
Core
EmbeddedMemory
Array
EmbeddedMemory
Array
BIST Controller
EmbeddedMemory
Array
32
24
3
32
24
3
Functional Memory Test
Direct Access Memory Test
BIST Memory Test
Data
Control
Address
Data
Address
Control
Invoke
Reset
Hold
Done
Fail
Chapter 4 Memory Test Architectures and Techniques
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
row # —> 0
column # —>
row # —> 1
row # —> 2
0 1 2 3
data bit cell
Figure 4-7 Simple Memory Model
0 1
00
00
1
11
11
1
Chapter 4 Memory Test Architectures and Techniques
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
0 1 1
1 0 1 0
single bit stuck-at 1word stuck-at
single bit stuck-at 0
data value 1110
address A031—>
address A032—>
address A033—>
Figure 4-8 Bit-Cell and Array Stuck-At Faults
1 1 1 0
1
Data in Bit Cells
May Be Stuck-At
Logic 1 or Logic 0
Chapter 4 Memory Test Architectures and Techniques
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
horizontal (row)
word bridging
bit bridging
vertical (column)bit bridging
unidirectionalone-way short
word bridgingbidirectional
two-way short
randombit bridging
Figure 4-9 Array Bridging Faults
1
1
10 0
1 0 1 0
1 0
0 0 11
1 1 00
1
0 0 11
1 1 00
Data in Bit Cells
May Be Bridged
to Other Bit Cells
Chapter 4 Memory Test Architectures and Techniques
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
1 10 1
1 0 1 1
0 1 11
0 0 11
R
O
W
XX
X
Select Lines
Column Decode
R
o
w
D
e
c
o
d
e
Row Decode
stuck-at faults result
in always choosing
wrong address
Row Decode
bridging faults result
in always selecting
multiple addresses
Figure 4-10 Decode Faults
Column Decode
stuck-at faults result
in always choosing
wrong data bit
Column Decode
bridging faults result
in always selecting
multiple data bits
X
XX 1 1 11
11 11
Select Line
faults result in
similar array
fault effects
C
O
L
Chapter 4 Memory Test Architectures and Techniques
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Data around target
cell is written with
complement data
0 11 0
0 1 0 1
0 1 10
Figure 4-11 Data Retention Faults
01 01
Address 21 = A
Address 22 = 5
Address 24 = 5
alternating 5’s and A’s make for a natural checkerboard pattern
Address 23 = A
ComplementaryData aroundTarget Cell
Chapter 4 Memory Test Architectures and Techniques
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-12 Memory Bit Mapping
Physical Memory Organization
Physical Memory Organization
Physical Memory Organization
Logical Memory Organization
Blue: Pass
Red: Fail
ColumnData Fault
Row AddressFault
Stuck-AtBit Faults
BridgedCell Faults
Chapter 4 Memory Test Architectures and Techniques
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-13 Algorithmic Test Generation
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 1 1 0 1 0 1 0
Address 00 —>
Address 01 —>
Address 02 —>
Address 03 —>
Address 04 —>
Address 05 —>
Address 06 —>
Address 07 —>
Address 08 —>
Address 09 —>
Address 10 —>
Address 11 —>
Address 12 —>
Address 13 —>
Address 14 —>
Address 15 —>
Address 16 —>
Address 17 —>
Address 18 —>
Address 19 —>
Address 20 —>
Address 21 —>
Address 22 —>
Address 23 —>
Addr(00) to Addr(Max)Read(5)-Write(A)-Read(A)Increment Address
Addr(00) to Addr(Max)Read(A)-Write(5)-Read(5)Increment Address
Addr(Max) to Addr(00)Read(5)-Write(A)-Read(A)Decrement Address
Addr(Max) to Addr(00)Read(A)-Write(5)-Read(5)Decrement Address
Addr(Max) to Addr(00)Read(5)Decrement Address
Addr(00) to Addr(Max)Write(5)-InitializeIncrement Address
Read (A)
Increment Address
Write (5)Read (5)
------->
Memory Array with 24 Addresseswith Algorithm at Read (A) Stage
March C+ Algorithm
Chapter 4 Memory Test Architectures and Techniques
14
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan-memoryboundary
Detection ofincoming
Control ofoutgoingsignalssignals
Memory
Array
Figure 4-14 Scan Boundaries
Boundary at some levelof scanned registrationor “pipelining” away
from the memoryarray
Data
Address
Control
Data
Minimum RequirementDetection up to Memory Inputand Control of Memory Output
Concern: the Logic betweenthe Scan Test Area and theMemory Test Area Is notAdequately Covered
Non-Scanned Registration inside the Boundarybut Before the Memory Test Area Results in
a Non-Overlap Zone
Chapter 4 Memory Test Architectures and Techniques
15
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-15 Memory Modeling
Data In
Address
Data Out
Memory
Array
ATPG
Model
Control
Din
Ain
Read/Write
Dout
ScanArchitecture
The Memory Array is modeledfor the ATPG Engine so the
ATPG Tool can use the memoryto observe the inputs
and control the outputs
Chapter 4 Memory Test Architectures and Techniques
16
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan black-boxboundary
Detection ofincoming
Control ofoutgoingsignals
signals
Figure 4-16 Black Box Boundaries
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersused for detection of memory
input signals
Gate or Multiplexor is usedto Block—fix to a known
value—the Memory Output Signals
Address
Data In
Control
Scan Mode
Gated Data Out
Memory
Array
can be
removed
from
netlist for
ATPG purposes
Multiplexed Data Out
All Registersare in thescan chain
architecture
Chapter 4 Memory Test Architectures and Techniques
17
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan black-boxboundary
Detection ofincoming
Input is passedto output as theform of output
signals
Figure 4-17 Memory Transparency
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersused for detection of memory
input signals
Multiplexor is used topass the input directly
to the output
Address
Control
Memory
array
can be
removed
from
netlist for
ATPG purposes
Bypass Data OutData In
control
Chapter 4 Memory Test Architectures and Techniques
18
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-18 The Fake Word Technique
scan black-boxboundary
Detection of incomingdata signals done here
Input is passedto output with
registration
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersnot needed on data since
register emulates memory
Register and multiplexoris used to emulate memory
timing and output
Address
Control
Memory
array
can be
removed
from
netlist for
ATPG purposes
Bypass Data OutData In
In ideal sense,timing should
also be matched
Chapter 4 Memory Test Architectures and Techniques
19
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-19 Memory Test Needs
Memory: data width by address depth
32 x 512
Data In
Address
Read/WriteB
Output Enable
Data Out
Data Bus: Possibly to Multiple Memory Arrays
Address Bus: Possibly to Multiple Memory Arrays
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Control Circuitry to Read, Write,and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Test Must Access the Data, Address, and Control Signalsin order to Test This Memory
Chapter 4 Memory Test Architectures and Techniques
20
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-20 Memory BIST Requirements
Algorithm Controller
Address Generator
Data Generator
Comparator
Retention
Debug
Invoke Done
Fail
Debug_data
Invoke: Start BISTRetention: Pause BIST and Memory ClockingDebug: Enable BIST Bitmap Output
Fail: A Memory Has Failed a BIST TestDone: Operation of BIST Is CompleteDebug_data: Debug Data Output
INPUTS
OUTPUTS
Memory Array(s)
Chip Level
Address: Ability to Apply Address SequencesData: Ability to Apply Different Data SequencesAlgorithm: Ability to Apply Algorithmic Control Sequences
OPERATIONS
Comparator: Ability to Verify Memory Data
Chapter 4 Memory Test Architectures and Techniques
21
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-21 An Example Memory BIST
Din
Ain
Write_en
Retention
Release
Bitmap
Invoke done
Fail
Bitmap_out
Dout
Invoke: invoke the BIST (apply muxes and release reset)Retention: enable retention algorithm and pauseRelease: discontinue and release pauseBitmap: enable bitmap output on fail occurrence
Fail: sticky fail flag—dynamic under bitmapDone: operation of BIST is completeBitmap_out: fail data under bitmap
INPUTS
OUTPUTS
Read_en
Clk
Com
parator
MemoryArrayDI
A
WRB
Do
CEB
Algorithm Controller
Address Generator
Data Generator Hold_out
Hold_out: indication of pause
Chapter 4 Memory Test Architectures and Techniques 22
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-22 MBIST Integration Issues
Invoke: a global signal to invoke all BIST units
Reset: a global signal to hold all BIST units in reset
Bitmap: a global signal to put all BIST units in debug mode
Hold_#: individual hold signals to place memories in retentionor to select which memory is displayed during debug
done: all memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold mode will present debug data
Chip Level
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_3
Hold_4 sos1
bitmap_out4
bitmap_out3
bitmap_out2
bitmap_out1
done1 fail1
done2 fail2
done3 fail3
done4 fail4
done 1-4fail 1-4
done fail diag_out
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Chapter 4 Memory Test Architectures and Techniques 23
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-23 MBIST Default Values
Invoke: must be a logic 0 when BIST is not enabled
Reset: should be a logic 0 when BIST is not enabled
Bitmap: should be a logic 0 when BIST is not enabled
Hold_#: should be a logic 0 when BIST is not enabled
done: should not be connected to package output pin when BIST is not enabled
fail: should not be connected to package output pin when BIST is not enabled
diag_out: should not be connected to package output pin when BIST is not enabled
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_3
Hold_4so
s1
bitmap_out4
bitmap_out3
bitmap_out2
bitmap_out1
done1 fail1
done2 fail2
done3 fail3
done4 fail4
done 1-4
fail 1-4
done fail diag_out
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Chapter 4 Memory Test Architectures and Techniques 24
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-24 Banked Operation
Invoke: global signal invokes bank 1 BIST
Reset: global signal holds bank 1 BIST in reset
Bitmap: global signal that enables BIST debug
Hold_#: paired hold signals to place memories in retentionor to select which memory is displayed during debug
done: bank n memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold will present debug data
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_n
sos1
diag_out
done
fail
donefaildiag_out
Memory
Arrays
with
Independent
MBISTs
invoke1-m1-n
1-n
done1-m
fail1-m
n
n
n
Bank 2
m
Memory
Arrays
with
Independent
MBISTs
Bank 1
m
mnn
1-m
scan_out1-n
debug
hold_l1
hold_l2
hold_1m
Chapter 4 Memory Test Architectures and Techniques 25
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-25 LFSR-Based Memory BIST
LFSR - MISR
CLK
Address
Data
Control
Memory Array
LFSR - PRPG
D Q
CLK
MBIST
Functional
Functional
Functional Data In
MBIST Data In
MBIST
D Q D Q
5A0F
D QD QD Q
Functional & MBIST Data Out Data Out
AlgorithmSequencer
Chapter 4 Memory Test Architectures and Techniques 26
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-26 Shift-Based Memory BIST
10101010101010
001011001110001111000011
10
1110
1010
Address
Data
Read/Write
Memory Array
The Address sequence can be shiftedboth forward and backward to provide
all addresses
The Data sequence can be shiftedacross the data lines, and can also
provide data for a comparator
The Control sequence can beshifted across the read-write
or output enable or othercontrol signals
010010
Chapter 4 Memory Test Architectures and Techniques 27
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-27 ROM BIST
MBIST
Functional Data Out
LFSR - MISR
CLK
D QD QD Q
Address
Read Control
Data Out
Read-Only Memory Array
MBIST
Functional
MBIST
Functional
Chapter 4 Memory Test Architectures and Techniques 28
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-28 Memory Test Summary
Memory Testing Fundamentals Summary
Memory Testing Is Defect-Based
Memory Testing Is Algorithmic
Memory Testing Relies on Multiple-Clue Analysis
A Memory Test Architecture May CoExist with Scan
Modern Embedded Memory Test Is BIST-Based
BIST-Based Testing Allows Parallelism
Parallel Testing Impacts Retention Testing
Parallel Testing Impacts Power Requirements
BIST Is the Moving of the Tester into the Chip
A Memory Can Block Scan Test Goals
Different Types of Memories—Different Algorithms
A Memory Fault Model Is Wrong Data on Read
Parallel Testing Requires Chip-Level Integration
Chapter 5 Embedded Core Test Fundamentals
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 5 Embedded Core Test Fundamentals
Figure 5-1 Introduction to Embedded Core Test and Test Integration
Core 1
Embedded
JTAG Boundary Scan
PLL TAPMemory
Core 2
Core 3
TCU
EmbeddedMemory
Core 4 Core 5
GeneralLogic
Chip-Level
Memory Access
Chapter 5 Embedded Core Test Fundamentals
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-2 What is a CORE?
WHAT IS A CORE?
HDLModel with
No Test
HDLModel with
Modeled Test
RTLModel with
No Test
RTLModel with
Modeled Test
SOFT
Gate-LevelNetlist with
No Test
Gate-LevelNetlist with
Synthesized Test
Gate-LevelNetlist withInserted Test
Gate-LevelNetlist withMixed Test
FIRM
LayoutGDSII with
No Test
Layoutwith Test from
Synthesis
Layoutwith Test from
Gate-Level
Layoutwith Test
Optimization
HARD
Chapter 5 Embedded Core Test Fundamentals
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-3 Chip Designed with Core
Chip-Level
UDL Core
Wrapper
CTCU
JTAG Boundary Scan
PLL
TMode[3:0]
EmbeddedMemories
EmbeddedMemories
TAP
- A Core-Based Device May Include -
1. Core(s) with Test Wrapper + Embedded Memory Arrays2. Chip-Level User Defined Logic + Embedded Memory Arrays3. Chip-Level Test Selection and Control Logic4. Dedicated Chip-Level Test Pins5. Chip-Level Clock Generation and Clock Control Logic6. IEEE 1149.1 Controller and Boundary Scan Logic
12
3
4
5
6
Chapter 5 Embedded Core Test Fundamentals
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-4 Reuse Core Deliverables
1. The Core
2. The Specification or Data Sheet
A ReuseEmbeddable
Core
3. The Various Models
4. The Integration Guide
5. The Reuse Vectors
Business Deliverables
Chapter 5 Embedded Core Test Fundamentals
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-5 Core DFT Issues
CORE-BASED DESIGN DFT ISSUES
A KNOWNEXPECTEDRESPONSE
A KNOWNSTIMULUS
ACCESSTO THE
EMBEDDEDCORE
Chip-LevelDevice
• If the Core is HARD — DFT must exist beforedelivery — how is access provided at the chip level?
• If the Core is HARD — and delivered with pre-generatedvectors — how are vectors merged in the whole test program?
• If the Core is HARD — and part of the overall chip testenvironment — how is the core test scheduled?
• If the Core is HARD — and part of the overall chip testenvironment — what defaults are applied when not active?
• If the Core is SOFT — is the overall chip test environmentdeveloped as a Core and UDL or as a unified design?
• If the Core is HARD — what is the most economical andeffective test mix — Scan? LBIST? MBIST? Functional?
OtherChip-Level Logic
• If the Core operates at a different frequency from the pinI/O or other chip logic — how does this affect DFT and Test?
Chapter 5 Embedded Core Test Fundamentals
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-6 Core Development DFT Considerations
• DFT Drivers During Core Development
Target Market/business — Turnkey versus Customer Design
• Design For Reuse Considerations
Reference Clocks — Test and FunctionalTest Wrapper — Signal Reduction/No JTAG/No Bidi’s
• Core Test Architectures and Interfaces
Direct Access — Mux Out Core TerminalsAdd-On Test Wrapper — Virtual Test SocketInterface Share-Wrapper — Scanned Registered Core I/O
Dedicated Core Test Ports — Access Via IC Pins
A ReuseEmbeddable
Core
Target Cost-Performance Profile — Low to HighPotential Packages — Plastic versus CeramicPotential Pin Counts
At-Speed Scan Or Logic Built-in Self-test (LBIST)
Virtual Test Socket — Vector Reuse
Chapter 5 Embedded Core Test Fundamentals
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-7 DFT Core Interface Considerations
• Core DFT Interface Considerations
I/O port count less restrictive than IC pin count
Access to core test ports via IC pins (integration)
A Chip Package with44 Functional Signals
A ReUseEmbeddable
Core with60 Functional
Signals
Note — none of this is known a priori
- Dedicated test signals to place in test mode
- Number of test signals needed to test core
Impact of routing core signals to the chip edge
- Frequency requirements of test signals
Chapter 5 Embedded Core Test Fundamentals
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-8 DFT Core Interface Concerns
UDL LogicEmbedded
Core
D Q
DQ
D Q
DQ
UDLDomain
COREDomain
At the time of Core Development,the UDL logic is not availableand i’s configuration is not known
For example:- registered inputs or outputs- combinational logic- bidirectional signals or tristate busses
How are vectors generated for a HardCore before integration?
How are vectors delivered that canassess the signal timing or frequency?
How is test access planned to beprovided — through the UDL or directlyfrom the package pins?
Chapter 5 Embedded Core Test Fundamentals
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-9 DFT Core Interface Considerations
• Core DFT Interface Considerations
Wrapper as a virtual test socket (for ATPG)
A Chip Package with44 Functional Signals
Wrapper for interface signal reductionWrapper for frequency assessmentWrapper as frequency boundary
Note: bidirectional functional signals can’t
A ReuseEmbeddable
Core with60 Functional
Signals
Test Wrapper with 10 Test Signals
cross the boundary if wrapper or scan
Chapter 5 Embedded Core Test Fundamentals
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-10 Registered Isolation Test Wrapper
UDL LogicEmbeddedHard Core
“Land between the Lakes”The Isolation Test Wrapper
D Q
DQ
D Q D Q
DQ DQ
where the wrapper is the registeredcore functional I/F that is scan-inserted separately
D Q
D Q
D Q
UDL ScanDomain
CORE ScanDomain
Core-Wrapper ScanDomain
Note: Wrapper and core are on same clockand path delay is used to generate vectors
Chapter 5 Embedded Core Test Fundamentals
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-11 Slice Isolation Test Wrapper
UDL LogicEmbeddedHard Core
“Land between the Lakes”The Isolation Test Wrapper
D Q
DQ
D Q
D Q
DQ
DQ
where the wrapper is an added “slice”between the core functional I/F
and the UDL functional I/F
DQ
D Q
UDL ScanDomain
CORE ScanDomain
Wrapper ScanDomain
Wrapper and core are on different clocksand path delay is used to generate vectors
Chapter 5 Embedded Core Test Fundamentals
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-12 Slice Isolation Test Wrapper Cell
UDL LogicEmbeddedHard Core
“Land between the Lakes”The Isolation Test Wrapper
D Q
DQ
D Q
DQ
the wrapper is an added “slice”between the core functional I/F
and the UDL functional I/F
D Q
UDL ScanDomain
CORE ScanDomain
Wrapper ScanDomain
Wrapper and core are on different clocksand path delay is used to generate vectors
TR_SDI
D Q
Core_Test
TR_Mode
TR_SDO
TR_SE TR_CLK
System Clock
Chapter 5 Embedded Core Test Fundamentals
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-13 Core DFT Connections through the Test Wrapper
UDL LogicEmbeddedHard Core
“Land between the Lakes”The Isolation Test Wrapper
DQ DQ
D Q
D Q
UDL ScanDomain
CORE ScanDomain
Core-Wrapper ScanDomain
Internal Scan In
DQInternal Scan Out
D QInternal BIST In
DQInternal BIST OutDirect Test
Signals goto Package
Pins
Wrapper Scan In
All Core Test Interface Signals pass through theTest Wrapper without being acted upon
All Core I/O are part of the Wrapper Scan ChainSo Total Core Test I/F is:
Internal ScanInternal MBISTWrapper Scan
DQ
Chapter 5 Embedded Core Test Fundamentals
14
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-14 Core DFT Connections with Test Mode Gating
UDL LogicEmbeddedHard Core
“Land between the Lakes”The Isolation Test Wrapper
DQ DQ
D QUDL ScanDomain
CORE ScanDomain
Core-Wrapper ScanDomain
Test Mode Control
D QInternal BIST In
Internal Scan InDirect TestSignals Goto Package
Pins
Wrapper Scan In
All Core Test Interface Signals pass through theTest Wrapper and may be acted upon by a Test Mode
All Core I/O are part of the Wrapper Scan ChainSo Total Core Test I/F is:Gated Internal ScanGated Internal MBISTGated Wrapper Scan
DQ
Core TestController
D Q
Chapter 5 Embedded Core Test Fundamentals
15
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-15 Other Core Interface Signal Concerns
• DFT ConsiderationsCan’t Support Bidirectional Core Ports
Input and Reference Clocks
Test Wrapper CoreUDL
Wrapper Cell
A ReuseEmbeddableHard Core
with Pre-ExistingClock Trees
PLL Clock OutSignal(s)
BypassTest Clock
Mul/DivClocks
Can’t Usethe
WrapperCell
Chapter 5 Embedded Core Test Fundamentals
16
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-16 DFT Core Interface Frequency Considerations
• Core DFT Frequency Considerations
Wrapper as a multi-frequency ATPG test socket
A Chip Package witha 25 MHz Interface
Wrapper for frequency boundaryTest signals designed for low frequencyPackage interface designed for high frequency
Note: functional high/low frequency signals can
A ReuseEmbeddable
Core withFmax = 100MHz
Logic
Test Wrapper with 10 Test Signals
cross the wrapper—the test I/F is the concern
Chapter 5 Embedded Core Test Fundamentals
17
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-17 A Reuse Embedded Core’s DFT Features
• Core DFT Goals and Features
Reuse of Core Patterns Independent of Integration
Test Insulation from Customer Logic
Embedded Core I/O Timing Specifications with Wrapper
Minimize Test Logic Area Impact
Minimize Test Logic Performance Penalty
Full-Scan Single-Edge Triggered MUX DFFTristate Busses - Contention/Float PreventionNegedge Inputs and Outputs
Iddq—No Active Logic and Clock Stop Support
- Bitmap Characterization Support
A ReuseEmbeddable
Core withExisting DFT
and Test Features
A Test Wrapper
Embedded Memory Test by MBIST- Few Signals — High Coverage — Less Test Time
Structure by Stuck-At Scan
Frequency by At-Speed Scan (Path & Transition Delay)
- High Coverage — Fewer Vectors — Ease of Application
- Deterministic — Fewer Vectors — Ease of Application
DFT Scannability Logic
Internal Scan Data InInternal Scan EnableWrapper Scan Data InWrapper Scan EnableWrapper Test EnableMemBIST InvokeMemBIST RetentionMemBIST BitmapInternal Scan Data OutWrapper Scan Data OutMemBIST FailMemBIST DoneMemBIST Bitmap Out
The Core’s Test Port
Chapter 5 Embedded Core Test Fundamentals
18
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-18 Core Test Economics
• Core Economic Considerations
Core Test Program Time/Size/Complexity (Tester Cost)
Test Integration (Time-to-Market)
Core Area and Routing Impact (Silicon/Package Cost)
Core Power and Frequency Impact (Package/Pin Cost)
ChipTest
ProgramBudget(s)
Time
TesterMemory
and/or
Tota
l
Chip Parametrics
Memory Testing
Retention Testing
Chip Logic Testing
Embedded Core Testing
A ReuseEmbeddable
Core withExisting DFT
and Test Features
A Test Wrapper
Internal Scan Data InInternal Scan EnableWrapper Scan Data InWrapper Scan EnableWrapper Test EnableMemBIST InvokeMemBIST RetentionMemBIST BitmapInternal Scan Data OutWrapper Scan Data OutMemBIST FailMemBIST DoneMemBIST Bitmap Out
The Core’s Test Port
Chapter 5 Embedded Core Test Fundamentals
19
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-19 Chip with Core Test Architecture
Chip-Level
UDL Core
Wrapper
CTCU
JTAG Boundary Scan
PLL
TMode[3:0]
EmbeddedMemories
EmbeddedMemories
TAP
- A Core-Base Device May Include -
Core(s) with Test Wrapper and Embedded Memory ArraysChip-Level Non-Core Logic with Embedded Memory Arrays
Chip-Level Test Selection and Control LogicDedicated Chip-Level Test Pins
Chip-Level Clock Generation and Control LogicIEEE 1149.1 Controller and Boundary Scan Logic
Chapter 5 Embedded Core Test Fundamentals
20
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-20 Isolated Scan-Based Core-Testing
Chip-Level
UDL Core
CTCU
JTAG Boundary Scan
PLL TAP
Pre-ExistingVectors
Test Selection
Clock Bypass
Wrapper andCore Scan
Package PinConnections
Chapter 5 Embedded Core Test Fundamentals
21
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-21 Scan Testing the Non-Core Logic
Chip-Level
UDL
CTCU
JTAG Boundary Scan
PLL TAP
DevelopmentGenerated Vectors
Test Selection
Clock Bypass
Wrapper andUDL Scan
Package PinConnections
Chapter 5 Embedded Core Test Fundamentals
22
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-22 Scan Testing the Non-Core Logic
Chip-Level
UDL
CTCU
JTAG Boundary Scan
PLL TAP
DevelopmentGenerated Vectors
I/O specification testing—bus_SETristate busses - contention/float prevention
Iddq—HighZ pinPin requirements—(open drains)
Test Selection
Clock Bypass
Wrapper andUDL Scan
Package PinConnections
Chapter 5 Embedded Core Test Fundamentals 23
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-23 Memory Testing the Device
Chip-Level
UDL Core
Wrapper
CTCU
JTAG Boundary Scan
PLL
EmbeddedMemories
EmbeddedMemories
TAP
DevelopmentGenerated Vectors
Test Selection
Clock Bypass
Chapter 5 Embedded Core Test Fundamentals 24
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-24 DFT Integration Architecture
Core 1
Embedded
JTAG Boundary Scan
PLL TAPMemory
Core 2
Core 3
CTCU
EmbeddedMemory
Core 4 Core 5
GeneralLogic
Chip-Level
Memory Access
• Chip-level DFT integration considerations
2. Frequency/Data Rate of Test Vectors1. Power Rating during Test
each core/vector set must have:
3. Fault Coverage of the Test Vectors4. Required Test Architecture to Reuse Vectors5. ATPG Test Wrapper or Encrypted Sim Model6. The Vector Set’s Format7. The Vector Set Sizing
Chapter 5 Embedded Core Test Fundamentals 25
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-25 Test Program Components
Chip ParametricsChip Iddq (Merged)Core 1 Test ComponentsCore 2 Test ComponentsCore 3 Test ComponentsChip-Level MemoryChip-Level Analog
Core 1 ComponentsCore 1 IddqCore 1 ScanCore 1 Memory TestCore 1 Analog
# of Cores
TestTimein (s)
1 2 3 4
Chapter 5 Embedded Core Test Fundamentals 26
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-26 Selecting or Receiving a Core
• Driven by Fab and Integration Requirements
• Core DFT Specification Items
- Test Mix
- Style of Test
• Receiving Core DFT Specification
- Maximum Number of Integration Signals
- Maximum Vector Sizing
- Minimum Fault Coverage
- Clock Source
- Minimum-Maximum Test Frequency
Chapter 5 Embedded Core Test Fundamentals 27
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 5-27 Embedded Core DFT Summary
• Two Concerns: Reuse and Integration
• Reuse: Interface, Clocks, Test Features- number of dedicated test signal- size of test integration interface
• Core Test Driven by Cost-of-Test and TTM
- ability to test interface timing
- specifications and vectors based on clock-in- specifications and vectors based on clock-out- ability to stop clock for retention or Iddq
- no functional bidirectional ports
- number of clock domains- at-speed full scan- at-speed memory BIST- use of a scan test wrapper- self-defaulting safety logic
• Integration: Core Connections, Chip Test Modes- simple core integration- reuse of pre-existing vectors- application of test signal defaults- shared resources (pins and control logic)- shared testing (parallel scheduling)- chip level test controller