3D Test TutorialUpdate - SiliconAidsiliconaid.com/2010_SWDFT_presentation/AC - 3D_Test... · 3D Test What we think we know about 3D Test Today Alfred L. Crouch ASSET, Austin, TX Chief

3D Test What we think we know about 3D Test Today

Alfred L. Crouch ASSET, Austin, TX Chief Technologist & Director of IJTAG R&D Vice-Chair IEEE P1687 “IJTAG” Working Group

[email protected]

Fred Roozeboom

SWDFT 2010

2-10-2009

…at the International Solid-State Circuits Conference (ISSCC), Samsung described an 8-gigabit DDR3 DRAM, based on TSVs. … Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying TSVs or related techniques. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.

At ISSCCC, Samsung described a DDR3 DRAM based on 50-nm technology. Measuring 10.9- x 9-mm2, the prototype device supports or stacks 4 devices, with a single master IC and three slave chips connected using 300 TSVs. The master is a 2-Gbit x 4 DDR3 DRAM with additional multi-rank control circuits, while the slaves have 2-Gbit memory cores.

EE-Times reported by Mark LaPedus

Dr. Philip Garrou

SWDFT 2010 Bill Bottoms, SIP White Paper

TSV Manufacturing

SWDFT 2010

In addition, depending on the via diameter, SUSS equipment can perform the subsequent lithography steps needed to create the vias themselves.

•  Via holes with sidewall angle of 80°

•  Reliable coating using AltaSpray

•  Contact pad opening

•  Contacts of 10 µm in 80 µm deep vias are clearly resolved

•  Spray Coat on Gamma AltaSpray

•  Exposure on MA200compact

•  Spray Develop on Gamma

From SUSS MicroTec Website: http://www.suss.com/markets/3d_integration/

Now…the real work, put your thinking hats on

SWDFT 2010

Why are we here today?

Hint: It has something to do with test!

Introduction to 3D and 3D Test

 What do we mean by 3D, 3D Test, and…

 …what is different from testing a chip today?

  For this tutorial, 3D means Stacking Die using Through-Silicon-Vias (TSV’s)

 The business being investigated is one of two things: taking a chip that exist today and to make its footprint smaller by distributing its functions over 3-D;

 …or enabling an “open socket” business where different companies vie for their place in the stack

SWDFT 2010

Introduction to 3D and 3D Test

 What do we mean by 3D, 3D Test, and…

 …what is different from testing a chip today?

  3D Test means the whole process of testing the Known-Good-Die (KGD) before stacking; and testing after stacking; and testing after packaging; and testing at board-test or system integration

  3D Test means to test die the way we test die today, and…

 …to test the extra/differences specific to the 3D process SWDFT 2010

A Look at the 3D Problem…

  The first floor die is what is connected to the board…

 2nd, 3rd, etc. floor die are connected to the board through TSV’s that go – through the lower chips…

 2nd, 3rd, etc. floor die are connected to each other through bumps or TSV’s, interposers and bumps…

 Identical die may have hot spot issues and may require rotation and an interposer…

SWDFT 2010

A Look at the 3D Architecture…

SWDFT 2010

Inside the chip Via in nanometers

Between the chip Via in micrometers

Erik Jan Marinissen, IMEC

There are really 2-businesses here…

 The IDM 3D that involves restructuring a single planar design into a 3D design… •  Design Tools, layout tools, vias, bumps, and TSV’s under control

of a single design group •  Same, process, same voltages, same process technology, etc.

 The Multi-Chip 3D that involves treating the space above a die like a socket that several companies can vie for… •  Potentially, different process technologies, voltages, etc. •  Potentially, different design tools, DFM issues, etc. •  Most definitely, different providers (and maybe for the same die)… •  …source – second-source

SWDFT 2010

There are really 2-businesses here…

  The Multi-Chip 3D has two known drivers: •  Form-Factor – the hand-held industry (cellphone, gaming, camera)

  cost, size, features   Yield – fix the problem in the fab, too cost sensitive, too short a lifetime

•  Performance – the super-computer industry (server, etc.)   the best process for the die   the best mix of architecture and peripherals   fault-tolerance, debug-diagnosis, compiler support (lifetime, tweak-time)

SWDFT 2010

So, what’s the Test Problem?

 Known Good Die and burn-in (already being delivered for MCM) – but minimal tests, some test escapes or FITs

 Test after processing but before stacking?

 Test after stacking (per stack layer?) – die for damage estimation; interconnect between die; TSVs

 Test after packaging? Traditional ATE test?

 Board-Test requirements in these markets – SerDes Tuning; Power/Performance Tuning; Memory Repair; Parametric Effects

SWDFT 2010

So, what’s the Test Problem?

  Physical Access – A Grid? A Bandwidth? A Variable Loading?

 TSV’s are HUGE (30um down to about 2um – 1u=1000nm)

 Power/Thermal Management implies “selectable test” as opposed to “all die on at the same time”

 Test Economics implies “test-scheduling” as applied to “one at a time” and “data/control bandwidth” as opposed to “traditional slow JTAG”

 Yield, Fault-Tolerance, Complexity, Configuration implies more than just “test” but “data-collection and debug-diagnosis”

SWDFT 2010

…and the number one problem is…

 Proprietary Interest!!! Comments from potential customers…

•  “I have things that not even the ATE test guys can know about and they are in my company! You think I am going to tell the board-test or system-development guy about it.”

•  “I bought a die from ACME and they won’t tell me about their Scan Compression! This reminds me of the Hard Core business.”

•  “I have a security requirement – in order to meet it, I have to fuse off my JTAG port because I use it to access ‘inside the chip’ features. Now my customer’s board development organization is mad at me!”

•  “I have encryption-decryption logic inside of my chip for test data and control – how do I pass information to my customers/test users without giving up my codes?”

SWDFT 2010

…and the number one problem is…

 Proprietary Interest!!! Comments from potential customers…

•  “I have things that not even the ATE test guys can know about and they are in my company! You think I am going to tell the board-test or system-development guy about it.”

•  “I bought a die from ACME and they won’t tell me about their Scan Compression! This reminds me of the Hard Core business.”

•  “I have a security requirement – in order to meet it, I have to fuse off my JTAG port because I use it to access ‘inside the chip’ features. Now my customer’s board development organization is mad at me!”

•  “I have encryption-decryption logic inside of my chip for test data and control – how do I pass information to my customers/test users without giving up my codes?”

SWDFT 2010

Not going to talk about this today!!!

What Efforts are Underway in Test?

 There is a 3D Study Group looking into creating a 3D IEEE Standard?

 Right now, they are trying to determine what to standardize.

SWDFT 2010

Who’s Interested?

SWDFT 2010

First Name 1. Saman 2. Lorena 3. Patrick Y 4. Paolo 5. Sandeep 6. Vivek 7. Eric 8. Adam 9. Al 10. Shinichi 11. Ted 12. Bill 13. Jan Olaf 14. Michelangelo 15. Said 16. Michael 17. Gert 18. Hongshin 19. Rohit 20. Santosh J 21. Philippe 22. Stephane 23. Hans 24. Erik Jan 25. Teresa 26. Ken 27. Herb 28. Mike 29. Andrew 30. Daniel 31. Jochen 32. Volker 33. Eric 34. Thomas 35. Ioannis 36. Min-Jer 37. Lee

Last Name Adham Anghel Au Bernardi Bhatia Chickermane Cormack Cron Crouch Domae Eaton Eklow Gaudestad Grosso Hamdioui Higgins Jervan Jun Kapur Kulkarni Lebourg Lecomte Manhaeve Marinissen McLaurin Parker Reiter Ricchetti Richardson Rishavy Rivoir Schöber Strid Thaerigen Voyiatzis Wang Whetsel

Affiliation TSMC IMAG-TIMA IBM Politecnico di Torino Atrenta Cadence Design Systems DfT-Solutions Synopsys Asset-Intertech Panasonic Cisco Cisco Neocera Politecnico di Torino Delft University of Technology Analog Devices TTU Cisco Synopsys Synopsys ST Microelectronics ST-Ericsson Qstar Test IMEC ARM Agilent Technologies eda2asic/GSA AMD Univ. of Lancaster TEL Verigy edacentrum Cascade Microtech SussMicroTec TEI of Athens TSMC Texas Instruments

Job Title Senior Manager Design Technology

Assistant Professor Product Director Senior Architect, DFT Synthesis and Verification Man. Director and Principal Trainer and Consultant Principal Engineer Chief Technologist, Director of IJTAG R&D Panasonic resident at imec Staff Engineer Distinguished Manufacturing Engineer Global Sales and Applications Manager Post-doc researcher

Senior Test Development Engineer Senior research fellow Technical Leader

Senior R&D Engineer DfT senior engineer SoC DFT & Test Specialist CEO Principal Scientist DFT Manager and Technical Lead Senior Scientist President DFT Architect Professor Product Marketing Manager System Architect Head of EDA Cluster Research Chief Technical Officer Bus. Man. FA Products and 3D Integration Test Professor Test Development Manager Distinguished Member Technical Staff

Location Canada Grenoble, France UK Torino, Italy San Jose, California, USA Endicott, New York, USA Fareham Hampshire, UK Allentown, Pennsylvania, USA Austin, Texas, USA Leuven, Belgium San Jose, California, USA San Jose, California, USA San Francisco, California, USA Torino, Italy Delft, the Netherlands Limerick, Ireland Tallinn, Estonia San Jose, California, USA Mountain View, California, USA India Grenoble, France Grenoble, France Brugge, Belgium Leuven, Belgium Austin, Texas, USA Loveland, Colorado, USA California, USA Boxboro, Massachusetts, USA Lancaster, UK Austin, Texas, USA Boeblingen, Germany Hannover, Germany Beaverton, Oregon, USA Dresden, Germany Athens, Greece Hsinchu, Taiwan Dallas, Texas, USA

And many more over the past few weeks!

Introduction to the History and Issues

 Moore’s Law is making the test problem worse…and 3D compounds that instantly…

 History Includes MCM and PCB Test…do they help?

 What about nanometer issues – more parametric effects?

 Are there Stack-Only faults and defects?

 What about Yield? Is it feasible in a Stack?

SWDFT 2010

What are we trying to Standardize about 3D Test?

Mem Core

FLASH Core

Mem-Core

CPU Core

Glue Logic

Voltage Monitor

DSP Core

ASIC Core

Power Config

CPU Core Process Monitor

LBIST MBIST

MBIST Scan

Temp Monitor

MBIST & DMA Scan

Base Die TAP

Controller

SerDes

JTAG

  Embedded Content has grown with adherence to Moore’s Law

  Cores include embedded content that becomes doubly or triply embedded logic (IEEE 1500 was created to assist with test access and portability; P1687 for instrument access and portability and vector reuse)

  Test/Debug Logic is no longer just used at Wafer-Probe or ATE IC Test – it is used at IC characterization on a board, at board test, and at system integration

  Fault Tolerance and reliability demands embedded runtime features

  Die Stacking has added a level of complexity to accessing embedded content (how is a Core’s LBIST on the 2nd die in a stack accessed and operated?) and makes a Chip look like a Board or MCM but with hidden connections

  Some Die have 1149.1 TAPs, some do not; some die may have multiple 1149.1 TAPs – some have no 1149.1 TAPs

  In reality, Cores are not standardized yet (not everyone uses 1500); DFT/DFD/DFY is not standardized yet – multiple access mechanisms exist – Ad Hoc development of the architecture is a tall pole in design

  Standardized and Scalable Access to embedded content (Instruments) that is available at Wafer, IC, Board, and System is needed

Scan & Debug

Scan & Debug

Mem-Core

FLASH Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core

MBIST

Scan & LBIST MBIST

MBIST Process Monitor

Temp Monitor MBIST MBIST

Die #2

Analog Core

RF Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core

MBIST

Scan & LBIST BIST

RF-BIST Process Monitor


Die #3 GPIO

SWDFT 2010


  Very Specifically: 1)  The Physical Port/Pins on the Package (e.g. like the TAP on a 2D chip)

2)  The DFT Access Mechanism on each Die (e.g. like the TAP on a 2D chip or a 1500 Wrapper on a Hard Core)

3)  The Physical and Logical DFT/Test/Debug Port/Pins/Socket on each Die (e.g. such as 2 or 4 TSVs and their X-Y locations that would represent Wire-Or TAP connections)

4)  The Operation Protocol for the Access Mechanism at the Chip Pin Map and at each Die’s Vertical Connection Socket (e.g. such as the 1149.1 TAP State Machine or the 1149.7 Packet-Protocol) and possibly the Bandwidth requirement (e.g. allowing each vertical connection to be an LVDS SerDes pair)

5)  The Description Language for all things connected to the whole 3D Access Mechanism (Chip Pins, Die Socket, Cores, Instruments, etc.)

6)  The Vectors and Vector Description Language (format) for all levels of vectors used in the 3D device (e.g. Instrument Vectors, Core Vectors, Die Vectors, Chip Vectors – and formats such as SVF, STIL, or PDL)

7)  Note that some of the things standardized may be just pointing to another standard and stating “as is” or “with these modifications.”

SWDFT 2010


 There are new Integration-Test Issues 1)  Multiple KGD have an architecture similar to a Board or MCM – at

the very least, connectivity must be checked and that is currently done with 1149.1 Boundary Scan (Extest/Sample)

2)  The vertical connections may be high-speed (e.g. vertical SerDes); or the vertical connections may be analog (varialbe voltage, variable current, non-digital waveforms) and may need more than just shorts, opens, DC connectivity

3)  Temperature-Evaluation, Noise-Sensitivity, Voltage-Stability, Power-Delivery between the stacked die

4)  In the future, there may be non-electrical die in the stack (thermal heat sinks, water cooling, Faraday shields, MEMs, etc.

  We have to think about all of this…but can we standardize for all of this?

SWDFT 2010

Current 2-D Method – The PCB or MCM

SWDFT 2010

Die/Chip #2 Die/Chip #1 Die/Chip #3

TCK TMS TDI TDO

TAP TAP TAP

Use of 1149.1 for Interconnect Use of Special Test Points/Routes for IC Test Use of 1149.1 for Embedded Test Use of Natural I/O for Functional Test

What about: Scan, Scan Compression, Memory BIST, Core Test?


 There are two different types of 3D Design 1)  Different Die from Different Providers are Stacked with TSVs and they must

play together when stacked   a test architecture exists whole and complete on each KGD   the overall test architecture exists whole and complete after stacking   a complication, the location in a stack may be competitive (source, second source)   A KGD may be made of multiple cores from different providers as well

2)  A monolithic design is turned into a stack to reduce its footprint or modify its form-factor – for example, a whole quad-microprocessor is made as a stack of 4 processors; or a planar design is now distributed into 3D – the test features and test IP may now be distributed among layers

3)  Known Limitations:   TSVs are still large compared to the process node drawn lines and they require Keep-

Out Zones (e.g. 20 microns = 20,000 nm; 2 microns = 2,000 nm and .2 microns = 200 nm) so it is assumed (given history with DFT) that TSVs will be for power, ground, and functional signals (duh, critical functional signals) – not lots of dedicated test routes.

  We want to serve both types of design flows SWDFT 2010

What Problems (Needs) do we face in 3D Test?

 Access…of course – we’re going to bury stuff worse than a double-stuffed double-decker Reuben sandwich and be happy about it

 Bandwidth – 2 million scan bits on level-3 being funneled through a few TSVs (think Schlitterbahn with only one slide open on the hottest day in the summer)

 Defect/Coverage – we can’t model everything in 2D – do we think we understand what will happen in 3D

 Yield Management – roll some dice…

SWDFT 2010

Access

 It seems that every leap forward has to do with access…

…it’s where JTAG came from originally…

SWDFT 2010

Mem Core

FLASH Core

Mem-Core

CPU Core

Glue Logic

Voltage Monitor

DSP Core

ASIC Core

Power Config


LBIST MBIST

MBIST Scan

Temp Monitor

MBIST & DMA Scan

Base Die TAP

Controller

SerDes

JTAG

Scan & Debug

Scan & Debug

Mem-Core

FLASH Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core

MBIST

Scan & LBIST MBIST



Die #2

Analog Core

RF Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core

MBIST

Scan & LBIST BIST



Die #3 GPIO

Current NTF Problem: PVTF Triple-Point

Voltage

Temperature

Frequency/Process

ATE Test

Location

Board Operation Location

Must correlate fails found at Board/System operation to ATE Test to avoid parametric NTF (No Trouble Found or Fail not Repeatable)

Must give Silicon Provider fail information in context

Silicon Provider must adjust Mfg Process or must adjust test to screen closer to Board/System operation point

In a Disaggregated World: must trace Systematic Si problems back to ultimate provider – Si Library, EDA Tool, Core Provider, Chip-Stack, Die-Provider, Design Organization, Mask, Fab, Package…

Cost Limits ATE Test to minimum PVTF points

A Board Test Problem that will move into our Silicon Packages

SWDFT 2010

Stacked-Die: KGD Integration Issues  Yield-Loss multiplies (learned from MCMs and PoPs)

•  1 in 10 = 10% loss for a KGD; •  3 die stack – 1 bad die is 3 in 30 = 2 good die thrown away; •  3 bad die in each group is 30% KGD yield-loss but could be 9

bad chips assembled – 9 in 10 = 90% packaged yield-loss •  Need to debug-diagnose-analyze yield-loss to die in stack

•  What hurts is Wafer-on-Wafer…you know which die are bad…

KGD #1

KGD #2

KGD #3

KGD Yield = 70%

KGD Yield = 70%

KGD Yield = 70%

Packaged Chip Yield = 10%

33 SWDFT 2010

Bandwidth

 The 2D digital chip’s have resorted to Scan Compression to reduce data volume and test time…

SWDFT 2010 34

 The 2D digital chip’s have resorted to Scan Compression to reduce data volume and test time…

 And you know we aren’t going to settle for just digital – analog, memory, and tons and tons of scan…

 And what about the new tests for the new defects and faults…

What “Wants” would we like?

 Reuse

 Reuse

 Reuse

 Reuse

 Reuse

SWDFT 2010

The Graphic Conceptualization of Reuse

36

Tests, Test Coverage, and Test Reuse: Documentation and Portability of Instruments

Design Model

Wafer

Chip Board

CPU Core

Mem Core

Design-Ware Insertion and

Verification Test

Wafer/Bare Die Probe Test

Functional, Structural

Packaged Die Stacked Die

ATE Test Functional, Structural, Parametric

Multiple Chips Embedded Instruments

Board Routes Chip Characterization

Board Test Chip-to-Chip Verification

(e.g. SerDes Tuning)

Design-Ware Insertion and

Verification Test

Design-Ware Integration and Verification Test and Compliance

SWDFT 2010

Restate the Problem…

 We need to:

 Be able to test each bare die/KGD to a great degree

 Be able to test the die after stacking

 Be able to test the interconnect after stacking

 Be able to access certain features for board integration •  SerDes Tuning •  Power/Performance Tuning •  Memory and Memory-Repair

 Be able to conduct test scheduling; meet bandwidth restrictions; and fit within test cost budgets

 And it all needs to be portable/reusable at each level of integration

SWDFT 2010

Part 2 – The Pictures and the Proposals

 Some background on the pieces and parts of the possible solutions…

SWDFT 2010


 Proposal for test of Cores, KGD, and Stack

 Define the Scalable HW Architecture

 Define Physical Access Port

 Protocol and Vectors, and Reuse across the Life-Cycle

SWDFT 2010

Some Thoughts or Hare-Brained Ideas

 Bandwidth – Vertical G-Bit Busses

 Access – Test Features self-contained and portable

 Coverage – Defined Test Features made formal

 Hmm, sounds difficult…can it be done?

SWDFT 2010


 Proposal for Cores, KGD, and Stack: Define Physical Access Port, Scalable HW Architecture, Protocol and Vectors, and Reuse across the Life-Cycle •  Use the current IEEE Standards and define bridge between them to cover

the whole 3D area (1149.1, 1149.6, 1149.7, P1687, 1500)

•  Stipulate P1687 for Instruments/1500 for large or complex Instruments or a hybrid 1500-1687 to meet scheduling and tradeoff requirements

•  Stipulate 1500 or P1687 for Cores (depending on needs)

•  Allow 1149.1 TAPs to be used per Core, per Wrapper, or per Die

•  Use 1149.1 or 1149.7 at the Stacked Die I/O boundary depending on the number of pins required and the number of TAPs supported

•  Some want 1149.1 on the first floor – and 1687/1500 as the interface on the stacked die

SWDFT 2010

Distribution of IEEE Standard Solution Spaces

42

Chip-Level 1149.7 IF

TAP.7 TAPC.7

Explanation: 4 Standards exist to access “inside the chip” logic called Cores and Instruments

Each Standard has a purpose and a section. There are 2 issues to be concerned with:

1.  Are there overlaps that muddy the delineations?

2.  Are there gaps that would leave undocumented areas?

Described by HSDL/BSDL

Good when reduced pin interface needed; good if multiple TAPs supported

1149.1 IF

BScan TAPC

TAP.1

Alt TAPC

TAP.1

Explanation: If there is no 1149.7, then there may be a chip-level 1149.1 TAP and TAPC;

or there may be more than one TAP and TAPC;

or there may be one TAP but multiple TAPCs using Compliance Enable pins to select the active TAPC.

Described by BSDL

Multiple TAPCs

TAP.1

Required if Bscan, 1500, or P1687 supported

SWDFT 2010

1687 IF SGB

(TDR)

1687 SIB

Explanation: The TAPC should connect to a Standard IF using 1 Instruction – further actions are all ScanDRs

The Interface can be an embedded TDR or can be an optional hierarchical connection TDR

Described by HDL

1687 TDR

Instrument

Good if Power/Clock-off domains or scheduling needed

Dynamic Scan Chains

Good if Complex Core and IO needs to be supported

1500/1500.1 Interface

WIR CDR2 CDR1

Explanation: The 1500 has TDRs arranged in parallel and requires a Mux Select in addition to an 1149.1 interface

Described by CTL

Instrument

SWIR

Instrument

1687 SIB


43


TAP.7 TAPC.7



1149.1 IF

BScan TAPC

TAP.1

Alt TAPC

TAP.1

Described by BSDL

Multiple TAPCs

TAP.1


SWDFT 2010

1687 IF SGB

(TDR)

1687 SIB

Described by HDL

1687 TDR




WIR CDR2 CDR1

Described by CTL

Instrument

SWIR

Instrument

1687 SIB

1687 TDR

1687 SIB

1687 TDR

Instrument


44


TAP.7 TAPC.7



1149.1 IF

BScan TAPC

TAP.1

Alt TAPC

TAP.1

Described by BSDL

Multiple TAPCs

TAP.1


SWDFT 2010

1687 IF SGB

(TDR)

1687 SIB

Described by HDL

1687 TDR




WIR CDR2 CDR1

Described by CTL

Instrument

SWIR

Instrument

1687 SIB

1687 TDR

1687 SIB

1687 TDR

Instrument

Provides Reduced-Pin Access to TAPs

Provides State-Machine Event-Sequence to

Scan-Paths

Provides Hierarchical Locally-Configurable

Scan-Paths

Provides Core Wrappers and Parallel-Ports and

Local-Instructions

1500 Wrapper

1500 Wrapper

1500 Wrapper 1500 Wrapper

1500 Wrapper

One Access Solution: Architecture of Standards

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan 2-‐Wire JTAG

CPU Core Scan & Debug

DSP Core

LBIST Scan & Debug

1149.7 Logic

1149.1 Logic

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Reduces Chip Access Cost

Addressable Broadcast Star Access Network

1149.7 adjusts network speed to 1149.1 speed

1149.1 TAP makes 1500 Wrapped Core look like JTAG chip w/BScan

1500 Wrapper makes Core portable and

reusable

DC 1149.1 Boundary Scan Cell

AC 1149.1 Boundary Scan Cell

I/O SerDes BIST (IBIST)

1687

1687

1687

1687 1687

1149.1 Boundary Scan Register for

I/O Access and Test

1687 Allows Op\mized Access to Embedded Instruments in Core

TempMon

SWDFT 2010


2-‐JTAG

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Logic

1149.1 Logic

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

TMSC TCKC

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687 1687

1687

TempMon

Dot-7 is ideal for TSV Connection to a Star Architecture; it is Scalable

SWDFT 2010

1149.1 Review   Instructions select registers and are used for scheduling

TDI 1149.1-IR

BYP

BSR

IDCode

TDO

B Y P

All inside the box described in the 1149.1 BSDL

TDR

FSM

ShiftEn CaptureEn UpdateEn ResetN

TCK

TMS

The 1149.1 Operation Sequence Generator

0

1

0 1 Select Data

Register

1

0

Select Instruct Register

1

0

Update Data

Register

1

0

Update Instruct Register

1 0

Capture Data

Register

0 1

Capture Instruct Register

0 1

Exit 1 Data

Register 0

1 Exit 1 Instruct Register

0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register

Pause Instruct Register

Shift Data

Register

Shift Instruct Register

•  Legal Sequences: those allowed by the compliant 1149.1 TAP FSM

1.  Normal Event Order: a ScanDR [Operation = Capture-Shift-Update] [Zero-Bit-Scan = Capture-E1-Update]

2.  All State Changes on Rising-TCK & TMS

3.  Five 1’s on TMS goes to TLR from anywhere in the State Machine

4.  All “Inputs and Samples” on Rising-TCK

5.  All “Outputs and Updates” on Falling-TCK


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  The Operation Sequence starts in Test-Logic-Reset (TLR) – all Scan Paths are in their Default Form

•  A Logic-1 on TMS keeps the State-Machine in TLR…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 0 on TMS moves the State-Machine to the Run-Test-Idle (RTI) “parking” state…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 0 on TMS “parks” in RTI;

•  A Logic 1 on TMS moves the State-Machine to the Select-Data-Register state…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 1 on TMS moves toward TLR;

•  A Logic 0 on TMS moves the State-Machine to the Capture-Data-Register state…

•  …which generates the CaptureEn signal and sets the selected Scan-Path Registers to conduct a Capture (Read) upon exiting the state…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR

IData


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 1 on TMS moves toward TLR and skips the Shift State;

•  A Logic 0 on TMS moves the State-Machine to the Shift-Data-Register state…

•  …which generates the ShiftEn signal and sets the selected Scan-Path Registers to conduct a Shift operation upon exiting the state…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR

SData


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 0 on TMS moves loops in the Shift State – generally this is done for the length of the Scan-Path;

•  A Logic 1 on TMS moves the State-Machine to the Exit1-Data-Register state…

•  …which is a state needed if the Shift-State is to be skipped…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR

SData


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 1 on TMS moves toward TLR and skips the Pause and Exit2 States and puts the State-Machine in the Update-Data-Register state;

•  A Logic 0 on TMS moves the State-Machine to the Pause-Data-Register parking state…

•  …entering UpdateDR generates the UpdateEn signal and sets the selected Scan-Path Registers to conduct an Update (Write) operation while passing through the state…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR

SData


0

1

0 1 Select Data

Register

1

0


1

0

Update Data

Register

1

0


1 0

Capture Data

Register

0 1


0 1

Exit 1 Data

Register 0


0

1

Exit 2 Data

Register

1


1

0 1

0

1

0

0

1

0

1

Test Logic Reset

Run Test Idle

Pause Data

Register


Shift Data

Register


•  A Logic 1 on TMS moves toward TLR and the SeDR state;

•  A Logic 0 on TMS moves the State-Machine to the RTI parking state…

•  …which is used as a parking state to allow operations to progress without doing any accesses or activities with Scan Path Registers…

TDI

To Instrument

TCK

U

TDO

SC

RST From Instrument

ShDR

The 1500 Wrapper Review

57

Chip Signals

TCK TMS

TDI TDO

TAP Controller

WBR

WBY

WIR

CDR

Instrument

Signal Legend Green = Control Blue = Data Red = Status

Core I/O

Has no FSM Must use 1149.1’s

SelectWIR


WSO WSI

The BIG Question?

 So, why isn’t 1149.1 and 1500 good enough?

 What is it about 1687 and 1149.1 that is different?

 …and if it is different, what are the advantages?

SWDFT 2010

 P1687 is mainly for “internal access” and it is intended to solve the “portability/reuse” issue; the “scheduling” aspect; the “tradeoff” concern; and “shortcomings” in 1149.1/BSDL

 1149.7 (for this tutorial) can solve the “pin/TSV cost” concern; the “multiple TAP” per chip problem; and is aimed at the “bandwidth” issue.

1149.1 Issues   Instructions select registers and are used for scheduling

TDI 1149.1-IR

BYP

BSR

IDCode

TDO

B Y P


TDR

FSM


TCK

TMS

The Limiting Factor

1149.1 Isn’t Good Enough?

TDI 1149.1-IR

BYP

BSR

IDCode

TDO

P R V T

Instrument1


One Private Instruction for BSDL

All outside the box is not described by BSDL

One Long Daisy-Chained TDR

Instrument2 Instrument3

1149.1 Isn’t Good Enough

TDI 1149.1-IR

BYP

BSR

IDCode

TDO

P R V T

Instrument1

All inside the box described in the 1149.1 BSDL Many Private Instructions for BSDL

All outside the box is not described by BSDL

Individual TDR

Instrument2 Instrument3

Individual TDR

Individual TDR

P R V T

P R V T

  Lottery Math to do scheduling


TDI 1149.1-IR

BYP

BSR

IDCode

TDO

G W E N

All inside the box described in the 1149.1 BSDL One Public/Private Instruction for BSDL

All outside the box is described by ICL/PDL

Special 1687 TDR Known as the Level-0 Gateway

Access to Instruments


TDI 1149.1-IR

BYP

BSR

IDCode

TDO

G W E N

All inside the box described in the 1149.1 BSDL One Public/Private Instruction for BSDL

Special 1687 TDR Known as the Level-0 Gateway

fromScanOut

toScanIn

toSelect

The Segment-Insertion-Bit (SIB) The Key Element for Adding, Organizing, Managing Embedded Content

TDI

Shift-Update Cell used as a SIB

Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP

Scan Path Management Bit


TDI


Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP


Normal TDI-TDO Scan Path

Default Configuration from Reset 0


TDI


Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP


Added Network Scan Path

Can access other SIBs or Instrument Interface TDR

1

67

Segment Insertion Bit (SIB) Instrument Connectivity Language

Module Sib { Ports { Sck {Function: TCK;} Rstb {Function: Reset;} Sdi {Function: ScanIn;} Sdo {Function: ScanOut; Source: SdoMux;} Sel {Function: Select;} ShEn {Function: ShiftEn;} CapEn {Function: CaptureEn;} UpdEn {Function: UpdateEn;} ToSel {Function: ToSelect; Source: SelMux;} ToSdi {Function: ToScanIn; Source: SibReg;} FmSdo {Function: FromScanOut;} } Registers { SibReg { Scanin: Sdi; CaptureSource: SibReg; // optional ResetValue: 1’b0; } } LogicSignals { SdoMux: case SibReg { 1’b0: SibReg; 1’b1: FmSdo; } SelMux: case SibReg { 1’b0: 0; 1’b1: Sel; } } /* end LogicSignals */ } /* end Module */

ToSel Sel Sdi

ToSdi

FmSdo Sdo

CS

Sck

ShEn CapEn

UpdEn U Rstb

SelMux

SdoMux

SibReg

0

Optional for debug

Q D

D Q

Thanks to Bill Bruce for the General Purpose P&P SIB

Difference: 1687 -vs- 1149/1500 Scan Paths

68

1687 Hierarchical “Add a Scan-Chain”

Model

1500 & 1149.1 “Swap a Scan-Chain”

Model

TDI TDO

TDI TDO

WIR

WBR

WBY

CDR1

CDR2

SWDFT 2010

1687 Hardware Interfaces: 1687 Starts at GW

TDI TDO

A

B C D E

F G H

TDI TDO

Level-0 Gateway is beginning of 1687

Update-En

fromSerialOut

Shift-En

Capture-En

ResetN

TCK

Select

toSerialIn Embedded IP with

Embedded Instruments and its own

Gateway

Embedded IP with its own Embedded

Instruments, Gateway, and

doubly embedded IP

Doubly Embedded IP

with Embedded

Instruments and its own

Gateway

Level-0 Gateway for IP becomes Level-1 Gateway

when integrated

Level-0 Gateway for IP becomes Level-1 Gateway to compound IP and Level-2 Gateway when integrated into chip

Scalability and

IP Reusability

TDR Interface Port Functions

Chip Signals

TCK TMS

TDI TDO

TAP Ctrl

SiB R W

MBIST Done Fail Reset Run

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

R W


R W


R W


Each SIB in this specific architecture can open to provide access to a 4-bit MBIST Instrument

One 1149.1 Instruction to select the first 1687 register

The minimal scan chain is 4-bits for this example

Each SiB can open a scan path to other Gateways or to embedded instruments

This architecture allows flexible scheduling of up to 16 instruments and any grouping of them can be accessed simultaneously

PDL is written to the instrument and is portable with the instrument

ICL allows the portable PDL to be re-targeted to the TAP pins with software automation

Access Cost for this configuration is only 36-bits

PDL Vectors go here

Architecture example

71

Chip Signals

TCK TMS

TDI TDO

TAP Ctrl

SiB R W


SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

SiB

R W


R W


R W


This specific 1687 architecture has 4 SIBs in the Level-0 Scan Path

Each Level-0 SIB opens to 4 SIBs in the Level-1 Scan Path

Each Level-1 SIB opens to a 4-bit Memory BIST Instrument-Interface Test Data Register

This example shows 4 MBISTs being accessed concurrently (the ability for the external process controller to Read and Write to these instruments in the same ScanDR

This active configuration has a maximum Scan Path of 36-bits

If only one instrument were accessed the Scan Path would be 12-bits

Access Cost is 4-bits in the L-0 Gateway + 4-bits in the L-1, and 4-bits for each selected Instrument or 24-Bits

The 3 Portions of the P1687 Architecture

Chip Signals

TCK TMS

TDI TDO

TAP Controller

SiB

T D R

RW

M B I S T

Done Fail Reset Run

T D R

RW

M B I S T

Done Fail Reset Run

SiB

SiB

•  The Controller •  1149.1 TAP & TAP Controller •  BSDL

•  The Instrument •  IP, Design-ware, EDA Gen •  Raw Instrument ICL, PDL

•  The P1687 Scan-Path Network •  Design-ware, EDA Generated •  P1687 Network ICL

BSR

BYP

ID Code

IR

PDL Vectors go here

Not P1687

Not P1687

Yes, P1687

The Simplest Network

73

A Legal 1149.1 TDR accessed from an Instruction - The difference = ICL/PDL

PD

L Here

Chip Signals

TCK TMS

TDI TDO

TAP Controller

TDR

T y p e

H

I n s t r u m e n t

Read

Write

Signal Legend Blue = Data Red = Status

ICL Here

The 1500+ is also Legal P1687

74

Chip Signals

TCK TMS

TDI TDO

TAP Controller

NiB

WBR

WBY

WIR

CDR

Instrument


Use Network-Instruction-Bit as SelectWIR to make 1500 control signals Plug&Play to TAPC

SiB PDL Here

SelectWIR


WSO WSI

Not P&P

ICL Here

The 1500+ Network

75

Use Network-Instruction-Bit as SelectWIR to make 1500 control signals Plug&Play to TAPC

Chip Signals

TCK TMS

TDI TDO

TAP Controller

NiB

WBR

WBY

WIR

P1687 TDR

Instrument 1


SiB

SiB

P1687 TDR

Instrument 2

SiB


WSO WSI

PDL Here

PDL Here

ICL Here

The Example 1687 Access Network

76

Chip Signals

TCK TMS

TDI TDO

TAP Controller

TDR T y p e R SiB

SiB TDR

T y p e W

I n s t r u m e n t

Read

Write

SiB

T y p e

RW

M B I S T

Special way to Deliver Separated Read & Write

The Multi-TAP Problem

  Many Chips today have multiple cores and maybe multiple TAPS

 For example, ARM (DAP); LogicVision (WTAP), etc.

77

  Today, either one Chip TAP muxed to internals, or Multiple Chip Pins, or “strangeness” (we are engineers…)

TAP

TAP

TAP

TAP TAP TAP

Core

TAP TAP

TAP

TDI TDO

TCK TMS


  So, how many of these TAP Controllers come with BSDL?

 How do we identify what is behind these TAPs?

 What if some TAPs are used for Instruments, some for turning a 1500 Wrapper into a pseudo-chip?

78

TAP

TAP

TAP

TAP TAP TAP

Core

TAP TAP

TAP

TDI TDO

TCK TMS


  Could use 1149.7 to provide this type of Access

 Broadcast Star – 2 up to 5 signals

 TDMA Packets

79

TAP

TAP

TAP

TAP TAP TAP

Core

TAP TAP

TAP

TCKC TMSC


2-‐JTAG

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Logic

1149.1 Logic

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

TMSC TCKC

SWDFT 2010

1149.7 Requires some logic in front of the TAP (acts as a Router)


2-‐JTAG

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Logic

1149.1 Logic

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

TMSC TCKC

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687 1687

1687

TempMon

Dot-7 is ideal for TSV Connection to a Star Architecture; it is Scalable

SWDFT 2010

One Access Solution: Scalability

Mem Core

FLASH Core

ASIC Core

CPU Core

DSP Core

TMSC TCKC

Mem Core

FLASH Core

ASIC Core

CPU Core

DSP Core

Addressible Packets

1149.7 looks identical at the board-level as it does inside of a chip!

82

The Periscope: Test and Data Collection   There are several “depths” that boards/systems may support

•  1149.1: BSDL/Boundary Scan – Chips-Routes on a Board •  1149.7: HSDL/Packet Router – TAPs in Chips, in Cores •  1500: CTL – IP Cores in Chips •  1687: ICL/PDL – Instruments on Board, in Chips, in Cores

CPU Core

Mem Core

Core

Core

Core

Core

Core

Core

Core

Core Core

Core

Core

Core

Core

Core

I/O Core

I/O Core

83

ASIC

Chip

FPGA

On-‐Board CPU

SoC Three Die Stack

Chip

TAP

TAP

TAP

TAP TAP TAP

Chip

TAP TAP

TAP

I

I

I

I

I I

I I

I I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I I

I

I

I

I

I

I

I

I

I

I I

I

I

I

I

I

I

I

I

I

I

I

I

I I

I I

I I

The Big Picture in the Board/System World

84

ASIC

Chip

FPGA

On-‐Board CPU SoC SIP

Chip

CPU Core

Instruments

Mem Core

tdi tdo

tms tck

PCIe

1500

1500

1500 1500

1500

Mem Core

BIST

FLASH Core

BIST

ASIC Core

Test

CPU Core Test

DSP Core BIST Test

Dot7

TAP

Dot-‐7 TAP

TAP Dot-‐7

Dot-‐7

TAP

Dot-‐7

TAP

Dot-‐7

TAP

1687

1687

1687

1687 1687

Mon

Mem Core

FLASH Core

Mem-Core

CPU Core

Glue Logic

Voltage Monitor

DSP Core

ASIC Core

Power Config


LBIST MBIST

MBIST Scan

Temp Monitor MBIST & DMA Scan

Base Die TAP

Controller

Scan & Debug

Scan & Debug

Mem-Core

FLASH Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core MBIST

Scan & LBIST MBIST



Die #2

Analog Core

RF Core

Mem-Core

Mem-Core

Mem-Core

MBIST

Mem-Config ASIC

Power Config

Embedded Repair

Mem-Core MBIST

Scan & LBIST BIST



Die #3

1500

1500

1500 1500

1500

Mem Core

BIST

FLASH Core

BIST

ASIC Core

Test

CPU Core Test

DSP Core

BIST Test

Tap

1687

1687

1687

1687 1687

Mon

1687

IOBIST uses I/O Instruments

PCT

Boundary Scan is Board-Level connectivity embedded instruments

An Embedded CPU is the Smartest Instrument on the Board: PCT

IJTAG uses Embedded Instruments inside the Chip

Part 3: The IEEE 3D Study Group Proposals

 There is an official 3D Study Group sanctioned by the IEEE

 Erik Jan Marinissen of IMEC is the Chair

 We have been meeting regularly on Thursdays and have put forth the following architectures to evaluate

SWDFT 2010

Specific Different 3D Access Proposals

 The “1149.7 Multiple-TAP Access” Proposal

 The “1149.1 TAP on Base-Die Only” Proposal

 The “1149.1 Prime TAP on each Die” Proposal

 The “1149.7 to Prime TAP on each Die” Proposal

SWDFT 2010

A Note on the P1687 SIB & NIB

 The IEEE P1687 Proposed Standard has a few architectural elements that will be shown in these 3D Die-Stacking Test Proposal

 One element is the Segment-Insertion-Bit which can add and subtract scan paths in a self-contained efficient manner…

 …another element is the Network-Instruction-Bit which is a data register that can be used as an Instruction command to modify other portions of the Scan-Path Access Network •  A departure from the pure 1149.1 separation of Instruction & Data


TDI


Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP



Default Configuration from Reset


TDI


Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP



Default Configuration from Reset 0


TDI


Select

TCK

U

TDO

fromScanOut

toScanIn

SC The HIP


Added Network Scan Path

Can access other SIBs or Instrument Interface TDR

1

The Network-Instruction-Bit (NIB) The Key Element for Local Configuration of Scan Path Networks

TDI

Shift-Update Cell used as a NIB

Network Command

TCK

U

TDO

SC

Scan Path Network Command Bit

Can access other SIBs or Instrument Interface TDRs

The Network-Instruction-Bit (NIB) The Key Element for Local Configuration of Scan Path Networks

TDI

Shift-Update Cell used as a NIB

Network Command

TCK

U

TDO

SC

Scan Path Network Command Bit

Can access other SIBs or Instrument Interface TDRs

1

A Note on IEEE 1500

 The 1500 Interface is not Plug&Play compatible with 1149.1 in that it requires a SelectWIR signal that is not specified in its connection to the 1149.1 TAP Controller

 Given that P1687 is an up and coming Proposed Standard, it can be used to turn 1500 into a Plug&Play interface…

 …so the 1500 Wrappers shown in this proposal should be represented with the following architecture

The Preferred 1500 Access Architecture

TCK TMS

TDI TDO

TAP Controller

NiB

WBR

WBY

WIR

CDR

Instrument


Use P1687 Network-Instruction-Bit as SelectWIR to make 1500 control signals Plug&Play to TAPC

SiB PDL Here

SelectWIR


WSO WSI

Not P&P

ICL Here

The 1149.7 Multiple TAP Proposal

 There is an 1149.7 TAP on the Base Die which becomes a two-wire distribution network to all the TAPs one each die

 There are two-TSVs on each die to deliver these signals (three-signals and three-TSVs if a Mux is used instead of a bidirectional TDI-TDO function)

 There are 1149.1 TAPs associated with groups of logic or cores – and there is an 1149.7 Controller in front of each 1149.1 TAP

 This method places more logic on each die (multiple dot-1 and dot-7 TAPs, multiple core-wrappers), but makes each addressable item a self-contained and locally controlled unit with 1149.7 only being a data/control delivery conduit – not a controller source for configuration or instructions.

An Access Solution: “1149.7 Multiple-TAP Access”

Bottom Die Known-Good-Die

Must have Probe Pads Must have a TAP •  TAP-1 or TAP-7 •  Speed to Instrument 1149.1 Boundary Scan for I/O

Dot-7 has two TSVs to feed Stacked-Die •  TMSC •  TCKC

My Preference -  More on-chip Logic -  but Self-Contained and Scalable

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Logic

1149.1 Logic

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

TCKC TMSC

An Access Solution: “1149.7 Multiple-TAP Access” Die 2-up-to-Die N •  Known-Good-Die Test •  Stack Test

Must have a few Probe Pads (Mux or SIB) for KGD

May use 1500 WBR or 1149.1 BSR for Interconnect Test

Prefer P1687 SIB for management of Scan Path lengths and Instrument Scheduling

Dot-7 I/O on each Die has 2 TSVs to feed Stacked-Die •  TMSC •  TCKC

TCKC TMSC

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.7 Interface

1149.1 TAP & Ctrl

1149.1 TAP & Ctrl

1149.7 Interface

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1149.7 Interface

1149.1 TAP & Ctrl

1687

1687

1687

1687 1687

TempMon

1149.7 Logic

1149/1500 BSR/WBR

Issue: each grouping adds a TAP and a Wrapper (Logic)

Note: many die already have multiple TAPs and could extend easily

The 1149.1 TAP on Base-Die Only Proposal

  There is one 1149.1 TAP on the Base Die which becomes a controller for all die in the stack – it provides the control signals for all JTAG-compliant object in the entire die stack

  There are up to seven-TSVs on each die to deliver these signals control and data signals •  ShiftEn •  CaptureEn •  UpdateEn •  TCK •  TDI •  TDO (single TDO requires a Multiplexor and a Select on each die) •  ResetN (opt)

  There are 1500 Wrappers/1687 Registers associated with groups of logic or cores – and they use these 1149.1 signals to coordinate all operations

  This method places the entire brunt of signal loading and instruction delivery on the single TAP Controller on the Base-Die – even if the die and number of die to eventually be placed above the base-die are unknown at the time of design; there is also a TDO management issue if only one TDO-TSV is used

An Access Solution: “1149.1 TAP on Base-Die Only”

SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO

Dot-1 on 1st floor-only has seven TSVs to feed Stacked-Die •  ShiftEn •  CaptureEn •  UpdateEn •  TCK •  TDI •  TDO • ResetN (opt)

Issue – unknown loading on instructions/signals

Note: 3 potential TDO architectures – Mux, Daisy-Chain, SIB

S

C

U

Tck

Tdi

Tdo

R


SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO





SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO




S

C

U

Tck

Tdi

Tdo

R


SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO





SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO




SIB

SIB

SIB

SIB

SIB

S

C

U

Tck

Tdi

Tdo

R


SWDFT 2010



1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1149.1 Logic

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO




SIB

SIB

SIB

SIB

SIB

An Access Solution: “1149.1 TAP on Base-Die Only” Die 2-to-N •  Known-Good-Die •  Stack Test

Must have a few Probe Pads (Mux or SIB) for KGD Test

Use 1500 WBR for Interconnect


Dot-1 I/O on each Die has 7 TSVs to feed Stacked-Die •  S/C/U/R/TCK •  TDI/TDO

Sen Cen Uen TCK TDI TDO RstN

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

SIB

SIB

SIB

SIB

SIB

An Access Solution: “1149.1 TAP on Base-Die Only” Die 2-to-N •  Known-Good-Die •  Stack Test

Must have a few Probe Pads (Mux or SIB) for KGD Test

Use 1500 WBR for Interconnect


Dot-1 I/O on each Die has 7 TSVs to feed Stacked-Die •  S/C/U/R/TCK •  TDI/TDO

Sen Cen Uen TCK TDI TDO RstN

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

SIB

SIB

SIB

SIB

SIB

The 1149.1 Prime TAP on Each Die Proposal

  There is one 1149.1 TAP on Each Die which becomes a controller for all JTAG-Compatible functions on each die – it locally provides the control signals for all JTAG-compliant objects in each die

  There are up to five-TSVs on each die to deliver the 1149.1 TAP signals •  TMS •  TCK •  TDI •  TDO (TDO managed to one pin on each die) •  TRST* (optional)

  Each die is a complete system similar to testing an MCM or chips on a board

  This method creates an Instruction Compatibility Issue in that parallel operation of each TAP implies parallel (Identical) operation of each TAP Controller (identical data and instruction flows into each dies TDI) – unless each die’s TDI-TDO is daisy chained

An Access Solution: “1149.1 Prime TAP on each Die”

SWDFT 2010


Must have Probe Pads Must have a TAP 1149.1 Boundary Scan for I/O 1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

TMS TCK TDI TDO TRST*

Dot-1 TAP on each Die has 4/5 TSVs to feed Stacked-Die •  TMS •  TCK •  TDI •  TDO •  TRST*

SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C


SWDFT 2010


Must have Probe Pads Must have a TAP 1149.1 Boundary Scan for I/O 1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon



SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C



Die 2-to-N •  Known-Good-Die •  Stack Test




1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

Dot-1 I/O on each Die has 4/5 TSVs to feed Stacked-Die •  TMS, TCK, TDI, TDO •  TRST*

1149.1 BSR or 1500 WBR

SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

Issues: 1149.1 TAPC Instruction Overlap •  TAPs operate in parallel •  Must have CE TSV per Die



Die 2-to-N •  Known-Good-Die •  Stack Test




1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon


1149.1 BSR or 1500 WBR

SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

Issues: 1149.1 TAPC Instruction Overlap •  TAPs operate in parallel •  Must have CE TSV per Die

The 1149.7 to Prime TAP on Each Die Proposal

 There is one 1149.1 TAP on Each Die which becomes a controller for all JTAG-Compatible functions on each die – it locally provides the control signals for all JTAG-compliant objects in each die

 There are two-TSVs on each die to deliver the 1149.7 TAP signals •  TMSC •  TCKC

 The two-TSVs feed the one Prime TAP on each Die

 Each die is a complete system similar to testing an MCM or chips on a board

 This method solves the Instruction Compatibility Issue the previous method in that each TAP only processes the packets targeted to its 1149.7 address

An Access Solution: “1149.7 to Prime TAP per Die”

SWDFT 2010

Bottom Die Known-Good-Die Test

Must have Probe Pads Must have a TAP 1149.1 Boundary Scan for I/O

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

TMSC

TCKC


SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

1 1 4 9 .7

T A P C


SWDFT 2010

Bottom Die Known-Good-Die Test

Must have Probe Pads Must have a TAP 1149.1 Boundary Scan for I/O

1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Core

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon

TMSC

TCKC


SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

1 1 4 9 .7

T A P C


TMSC

TCKC

Die 2-up-to-Die N •  Known-Good-Die Test •  Stack Test




1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon


1149.1 BSR or 1500 WBR

SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

1 1 4 9 .7

T A P C

My 2nd Preference

An Access Solution: “1149.7 to Prime TAP per Die” Die 2-up-to-Die N •  Known-Good-Die Test •  Stack Test




1500 Wrapper

1500 Wrapper


1500 Wrapper

Mem Core

MBIST

FLASH Core

MBIST

ASIC Logic

Scan


DSP Core

LBIST Scan & Debug

1687

1687

1687

1687 1687

TempMon


1149.1 BSR or 1500 WBR

SIB

SIB

SIB

SIB

SIB

1 1 4 9 .1

T A P C

1 1 4 9 .7

T A P C

TMSC

TCKC

My 2nd Preference

Summary: What to Standardize about 3D Test?

  One of the key items to Standardize is the Physical form of the Scalable Access Mechanism, and the Protocol-Vectors to be applied

1)  Instruments: Inside of a die or a core – will have (hopefully) a P1687 HW Architecture – an 1149.1 type protocol that includes a description (ICL) and “instrument vectors” (PDL)

2)  Cores or complex logic blocks: will have a 1500 Wrapper Architecture – an 1149.1 type protocol for most cases. Note, Cores may include a TAP that uses the 1500 WIR and WBR as if it were an 1149.1 IR and BSR – the Core may be described in ICL, CTL, and BSDL (if a TAP) is supported; the vectors may be STIL or PDL

3)  KGD: must have test-pads and TSV connections (with local Mux-Control to Select). May have multiple cores and Raw Logic and so may support one or more TAPs – one of which should be used to access Boundary Scan (1149.1 features) and/or 1500 and/or 1687 at the Die Level (BSDL, CTL, ICL, PDL, STIL, SVF)

4)  Stacked-Die: package should have a solution that seamlessly merges and incorporates these existing IEEE Standards and may need to include a “physical stipulation” of where the TSV’s (and how many) that provide the Test/Debug Access to other die should be – the per Die access Interface should result in a robust architecture automatically when die are stacked. The solution adds TSV interconnect testing to the mix.

5)  End-Use: the solution should merge with board test solutions that will be available (1149.1, 1149.7) to facilitate items that “must be” dealt with at the board/system level (SerDes Tuning, Power-Performance Tuning, Memory Test and Memory Repair).

SWDFT 2010

Summary: What to Standardize about 3D Test?

 The IEEE Scope with most-likely be…

1)  Access Port/Protocol for All Die in a Stack

2)  Interconnect Test for All Die in a Stack (1149.1 BSR, 1500 WBR, Mix)

3)  Mandate KGD Pads and Stacked TSVs

4)  Physical Location of Test TSVs

5)  Description Language of all elements on each die and the overall stack (TAPs, Wrappers, Scan Paths, Instructions, Network-Instructions)

6)  Portable Vectors for elements on each die

7)  Maybe Considered: Required Features (e.g. MBIST, TempMon); Security

8)  Not Considered: Data Collection Format, Wafer Maps, Die Order, etc. (things that may be covered by Semi or JEDEC)

SWDFT 2010

The End…for now

 Questions…[email protected]

 Dot-7: Adam Ley…[email protected]

 P1687: Ken Posse (Avago – Chair) Al Crouch (ASSET – Vice-Chair) Jeff Rearick (AMD – Editor) J-F Cote (Mentor/LV – ICL)

SWDFT 2010

Documents

3D Test TutorialUpdate - SiliconAidsiliconaid.com/2010_SWDFT_presentation/AC - 3D_Test... · 3D Test What we think we know about 3D Test Today Alfred L. Crouch ASSET, Austin, TX Chief