Design Once withDesign Compiler® FPGAThe Best Solution for ASIC Prototyping
Synopsys Inc.
© 2002 Synopsys, Inc. (2) CONFIDENTIAL
Agenda
• Prototyping Challenges• Design Compiler® FPGA Overview• Flexibility in Design Using DC FPGA and
Altera Devices
© 2002 Synopsys, Inc. (3) CONFIDENTIAL
41% of our ASIC customers are prototyping their ASIC designs in FPGA
Synopsys 2004Implementation Seminar Survey
8%5%
41% 52%Not Using FPGA ASIC Prototyping
Pre-ProductionFull Production
Customer’s use of FPGA’s – Multiple Responses Allowed
© 2002 Synopsys, Inc. (4) CONFIDENTIAL
Compelling Needs are Fueling Prototyping Market
FPGA SynthesisFPGA SynthesisFPGA Synthesis
ASICDesign Data
ASICDesign Data
FPGA Prototyping
Platform
FPGA Prototyping
Platform
Earlier integration
Fasterverification
RTL
Avoid costly ASIC re-spins
Earlier software development
© 2002 Synopsys, Inc. (5) CONFIDENTIAL
ASIC Prototyping Poses Complexity Challenges
• FPGAs are approaching ASIC-like complexity
Require ASIC-strength solution
• Timing Quality of Results is critical
Many prototypes (such as, wireless) need to run at top speedReal World Interfaces do not slow down for prototypes
Cisco Wireless Card
ASI
C G
ates
ASI
C G
ates
1K
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
10K
100K
1M
10M
Largest FPGA
Available
Median ASIC Size
© 2002 Synopsys, Inc. (6) CONFIDENTIAL
Two Flows = Two Implementations
TraditionalTraditionalPrototyping FlowPrototypi
Design CompilerDesign Compiler®®
ASIC FlowASIC Flowng Flow
RTLRTL
Clock GatingClock Gating
ConstraintsConstraintsand Scriptsand Scripts
DesignWareDesignWare®® //ASIC IPASIC IP
FormalityFormality®®
RTL
Constraintsand Scripts
Manual Clock Gating
FPGA IP
Build to Verify
• Different source, tools, IP and flows
TimeTime--consuming consuming manual processmanual process
In Lab Debug
Rewrite
Manual PostProcessing
RTL Modifications
RTL Modification
• Time consuming, error prone, manual modifications
Are they Are they functionally functionally equivalent?equivalent?
• Is design integrity guaranteed?
© 2002 Synopsys, Inc. (7) CONFIDENTIAL
Agenda
• Prototyping Challenges• Design Compiler® FPGA Overview• Flexibility in Design Using DC FPGA and
Altera Devices
© 2002 Synopsys, Inc. (8) CONFIDENTIAL
Design Compiler FPGA
EvolutionaryEvolutionary
Adaptive Adaptive OptimizationOptimization™™
TechnologyTechnology++RevolutionaryRevolutionary
Design Design CompilerCompiler®
FPGA OptimizedFPGA Optimized
•• Industry standard ASICIndustry standard ASIC--strength solutionstrength solution•• Best timingBest timing
•• Fastest path to prototypeFastest path to prototype
© 2002 Synopsys, Inc. (9) CONFIDENTIAL
Industry Standard ASIC-Strength Solution Built on Design Compiler® Technology
• ASIC ReliabilityProven through over 125,000 ASIC tapeouts
• AdvancedAlgorithms that deal with the most challenging designs
• Controllability Ability to customize the synthesis process to meet your design goals
• Formal verification supportASIC strength platforms
© 2002 Synopsys, Inc. (10) CONFIDENTIAL
Drawback of Traditional “Inflexible”Synthesis Process
0
20
40
60
80
100RuntimeRuntime
Freq
uenc
y (M
Hz)
Freq
uenc
y (M
Hz)
TraditionalTraditionalSynthesisSynthesis
ProcessProcess““InflexibleInflexible””
aa bb ccdd
ee ffgg
hh
aa bb cc dd ee ff gg hh
© 2002 Synopsys, Inc. (11) CONFIDENTIAL
Adaptive Optimization™™ Technology Delivers the Best Timing
0
20
40
60
80
100RuntimeRuntime
Freq
uenc
y (
Freq
uenc
y ( M
hzM
hz))
TraditionalTraditionalSynthesisSynthesis
ProcessProcess““InflexibleInflexible””
aa bb ccdd
ee ffgg
hh
Select best synthesis algorithms
Select best Select best synthesis synthesis algorithmsalgorithmsaa bb cc dd ee ff gg hh
© 2002 Synopsys, Inc. (12) CONFIDENTIAL
Adaptive Optimization™™ Technology Delivers the Best Timing
RuntimeRuntime
Freq
uenc
y (M
Hz)
Freq
uenc
y (M
Hz)
TraditionalTraditionalSynthesisSynthesis
ProcessProcess““InflexibleInflexible””
aa bb cc ddee ff
gg
hh
Select best synthesis algorithms
DD’’Dynamically tune
algorithmsDynamically tune Dynamically tune
algorithmsalgorithmsGG’’ HH’’
aa bb cc dd ee ff gg hh
GG’’HH’’
DD’’
0
20
40
60
80
100
© 2002 Synopsys, Inc. (13) CONFIDENTIAL
Adaptive Optimization Technology Delivers the Best Timing
0
20
40
60
80
100RuntimeRuntime
Freq
uenc
y (M
Hz)
Freq
uenc
y (M
Hz)
aa bb cc dd ee ff gg hhTraditionalTraditionalSynthesisSynthesis
ProcessProcess““InflexibleInflexible””
aa bb ccdd
ee ffgg
hh
Select best synthesis algorithms
Dynamically tune Dynamically tune algorithmsalgorithms
Re-order algorithmsReRe--order order
algorithmsalgorithmsDD’’GG’’ HH’’
GG’’
HH’’
DD’’
TraditionalTraditional AOTAOT
Freq
uenc
yFr
eque
ncy ~15%
Better
AdaptiveAdaptiveOptimizationOptimization™™
TechnologyTechnology
© 2002 Synopsys, Inc. (14) CONFIDENTIAL
Design Once With Design Compiler® FPGA
In Lab Debug
RTL Modification
Rewrite
Manual PostProcessing
RTL Modifications
TraditionalPrototyping Flow
TraditionalPrototyping Flow
Likely ErrorsLikely Errors
ASIC FlowDesign Compiler
ASIC FlowDesign Compiler
RTLRTL
Clock GatingClock Gating
Constraintsand ScriptsConstraintsand Scripts
DesignWare® /ASIC IP
DesignWare® /ASIC IP
Formality®Formality®
RTL
Constraintsand Scripts
Manual Clock Gating
FPGA IP
Build to Verify
Design Compiler®
FPGADesign Compiler®
FPGA
ASIC-StrengthPrototyping Flow
ASIC-StrengthPrototyping Flow
RTLRTL
Constraints and ScriptsConstraints and Scripts
Clock Gating TransformationClock Gating
Transformation
DesignWare® /ASIC IP
DesignWare® /ASIC IP
Formality®Formality®
Design Integrity Ensured
Design Integrity Ensured
AutomaticAutomatic
© 2002 Synopsys, Inc. (15) CONFIDENTIAL
ASIC-Strength Flow at Alereon
“The [DC FPGA] methodology and flow wereexactly the same as Design Compilerso we were able to use the same scripts,
constraints and RTL from the ASIC design.”
- Dave Ohmann, IC Design Engineer
© 2002 Synopsys, Inc. (16) CONFIDENTIAL
Best Timing at AMD
“…A significant speed increase over what we were able to achieve with other FPGA synthesis tools.“
- Dirk Haentzschel, Sr. Design Engineer
© 2002 Synopsys, Inc. (17) CONFIDENTIAL
Fastest Path to Prototype at Matrix Semiconductor
“Design Compiler FPGA was the only FPGA synthesis solution that had an integrated ASIC/FPGA flow, providing the easiest path to prototype our technology.“
-James Tringali, ASIC Design Manager
© 2002 Synopsys, Inc. (18) CONFIDENTIAL
Agenda
• Prototyping Challenges• Design Compiler® FPGA Overview• Flexibility in Design Using DC FPGA and
Altera Devices
© 2002 Synopsys, Inc. (19) CONFIDENTIAL
Design Once Implementation FlowRTL, Constraints
Design CompilerDesign Compiler®
FPGAFPGADesign Design
CompilerCompilerSynthesis
PrototypingPlatform
ProductionAltera FPGA Altera HardCopy ASIC
Time TimeTime
© 2002 Synopsys, Inc. (20) CONFIDENTIAL
ASIC Strength Flow for Flexibility
Gate-Level Simulation
Fitter
Programming
Power Estimation
Timing Analysis
Post-P&R Verification
In-SystemDebug
Formal Verification
Synthesis
Static TimingAnalysis
Synthesis
RTL,Constraints
Design Compiler®
FPGA
Quartus IIPrimeTime®
VCS® Formality®
© 2002 Synopsys, Inc. (21) CONFIDENTIAL
Design Compiler® FPGASupported Devices and Platforms
HardCopyTM
StratixTM II (Available 2004.12)
CycloneTM II (Available 2005.03)
StratixTM
StratixTM GXCycloneTM
DC FPGA is available today on: Solaris (32 and 64 bit) and Linux
© 2002 Synopsys, Inc. (22) CONFIDENTIAL
DC FPGA is Having Significant SuccessOver 80 Customers
© 2002 Synopsys, Inc. (23) CONFIDENTIAL
Fastest Path to PrototypeDC FPGA Partners
DSP Algorithms in SiliconDSP Algorithms in Silicon
Embedded InstrumentationEmbedded Instrumentation
Hardware Assisted VerificationHardware Assisted Verification
Configurable CoresConfigurable Cores
Reconfigurable Prototyping PlatformsReconfigurable Prototyping Platforms
Automated PartitioningAutomated Partitioning
© 2002 Synopsys, Inc. (24) CONFIDENTIAL
SummaryDesign CompilerDesign Compiler®® FPGAFPGA
• Industry standard ASIC-strength solutionFlexibility and Stability of DCAdvanced Algorithms
• Best timingAdaptive OptimizationTM Technology
• Fastest path to prototypeEnsuring Design Integrity between Prototype and ASIC
• Flexibility to target Altera FPGA or HardCopy Devices
Design Once!Design Once!