ECE 305 Spring 2015
ECE-‐305 Spring 2015 1
ECE 305 Homework SOLUTIONS: Week 12
Mark Lundstrom Purdue University
1) The energy band diagram for an MOS capacitor is sketched below. Assume T = 300K
and an oxide thickness of xo = 1.1 nm. Answer the following questions using the delta-‐depletion approximation as needed. (Note that EF = Ei at the oxide-‐silicon interface.) (This problem is similar to prob. 16.7, Pierret, SDF).
1a) Sketch the electrostatic potential vs. position inside the semiconductor.
Solution:
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HW Week 12 Solutions (continued)
1b) Roughly sketch the electric field vs. position inside the oxide and semiconductor.
Solution:
Note: We assume that there is no charge in the oxide and no charge at the oxide-‐Si interface.
1c) Do equilibrium conditions apply inside the semiconductor? Explain
Solution: YES. The Fermi level is constant, but even if the Fermi level in the metal does not align with the Fermi level in the semiconductor (as is the case when a gate voltage is applied) the oxide insures that no current flows, so the metal and semiconductor are two separate systems in equilibrium with possibly different Fermi levels. (Note: We assume that light is not shining on the semiconductor.)
1d) Roughly sketch the hole concentration vs. position inside the semiconductor.
Solution:
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HW Week 12 Solutions (continued)
1e) What is the hole concentration in the bulk?
Solution: p x→∞( ) = nie Ei −EF( ) kBT = 1010e0.51/0.026 = 3.3×1018 cm-‐3 p x→∞( ) = 3.3×1018 cm-3
1f) What is the hole concentration at the surface?
Solution: p x = 0( ) = nie Ei −EF( ) kBT = 1010e0 = 1×1010 p x = 0( ) = 1010 cm-3
1g) What is the surface potential?
Solution: φS = φ x = 0( )−φ x→∞( ) = 0.51V
1h) What is the gate voltage?
Solution: The Fermi level in the metal aligns with the Fermi level in the semiconductor, so the gate voltage must be zero. (Note: The fact that there is a volt drop across the oxide and the semiconductor with VG = 0 indicates that there is a workfunction difference between the metal and the semiconductor.)
1i) What is the voltage drop across the oxide?
Solution: The electric field at the surface of the semiconductor is given by eqn. (16.27) in SDF as:
E S =
2qN AφS
KSε0
We find the electric field in the oxide from:
KOE ox = KSE S so
E ox =
KS
KO
2qN AφS
KSε0
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HW Week 12 Solutions (continued)
The volt drop across the oxide is:
Δφox = x0E ox = x0
KS
Kox
2qN AφS
KSε0
alternatively we can write this as:
Δφox =
x0
KOε0
2qKSε0N AφS = −QB φS( )
Cox
where
QB φS( ) is the depletion charge in C/cm2 in the semiconductor and
Cox is the oxide capacitance in F/cm2
Putting in numbers:
Cox =
KOε0
x0
= 3.9×8.854×10−14
1.1×10−7 = 3.6×10−6 F/cm2
We found the doping density in 1e) and the surface potential in 1g), so
QD = − 2qKSε0N AφS = − 2×1.6×10−19 ×11.8×8.854×10−14 × 3.3×1018 × 0.51
QD = −7.5×10−7 C/cm2
Δφox = −
QD φS( )Cox
= 7.5×10−7
3.6×10−6 = 0.21
Δφox = 0.21 V
Question: If the substrate were n-‐type, as in the figure below, could you repeat this problem?
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HW Week 12 Solutions (continued) 2) There is currently great interest in replacing SiO2 with a higher dielectric constant
material. Different oxides are compared to SiO2 in terms of the “Equivalent Oxide Thickness” (EOT). EOT is the thickness of SiO2 that would give the same capacitance per unit area. What is the EOT of 4 nm of hafnium dioxide, HfO2, which has a relative dielectric constant of 25? Solution:
CHfO2
=KHfO2
ε0
xHfO2
CEOT =
KOε0
EOT (The capacitance of a layer of SiO2 of thickness, EOT.
By definition, the above two capacitances must be equal:
CHfO2
=KHfO2
ε0
xHfO2
= CEOT =KOε0
EOT
EOT = xHfO2
KO
KHfO2
= 4× 3.925
= 0.6nm EOT = 0.6nm
Note that 0.6 nm of SiO2 would be too leaky because of quantum mechanical tunneling, but 4 nm of HfO2 gives the same capacitance with less leakage current due to quantum mechanical tunneling.
3) Assume an MOS capacitor on a p-‐type Si substrate with the following parameters:
N A = 2.7 ×1018 cm-3 for the bulk doping Oxide thickness: xo = 1.1 nm KO = 3.9
QF = 0 (no charge at the oxide-‐Si interface) T = 300 K VG = 1 V Also assume that the structure is ideal with no metal-‐semiconductor workfunction difference. Determine the following quantities by analytical calculations. You should use the depletion or delta-‐depletion approximation for these calculations.
3a) The flatband voltage, VFB .
Solution: VFB = 0 because there is no workfunction difference and no charge at the interface.
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HW Week 12 Solutions (continued)
3b) The surface potential, φS .
Solution:
VG = φS + Δφox = φS −
QS φS( )Cox
= φS +2qKSε0N A
Cox
φS
(We are assuming here that all of the charge in the semiconductor is depletion charge -‐ no inversion charge. This assumption will be checked later.
VG = φS + β φS β =
2qKSε0N A
Cox
= 0.303
φS + β φS −VG = 0 is a quadratic equation for φS
φS =
−β ± β 2 + 4VG
2 (take positive sign. Since there is a positive gate
voltage, we should get a positive surface potential.) Putting in numbers, we find:
φS = 0.74 V Is this greater than 2φF ?
φF =
kBTq
lnN A
ni
⎛
⎝⎜⎞
⎠⎟= 0.026× ln 2.7 ×1018
1010
⎛⎝⎜
⎞⎠⎟= 0.505
2φF = 1.01V
Our use of the depletion approximation for QS φS( ) in the first equation is justified, and
φS = 0.74 V
3c) The electric field in the oxide, E OX .
Solution: Since there is no metal-‐semiconductor workfunction difference, the voltage on the gate is just 1V (no built-‐in voltage to worry about) and the voltage at the oxide-‐Si interface is 0.74 V, so
E ox =
VG −φS
x0
= 1− 0.741.1×10−7 = 2.4×106 V cm
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HW Week 12 Solutions (continued) Alternatively, we could do it another way. Gauss’s Law gives: KOε0E ox = −QS = −QB = 2qKSε0N AφS
QB = − 2qKSε0N AφS = − 2×1.6×10−19 ×11.8×8.854×10−14 × 2.7 ×1018 × 0.74
QB = −8.17 ×10−7 C/cm2
E ox = −
QB
κ oxε0
= 8.17 ×10−7
4×8.854×10−14 = 2.35×106
E ox = 2.3×106 V/cm
(slight round-‐off error gives different answers)
3d) The electric field in the silicon at the surface, E S .
Solution: At the oxide-‐Si interface, we have: KOε0E ox = KSε0E S
E S =
KO
KS
E ox =3.9
11.82.4×106( ) = 7.9×105
E S = 7.9×105 V/cm
3e) The depletion region depth, WD .
Solution:
WD =
2KSε0
qN A
φS = 2×11.8×8.854×10−14
1.6×10−19 × 2.7 ×1018 × 0.74
WD = 1.89×10−6 cm
WD = 18.9 nm
3f) The charge in the silicon, QS in C/cm2
Solution: From the solution to 2c): QS = −8.17 ×10−7 C/cm2
QS = −8.17 ×10−7 C/cm2
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HW Week 12 Solutions (continued) 3g) The charge on the gate, QG in C/cm2
Solution: Charge balance dictates that the charge on the gate must be equal and opposite to the charge in the semiconductor (there is no charge at the oxide-‐Si interface).
QG = −QS = +8.17 ×10−7 C/cm2
3h) The voltage drop across the oxide
Solution:
VG = Δφox +φS Δφox =VG −φS = 1− 0.77 = 0.23 V
Δφox = 0.23 V
3i) The threshold voltage for this MOS capacitor
Solution:
VT = 2φF −
QB 2φF( )Cox
= 1.01+2qKSε0N A 1.01( )
Cox
VT = 1.01+ 0.304 = 1.314 V
VT = 1.314 V
4) The measured IV characteristics of a 75 nm, unstrained Si, N-‐MOSFET are shown
below. Estimate the device metrics for this transistor. Specifically, determine: a) the on-‐current, b) the off current, c) the subthreshold swing, d) the DIBL, e) the output resistance, f) the transconductance in the saturation region, and g) the “on-‐resistance” (the resistance in the linear region for the maximum gate voltage).
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HW Week 12 Solutions (continued)
Solution:
On current in mA/µm : ≈ 800 µA/µm
The on-‐current is the current for the maximum gate and drain voltages.
Off current in µA/µm : ≈ 6 µA/µm
The off current is the current for zero gate voltage when the drain voltage is at its maximum value.
ION
IOFF S
DIBL RON
ROUT gm
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HW Week 12 Solutions (continued) Subthreshold swing in mV/decade:
≈ 85 mV/decade
This is the millivolts it take to increase the drain voltage by a factor of 10 when operating in the linear region. Typically measured at maximum drain voltage. DIBL in mV/V:
≈ 85 mV/V
The horizontal shift in gate voltage at a fixed subthreshold current between a low and high drain voltage. On-‐resistance in Ω-µm :
≈ 450 Ω− µm
The minimum resistance in te linear region. Output resistance: in Ω-µm ;
≈ 8000 Ω− µm
One over the slope of drain current vs. drain voltage in the saturation region. Transconductance in µS µm :
≈1000 µS/µm
(at maximum drain and gate voltage) The change in drain current divided by the change in gate voltage.
5) Real transistors have parasitic series resistances at the source and drain. As shown in
the figure below, the result is that the voltages applied to the terminals of the device are not the voltages on the terminals of the intrinsic device.
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HW Week 12 Solutions (continued) 5a) Modify the square law MOSFET equations to include the effects of source and
drain series resistances. Solution: The voltages in the square law expressions are the intrinsic voltages – not the voltages applied to the terminals. Using primes to denote the intrinsic voltages:
ID =
WµnCox
L′VGS −VT( ) ′VDS −
′VDS2
2⎡
⎣⎢
⎤
⎦⎥ 0 ≤ ′VDS <VDsat ′VGS ≥VT
ID =
WµnCox
2L′VGS −VT( )2
′VDS ≥VDsat ′VGS ≥VT Note that we use ′VGS instead of ′VG and ′VDS instead of ′VGS because with a series resistance, the intrinsic source is not at ground potential. Straightforward circuit analysis gives the intrinsic voltages as
′VGS =VG − ID RS
′VDS =VDS − ID RS + RD( ) Inserting these voltages in the square law theory gives the answer. Note that ID ends up on both sides of the equations, and it is not completely trivial to plot the IV with series resistance.
5b) The series resistances affect the drain current differently in the linear and the saturation regions. Explain how RS and RD affect the linear region drain current and the saturation region drain current.
Solution: Begin with the linear region and assume ′VDS
2 2 can be ignored:
ID =
WµnCox
L′VGS −VT( ) ′VDS =
WµnCox
L′VGS −VT( ) VDS − ID RS + RD( )⎡⎣ ⎤⎦
To keep track of the algebra, define: α =
WµnCox
L
ID =α ′VGS −VT( ) VDS − ID RS + RD( )⎡⎣ ⎤⎦
ID =α ′VGS −VT( )VDS −α ′VGS −VT( ) ID RS + RD( ) or
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HW Week 12 Solutions (continued)
ID =α ′VGS −VT( )VDS
1+α ′VGS −VT( ) RS + RD( ) =VDS
1α ′VGS −VT( ) + RS + RD( )
Note that
ID =
WµnCox
L′VGS −VT( ) ′VDS =
′VDS
RCH where
RCH = 1
α ′VGS −VT( ) is the resistance of the channel. Finally, we find:
ID =VDS
RCH + RS + RD( )
which is intuitively what we expect. In the absence of series resistance, we just have a channel resistance. In the presence of series resistance, the measured resistance in the linear region,
Rmeas =
VDS
ID is the sum of the intrinsic channel resistance and the two series resistors. Now consider the saturation region. If
′VDS =VDS − ID RS + RD( ) >VDsat , then we are saturated and
ID =
WµnCox
2L′VGS −VT( )2
= ID =WµnCox
2LVGS − ID RS −VT( )2
so if VDS is large enough, the RD does not matter. The current of the intrinsic device (no series resistance) would be
ID
i =WµnCox
2LVGS −VT( )2
so
ID
IDi =
VGS − ID RS −VT
VGS −VT
⎛
⎝⎜⎞
⎠⎟
2
ID
IDi = 1−
ID RS
VGS −VT( )⎛
⎝⎜
⎞
⎠⎟
2
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HW Week 12 Solutions (continued) When the volt drop across the series resistance of the source is comparable to the gate overdrive, then the saturation current decreases. The effect of the series resistors on the IV characteristic in the linear and saturation regions is shown below.
The source and drain series resistors increase the linear region resistance, and the source series resistance lowers the saturation current.