Improving Single Slope ADC and an Example Implemented in FPGA with 16.7 GHz Equivalent Counter Clock Frequency
Wu, Jinyuan
Fermilab
John Odeghe, Scott Stackley and Charles Zha
Oct. 2011
Voltage Measurement Voltage Measurement
Charge Measurement Charge Measurement
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 2
In Wilkinson ADC, a capacitor is charged and then discharged. The two schemes are suitable for different applications.
Single Slope ADC ?= Wilkinson ADC
TDCTDC
INPUT
Ramping Ref. Voltage
INPUT
Timing Uncertainty Confinement
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 3
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 4
Feeding CMP output to CK port of the register causes unnecessary challenges due to unconfined timing uncertainty:
Must use Gray Code Counter.
Must match propagation delays of all bits.
A Common Implementation
GrayCode
Counterf
+ CMP
-
Register
+ CMP
-
Register
TimingUncertainty
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 5
Feeding CMP output to D port of a FF reduces complexity: The counter is regular binary counter. No propagation delay matching is needed.
An Improvement
BinaryCounter
+ CMP
-Hold
f
Timing Uncertainty
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 6
Confining timing uncertainty opens possibilities for further improvements: Resolution or sampling rate can be doubled easily. Improvements by a factor of 4, 8, 16, 32 etc. are possible.
Doubling Digitizing Resolution
BinaryCounterf
+ CMP
-Hold
Improvement,Further Improvement,Further, Further Improvement
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 7
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 8
Crossing time between ramping reference voltage and input voltage is digitized.
Finer timing measurement resolution is preferable.
Equivalent (Virtual) Clock Frequency
T1
V1
T2
V2
Sampling Period
Equivalent Clock Frequency = 1/DT
+ CMP
-TDC
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 9
Single Slope ADC Implemented in FPGA
ShaperSignalSource
Shaper
The ramping reference voltage is generated from digital outputs of FPGA. The differential receivers for the FPGA input are used as comparator. TDC is implemented in the FPGA with approximately 60 ps bin width.
FPGA
TDC
TDC
R R
C
R1
VREF
SignalSource
The Wave Union TDC Implemented in FPGA
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 10
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 11
TDC Using FPGA Logic Chain Delay
This scheme uses low-cost FPGA devices
Fine TDC precision can be implemented in slow devices (e.g., 60 ps (LSB) in EP2C8T144C6).
FPGA internal structures cause uneven bin widths and ultra-wide bins.
IN
CLK
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64
bin
wid
th (
ps)
Ultra-wide Bins
Wu Jinyuan, Fermilab, [email protected] 12May 2009
0: Hold
0
1: Unleash
1
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64 80 96 112 128bin
wid
th (p
s)
Plain TDC
Wave Union TDC A
+
Ultra-wide bins are sub-divided.
The Wave Union TDC SchemeRegular TDC records only one transition
Wave Union TDC records multiple transitions.
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64
bin
wid
th (
ps)
Ultra-wide Bins
Wave Union?
Photograph: Qi Ji, 2010
Oct. 2011, Wu Jinyuan, Fermilab [email protected] 13
Improving Single Slope ADC and an Example in FPGA
TDC Test Results
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 14
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 15
The Test Hardware (2008)
2008
Altera Cyclone II + VME (~$1k)
FPGA: EP2C8T144C6 ($28.80)
16 channel: 25 ps
2 channel: 10 ps
81 mW/channel
Ref: Search “Wave Union TDC”
Wu Jinyuan, Fermilab, [email protected] 16May 2009
The Test Module & Result
Two NIM inputs
FPGA with 8ch TDC
Data Output via Ethernet
BNC Adapter to add delay @ 140ps step.
0 1 2
RMS 10ps
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64 80 96 112 128bin
wid
th (p
s)
Plain TDC
Wave Union TDC A
0
500
1000
1500
2000
2500
0 16 32 48 64 80 96 112 128
bin
t(p
s)
Plain TDC
Wave Union TDC A
DNLHistogram
LUT
S
Auto-Calibration
In(bin) Out(p
s)
1
2
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 17
The Test Hardware (2011)
2011
Altera Cyclone III Starter Kit ($211+$50)
FPGA: EP3C25F324C6N ($73.90)
32 channel: 30 ps (25 ps with linear power supply)
27 mW/channel
www.altera.com
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 18
Delta T Between NIM Inputs
TDC channels internally ganged together has smallest standard deviation of time differences. Typical channel pairs sharing same fan-out unit has 30 ps RMS. Timing jitters of the fan-out units add to the measurement errors.
0
10
20
30
40
50
60
10 100 1000 10000
sigm
a (p
s)
dt (ps)
8ns 6ns 4ns 2ns
0
500
1000
1500
2000
2500
1500 1700 1900 2100 2300 2500
dt (ps)
HistA HistB HistC
PulseGen.
LeCroy429ANIMFAN-OUT
NIMTo
LVDS
FPGA
LeCroy429ANIMFAN-OUT
TDC
TDC
TDC
TDC
TDC
TDC
TDC
TDC
NIMTo
LVDS
A
B
C
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 19
Specifications
RMS Resolution (Delta T between two channels) 25 to 30 ps
Same channel re-hit time interval 64 ns
Temporary buffer capacity 128 hits/(4 ch)/(16 us)
LVDS output port rate: 250 M bits/s/port
Output capacity in each LDVS output port: 128 hits/(16 ch)/(16 us)
Number of LVDS output ports: 1, 2, 3, 4/(16 ch)
Power Consumption (Core only) 9.3 mW/channel
Power Consumption (Total) 27 mW/channel
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 20
If You Want to Try
The FPGA on the Starter Kit is fairly powerful. More than 16 pairs LVDS I/O can be accessed via the daughter card. FPGA can fit 32 channels but implementing 16 channels is more practical given the I/O pairs. TDC data are stored in the RAM on the board and can be readout via USB. A good solution for small experiment systems as well as student labs.
www.altera.comDK-START-3C25NCyclone III FPGA Starter Kit$211
www.altera.comTHDB-H2G (HSMC to GPIO Daughter Board)$50
ADC Test Results
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 21
FPGA
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 22
A Demo Proto-type Module
Shaper
DataHandling
FPGA
Con
nect
or Shaper
Shaper
Shaper
TDC
TDC
TDC
TDC
A symmetrical summing circuit is used.
Both the shaper output and the ramping reference are fully differential for low noise performance.
EthernetInterface
FPGA
TDC
TDC
R RC
R1
VREF+
4xR2
4xR2
VREF-
VIN1+
VIN1-
VIN2+
VIN2-
23
Single-ended and Differential Comparators
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
0
0.5
1
1.5
2
2.5
0 32 64 96 128 160 192 224 256
V
t (ns)
Vc+ Vc- Vin+/2 Vin-/2
FPGA
TDC
TDC
R RC
R1
VREF+
4xR2
4xR2
VREF-
VIN1+
VIN1-
VIN2+
VIN2-
FPGA
TDC
TDC
R R
C
R1
VREF
24
Test Result: 2 M samples/s, 12 bits
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
INPUT
Ramping Ref. Voltage
DigitizedData
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 25
Noise/Pedestal Width
Each bin in the histogram is (full scale)/4096. The measurement is taken when there is no input signal. There is no intrinsic noise preventing the comparator + TDC structure
from being used as a 12-bit ADC
FWHM ~ 3 bins FWHM ~ 2 bins
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 26
A Single-ended Test Module
A single-ended circuit is used. The ramp generation circuit and the
input connectors are put on the proto-type board.
The FPGA is on the Cyclone III Starter Kit evaluation board.
FPGA
TDC
TDC
R R
C
R1
VREF
0
64
128
192
256
320
384
448
512
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000
AD
C Co
unts
ns
Falling Rising
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 27
Test Result: 62.5 M Samples/s, ~7 bits
The digitized data follow the input pulses as expected.
Large noise can be seen in the digitized raw data partially due to single-ended scheme and partially due to long signal paths from the prototype board to the FPGA pins through the daughter card.
Improvements can be anticipated with a better hardware.
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 28
Summary
Today, TDC in FPGA has reached fine time resolutions (<100 ps LSB). It becomes feasible using an FPGA plus a few passive components to
implement the “fully digital” single slope ADC for most applications in high-energy physics and nuclear science.
# of Bits
Max. Sampling Rate:(TDC LSB = 60 ps)
Test Results:
7 1/(128*60 ps) = 130 MHz 7 bits @ 62.5 MHz
8 1/(256*60 ps) = 65 MHz
9 1/(512*60 ps) = 32.6 MHz
10 1/(1024*60 ps) = 16.3 MHz
11 1/(2048*60 ps) = 8.1 MHz
12 1/(4096*60 ps) = 4 MHz 12 bits @ 2 MHz
The End
Thanks
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 30
The Wave Union TDC using FPGA A possible choice of the TDC can
be a delay line based architecture called the Wave Union TDC implemented in FPGA.
Shown here is an ASIC-like implementation in a 144-pin device.
18 Channels (16 regular channels + 2 timing reference channels).
This FPGA (EP2C8T144C6) costs $28, $1.75/channel. (AD9222: $5.06/channel)
LSB ~ 60 ps. RMS resolution < 25 ps. Power consumption 1.3W, or 81
mW/channel. (AD9222: 90 mW/channel)
In
CLK
Wave UnionLauncher A
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 31
Time Measurement Errors Due to Power Supply Noise
Typical RMS resolution is 25-30 ps. Measurements with cleaner power (diamonds) is better than noisy power (squares).
SwitchingPower Supply Linear
Power Supply
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 32
Single Slope ADC Test: Waveform Digitization
1
1.5
2
2.5
2500 3000 3500 4000 4500 5000 5500
t(ns)
V
Leading Ramp Trailing Ramp
0
8
16
24
32
40
48
56
64
0 32 64 96 128 160 192 224 256
Leading Ramp Trailing Ramp
RawData
Input Waveform, Overlap Trigger& Reference Voltage
Calibrated
FPGA
TDC
TDC
50 50
1000pF
100
VREF
Shown here is a demo of a 6-bit single slope TDC.
Sampling rate in this test is 22 MHz.
Both leading and trailing reference ramps are used in this example.
Nonlinear reference ramping is OK. The measurement can be calibrated.
33
Historical Implementation in ASIC TDC
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
DLL Clock Chain
Encoder
CoarseTime
Counter
HIT CoarseTime
Register
CoarseTime
SelectionLogic
c1c0
HIT is used as CK input which creates unnecessary challenges.
Deadtime is unavoidable. Coarse time recording needs special care. Two array + encoder sets are needed for raising edge and falling edge. The register array must be reset for next event. The encoder must be re-synchronized with system clock in order to interface with readout stage.
Unnecessary Challenges = Extra Efforts + Reduced Performance
34
Unnecessary Challenges
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
In history, Gray code counters, double counters and dual registers + MUX are found in ASIC TDC coarse time counter schemes.
Theses are unnecessary if the TDC is designed appropriately. In FPGA, a plain binary counter is sufficient.
CoarseTimeCounter
CoarseTimeCounter
CoarseTimeCounter
GrayCodeCounter
000001011010110111101100
Unnecessary for FPGA TDC
35
Coarse Time Counter
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
The timing uncertainty between HIT and CLK is confined in the sampling register array.
All the remaining logics are driven by the CLK signal.
No special cares such as Gray code counter is needed for coarse time counter.
Hit Detect Logic
CoarseTimeCounter
FineTimeEncoder
HIT
CLK
ENA
FineTime
CoarseTime
DataValid
36
A Better Implementation
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA
DLL Clock Chain
OR + Register
ClockDomainTransfer
DV EG T4..T0
HITMulti-
SamplingRegister
Array
Deadtimeless operation is possible. No special care is needed for coarse time. Both raising and falling edges are digitized with a single array + encoder set. No resetting is needed for the register array. The output is synchronized with the system clock and is ready to interface with readout stage.
CoarseTime
Counter
TC
16-bit Encoder with Registered Outputs 16-bit Encoder with Registered Outputs
HIT is used as D input.
Oct. 2011, Wu Jinyuan, Fermilab [email protected]
Improving Single Slope ADC and an Example in FPGA 37
Typical ADC devices creates noise that may interfere the analog circuits. The time interval for resetting of the common reference voltage may be noisy
but analog signal is not sampled during it. There is no digital control activities during ramping up of the common
reference voltage.
Digital Noise During Digitization
T1
V1 T2
V2
Noisy NoisyClean Clean
ADCShaper