ITRS004Optimization of Package Power Delivery and Power Removal Solutions to meet Platform level Challenges
Optimization of Optimization of Package Power Package Power Delivery and Power Delivery and Power Removal Solutions to Removal Solutions to meet Platform level meet Platform level ChallengesChallengesKaladhar RadhakrishnanMichael J. HillKemal AygünChia-Pin ChiuGaurang Choksi
Kaladhar RadhakrishnanKaladhar RadhakrishnanMichael J. HillMichael J. HillKemal Kemal AygAygüünnChiaChia--Pin ChiuPin ChiuGaurang ChoksiGaurang Choksi
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AgendaAgenda
Metrology for Platform Level Power Delivery Metrology for Platform Level Power Delivery CharacterizationCharacterizationNew Power Delivery Architecture and Thermal New Power Delivery Architecture and Thermal Considerations for MultiConsiderations for Multi--Core ServersCore ServersRecent Advances in Package Power Delivery Recent Advances in Package Power Delivery and Power Removal Solutionsand Power Removal Solutions
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AgendaAgenda
Metrology for Platform Level Power Delivery Metrology for Platform Level Power Delivery CharacterizationCharacterizationNew Power Delivery Architecture and Thermal New Power Delivery Architecture and Thermal Considerations for MultiConsiderations for Multi--Core ServersCore ServersRecent Advances in Package Power Delivery Recent Advances in Package Power Delivery and Power Removal Solutionsand Power Removal Solutions
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Enabling Platform Level Power Enabling Platform Level Power Delivery CharacterizationDelivery Characterization
The Power Delivery NetworkThe Power Delivery NetworkTime Domain ValidationTime Domain ValidationWhat is What is Z(fZ(f)?)?Measurement SetupMeasurement SetupApplication ExamplesApplication ExamplesStatus & PlansStatus & Plans
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Typical Power Delivery NetworkTypical Power Delivery Network
RMBRMB
CMBCMB
LMBLMB
RblkRblk
LblkLblk
VIDVID
LvrLvr RvrRvr
CblkCblk
LsktLskt RsktRskt
RpkgRpkg
CpkgCpkg
LpkgLpkg
CdieCdie
RdieRdie
LviaLvia RviaRvia
IdieIdie
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Time Domain ValidationTime Domain Validation
∆V∆I
Voltage Transient Test (VTT)
Tool
Voltage Voltage Transient Transient Test (VTT) Test (VTT)
ToolTool
Test Platform
Test Test PlatformPlatform
LoadlineLoadline = = ∆∆V/V/∆∆II
VTT tool is used as CPU emulatorVTT tool is used as CPU emulatorDrawbacks with TD validationDrawbacks with TD validation
–– VTT tool rise time different from that of processorVTT tool rise time different from that of processor–– Not enough insight about the PD solutionNot enough insight about the PD solution
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What is Z(f)?What is Z(f)?
Sink current from socketSink current Sink current from socketfrom socket
Measure Voltage at MB sense pts.Measure Voltage Measure Voltage at MB sense pts.at MB sense pts.
i(t)i(ti(t))
v(t)v(tv(t))
SocketSocketSocketVR ComponentsVR ComponentsVR Components
V(f) = FFTv(t)I(f) = FFTi(t)
V(fV(f) = ) = FFTFFTv(tv(t))I(fI(f) = ) = FFTFFTi(ti(t))
Fourier TransformFourier Transform can be used can be used to determine frequency content to determine frequency content of a time domain signalof a time domain signal
Z(f)=Z(f)=V(fV(f) / ) / I(fI(f))
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Platform Platform Z(fZ(f) ) –– Measurement SetupMeasurement SetupHost System Host System Scope Scope
USBUSB
GPIBGPIB
ProbesProbes
VTT ToolVTT Tool Target PlatformTarget Platform
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Time & Frequency DomainsTime & Frequency Domains
freqfreqff00 3f3f00 5f5f00 7f7f0000
1/31/31/51/5
1/71/7
11
1/21/2
ff00 3f3f00 5f5f0000 7f7f00
00
1/1/ ff00
freqfreq
freqfreq
timetime
timetime
i(ti(t))I(fI(f))
FFT
v(tv(t)) V(fV(f))
FFT
Z(fZ(f) = ) = V(fV(f) ) / / I(fI(f)) Z(fZ(f))
ff00 3f3f00 5f5f00 7f7f00
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Time & Frequency DomainsTime & Frequency Domains
ff11 3f3f11 5f5f11
1/31/31/51/5
7f7f11
1/71/7
11
00
1/21/2
ff11 3f3f11 5f5f1100 7f7f11
ff00 3f3f00 5f5f0000 7f7f00
1/1/ ff11
timetime
timetime
i(ti(t))I(fI(f))
FFT
freqfreq
v(tv(t)) V(fV(f))
FFT
freqfreq
Z(fZ(f))
freqfreqff11 3f3f11 5f5f11 7f7f11
Sweep frequency to populate the Sweep frequency to populate the data points on the impedance data points on the impedance profile plotprofile plot
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AutomationAutomation
SpecifySpecifyFrequencyFrequency
SpecifySpecifyCurrentCurrent
VTT Tool VTT Tool SettingsSettings
Scope Scope SettingsSettings
Platform Z(f) can be found in ~3Platform Z(f) can be found in ~3--5 minutes5 minutes
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Typical Platform Typical Platform Z(fZ(f))
0
0.5
1
1.5
2
2.5
3
3.5
4
0.0001 0.001 0.01 0.1 1 10
Impe
danc
e (m
Ω)
Frequency (MHz)
Influenced by VR design & bandwidth
Influenced by bulk caps
Influenced by ceramic caps
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Application Application –– LGA775 platformLGA775 platform
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0.0001 0.001 0.01 0.1 1 10
Bulk Caps
Bulk Caps
MLCC CapsMLCC Caps
Frequency (MHz)
Impe
danc
e (m
Ω) Loadline = 1mΩ
10 x 560 uF Bulk Caps12 x 22 uF MLCC Caps
10 x 820 uF Bulk Caps12 x 22 uF MLCC Caps
10 x 820 uF Bulk Caps16 x 22 uF MLCC Caps2 x 47uF MLCC Caps
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Status & Plans for OEM DeploymentStatus & Plans for OEM Deployment
Setup and plans demonstrated to OEMsSetup and plans demonstrated to OEMs–– Aug 5 Intel Power Summit at Dupont, WAAug 5 Intel Power Summit at Dupont, WA
Customer version of the automation tool is Customer version of the automation tool is currently being developedcurrently being developed–– Tool will be designed to support different Tool will be designed to support different
measurement setups using multiple scopesmeasurement setups using multiple scopes–– Automation tool will be made available to the Automation tool will be made available to the
OEMs along with the next release of the VTT toolOEMs along with the next release of the VTT tool
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SummarySummary
Capability developed for fully automated Capability developed for fully automated platform impedance profile measurementsplatform impedance profile measurements
Steps underway for deployment of Steps underway for deployment of measurement capability to OEMsmeasurement capability to OEMs
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AgendaAgenda
Metrology for Platform Level Power Delivery Metrology for Platform Level Power Delivery CharacterizationCharacterizationNew Power Delivery Architecture and Thermal New Power Delivery Architecture and Thermal Considerations for MultiConsiderations for Multi--Core ServersCore ServersRecent Advances in Package Power Delivery Recent Advances in Package Power Delivery and Power Removal Solutionsand Power Removal Solutions
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Novel PD Architecture and Thermal Novel PD Architecture and Thermal Considerations for MultiConsiderations for Multi--Core ServersCore Servers
Itanium Server PD ArchitectureItanium Server PD ArchitectureXeon Server PD ArchitectureXeon Server PD ArchitectureMotivation for new architectureMotivation for new architectureNew PD Scheme for MultiNew PD Scheme for Multi--Core ServersCore ServersThermal ConsiderationsThermal Considerations
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Itanium Server PD ArchitectureItanium Server PD ArchitecturePower is supplied through a power podPower is supplied through a power podPower is delivered through a topside power connector Power is delivered through a topside power connector from one side of the packagefrom one side of the package
Power PodPower PodPower Pod
Mother BoardMother BoardMother Board
Package & HSPackage & HSPackage & HS
Power Connector LandsPower Connector LandsPower Connector Lands
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Xeon Server PD ArchitectureXeon Server PD ArchitecturePower is supplied through pins on the socketPower is supplied through pins on the socketPower is supplied from the voltage regulator through Power is supplied from the voltage regulator through the pins from two sides on the packagethe pins from two sides on the package
VR ComponentsVR ComponentsVR Components VR ComponentsVR ComponentsVR ComponentsPackagePackagePackageDieDieDie
SocketSocketSocket
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Motivation for New ArchitectureMotivation for New Architecture
Power Delivery performance is limited with either PD Power Delivery performance is limited with either PD architecturearchitectureMB Real Estate for Power DeliveryMB Real Estate for Power DeliveryOpportunity for synergy between the Xeon and Opportunity for synergy between the Xeon and Itanium serversItanium servers
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New Power Delivery ArchitectureNew Power Delivery Architecture
CPU & PackageCPU & PackageCPU & Package
VR Board & HeatsinkVR Board & VR Board & HeatsinkHeatsink
CPU HeatsinkCPU CPU HeatsinkHeatsink
MB & SocketMB & SocketMB & Socket
CPU HeatsinkCPU CPU HeatsinkHeatsink
VR ComponentsVR ComponentsVR Components
Backing Plate & Chassis StiffenerBacking Plate & Backing Plate & Chassis StiffenerChassis Stiffener
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New Architecture New Architecture –– Package DetailsPackage DetailsFourFour--sided power delivery scheme for improved sided power delivery scheme for improved performanceperformanceDedicated power connector is more scalableDedicated power connector is more scalable
Power Connector Lands
Power Power Connector Connector LandsLands
CPUCPUCPU
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CrossCross--SectionSection
TIM1TIM1VR VR HeatsinkHeatsink
CPU CPU HeatsinkHeatsink
VR VR HeatsinkHeatsink
VR ComponentsVR Components VR ComponentsVR ComponentsPower ConnectorPower Connector Power ConnectorPower Connector
TIM2TIM2TIM3TIM3 TIM3TIM3
VR components moved to the VR board to free up MB VR components moved to the VR board to free up MB real estatereal estateNew TIM3 material introduced to cool VR componentsNew TIM3 material introduced to cool VR components
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Thermal ConsiderationsThermal ConsiderationsCPU CoolingCPU Cooling
–– Increased die size due to multiple cores improves CPU Increased die size due to multiple cores improves CPU cooling capacitycooling capacity
VR ComponentsVR Components–– Increased power dissipation from the VR components due Increased power dissipation from the VR components due
to the increasing current levelsto the increasing current levels–– New TIM3 material introduced to keep VR component New TIM3 material introduced to keep VR component
temperature under spectemperature under spec
Power ConnectorPower Connector–– Joule heating in the power delivery path can drive up power Joule heating in the power delivery path can drive up power
connector temperatureconnector temperature–– Need to contain maximum current through connector pinsNeed to contain maximum current through connector pins
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Thermal Analysis of the VR BoardThermal Analysis of the VR BoardGlobal model to obtain temperature distribution across Global model to obtain temperature distribution across VR boardVR board
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Thermal Analysis of the ConnectorThermal Analysis of the ConnectorLocal model to estimate connector selfLocal model to estimate connector self--heating as a heating as a function of current through the pin function of current through the pin
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SummarySummary
Novel PD architecture introduced for multiNovel PD architecture introduced for multi--core serverscore servers
–– 4 sided power delivery for better performance4 sided power delivery for better performance–– Dedicated power connector makes the new Dedicated power connector makes the new
architecture more scalablearchitecture more scalable
Unified platform strategy for Xeon and Unified platform strategy for Xeon and Itanium server productsItanium server productsTIM3 material intrTIM3 material introduced to help keep VR and oduced to help keep VR and power connector temperature under specpower connector temperature under spec
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AgendaAgenda
Metrology for Platform Level Power Delivery Metrology for Platform Level Power Delivery CharacterizationCharacterizationNew Power Delivery Architecture and Thermal New Power Delivery Architecture and Thermal Considerations for MultiConsiderations for Multi--Core ServersCore ServersRecent Advances in Package Power Delivery Recent Advances in Package Power Delivery and Power Removal Solutionsand Power Removal Solutions
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Advances in Package Power Delivery Advances in Package Power Delivery and Power Removal Solutionsand Power Removal Solutions
Desktop & Mobile Desktop & Mobile LoadlineLoadline TrendsTrendsEvolution of CapacitorsEvolution of CapacitorsAdvances in Socket TechnologyAdvances in Socket TechnologyPackage Technology ImprovementsPackage Technology ImprovementsSummarySummary
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Desktop & Mobile Desktop & Mobile LoadlineLoadline TrendsTrends
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008
Year
Load
line
(mill
iohm
s)DesktopMobile
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Capacitor TechnologyCapacitor Technology
0805 2T Capacitor0805 2T Capacitor 0805 IDC0805 IDC 0603 IDC0603 IDC Array CapacitorArray Capacitor
Capacitor technology has evolved over the yearsCapacitor technology has evolved over the years–– Transitioned from 2T capacitors to 0805 Transitioned from 2T capacitors to 0805 IDCsIDCs starting with starting with
processors in the 130 nm nodeprocessors in the 130 nm node–– Processors in the 65 nm node have started using 0603 Processors in the 65 nm node have started using 0603 IDCsIDCs–– Future generation processors could potentially use array Future generation processors could potentially use array
capacitors if the technology warrants itcapacitors if the technology warrants it
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Capacitor ExampleCapacitor ExampleReducing body size drives up capacitor count Reducing body size drives up capacitor count
Single Core ProcessorSingle Core Processor Dual Core ProcessorDual Core Processor
(16 x 0805 (16 x 0805 IDCsIDCs)) (35 x 0603 (35 x 0603 IDCsIDCs))
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Impedance Profile ComparisonImpedance Profile Comparison
0.010.01 0.10.1 11 1010 100100 10001000
Frequency (MHz)Frequency (MHz)
Impe
danc
eIm
peda
nce
Increased number of capacitors reduces high frequency resonant peakSingle Core (16 x 0805 IDCs)
Dual Core (35 x 0603 IDCs)
Impedance vs. FrequencyImpedance vs. Frequency
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Socket TechnologySocket Technology
Socket 37049.5 x 49.5 mmSocket 370Socket 37049.5 x 49.5 mm49.5 x 49.5 mm
Socket 47835 x 35 mmSocket 478Socket 47835 x 35 mm35 x 35 mm
Socket 77537.5 x 37.5 mmSocket 775Socket 77537.5 x 37.5 mm37.5 x 37.5 mm
Improvement in socket technology has enabled us to Improvement in socket technology has enabled us to scale the pitch and fit more pins for a given areascale the pitch and fit more pins for a given area
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Package ResistancePackage Resistance90nm Processor Package90nm Processor Package 65nm Processor Package65nm Processor Package
Packages for the 65nm processors have increased Packages for the 65nm processors have increased copper in the core layers to reduce resistancecopper in the core layers to reduce resistance
35 um35 um68 um68 um
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Power Removal StrategiesPower Removal Strategies
Temp – Silicon(Tj)
Temp Temp –– SiliconSilicon(T(Tjj))
Temperature GradientTemperature Gradient HeatsinkDuct out heatPackaging
Smooth out Hot Spots
Temp – Package Case(Tc)
Temp Temp –– Package CasePackage Case((TTcc)) Temp – Ambient
(Ta)Temp Temp –– AmbientAmbient
(T(Taa))
Packaging StrategyPackaging Strategy–– Hot spot mitigationHot spot mitigation–– Reduction in thermal resistance (bulk & interface)Reduction in thermal resistance (bulk & interface)
Heat Sink StrategyHeat Sink Strategy–– Material & Geometry OptimizationMaterial & Geometry Optimization–– Cost effective manufacturabilityCost effective manufacturability
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Hot Spot mitigationHot Spot mitigationExample: ItaniumExample: ItaniumExample: Itanium
Integrated HeatSpreader
Integrated HeatIntegrated HeatSpreaderSpreader
High conductivity Interface MaterialHigh conductivity High conductivity Interface MaterialInterface Material
Integratedheat pipeIntegratedIntegratedheat pipeheat pipe
Polymer -> SolderPolymer Polymer --> Solder> Solder
Example: Pentium 4Example: Pentium 4Example: Pentium 4
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Heat Sink TechnologyHeat Sink Technology
SkiveSkive
Extrusion Extrusion HeatsinksHeatsinks
FanFan--sinkssinks
Spiral FanSpiral Fan--sinksinkCrimped FinCrimped Fin
Hea
t Sin
k Th
erm
al P
erfo
rman
ceH
eat S
ink
Ther
mal
Per
form
ance
TIMETIME
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SummarySummaryThe power delivery impedance target has been The power delivery impedance target has been shrinking steadily over the yearsshrinking steadily over the yearsCapacitor technology has been steadily improving Capacitor technology has been steadily improving to address high frequency noiseto address high frequency noiseImprovements in socket and package technology Improvements in socket and package technology help reduce DC resistancehelp reduce DC resistanceUse of the heat spreader and better TIM material Use of the heat spreader and better TIM material have reduce package thermal resistancehave reduce package thermal resistanceHeat sink technology has been improving to Heat sink technology has been improving to enhance cooling capability without driving up costenhance cooling capability without driving up cost
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