EE720A Study of Pipeline Architectures for High-
Speed Synchronous DRAM’s
Ranjith MurugesanSpring Semester 2015
May 3, 2023
May 3, 2023 EE720 Paper Presentation 2
Author and Affiliations
• Hoi-Jun Yoo• Department of Electronic Engineering ,
Kangwon National University,Kangwon-Do,Korea-200-701
• Graduated from Seoul National University,received M.S and Ph.D degrees from Electrical Engineering
Contd..
• Full time advisor- Korean Ministry of Information and Communication, VSCEL pioneer in Bell Communications Research at Red Bank, USA , Manager of DRAM design group at Hyundai Electronics designing
• Published 250 papers, wrote or edited 5 books
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Problem Statement
The performances of SDRAM’s with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. •On-Chip cache refill time•Various pipeline architecture comparison•Parallel registered wave pipeline architecture
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On-Chip Cache Refill Time
• System clock time• texec =
Nreadτ+NreadMttotal+Nstoreηwriteτ
• mτ >=tacc
• ttotal = mτ+ (n-1) τ
• τ = αtacc
• α = 1/m • ttotal = (m+n-1) (αtacc)
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Contd..When the secondary cache is omitted and only SDRAM main memory is used,•Speedup = 4m/(m+3)•ttotal = (1+3/m)tacc
•mo = √(taccAtot/tlAl)
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Comparison of Different Pipeline Architecture
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
•3 stage pipeline architecture•τ > tacc/3•4 stage pipeline architecture•ttotal =7α2tacc<6α1tacc ;
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Prefetch Pipeline Architecture
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
•Prefetch pipeline architecture•τ = tacc/3;Y addresses are not free to input randomly•Wave pipeline architecture
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Contd..
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
•Common idea : More latches into the column address access path•No overheads •tw < tacc / m ;condition satisfied at the address buffer ,not at pipeline end
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Parallel Registered Wave Pipeline Architecture
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
•t1 – t2+tsink
•τ = tacc – t’acc +tvalid ;
• tvalid = tsink + margin
•τ < tacc/m
Contd..
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
•tvalid = rτ-(tacc –t’acc )•τ=(1/r)(tacc- t’acc+tvalid)• If r = m => τ=tacc /m; tvalid = t’acc
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Comparision of different pipeline architecture
Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603
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Conclusion
• Better than conventional pipeline architecture
• Parallel registered architecture have smallest τ and ttotal
• Speedup
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Questions ?
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