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Arithmetic Logic Unit Main Module Test Bench module ALU(op1,op2,out,opt,enb); input enb; input [3:0] op1; input [3:0] op2; input[3:0]opt; output [3:0] out; reg [3:0] out; always@(op1 or op2 or opt or enb) begin if(enb == 1) begin case(opt) 4'b0000: out = (op1+op2); 4'b0001: out = (op1*op2); 4'b0011: out = (op1-op2); 4'b0010: out = (op1/op2); endcase end end endmodule module test_Alu; reg enb; reg [3:0] op1; reg [3:0] op2; reg [3:0]opt; wire [3:0] out; ALU g1(op1,op2,out,opt,enb); initial begin enb = 1'b1; op1 = 4'b0100; op2 = 4'b0010; opt = 4'b0000; #100 enb = 1'b1; op1 = 4'b0100; op2 = 4'b0010; opt = 4'b0001; #100 enb = 1'b1; op1 = 4'b0100; op2 = 4'b0010; opt = 4'b0010; #100 enb = 1'b1; op1 = 4'b0100; op2 = 4'b0010; opt = 4'b0011; #100 enb = 1'b0; op1 = 4'b0100; op2 = 4'b0010; opt = 4'b0000; #100

Arithmetic logic unit Assembly Language Code

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Page 1: Arithmetic logic unit Assembly Language Code

Arithmetic Logic Unit

Main Module Test Benchmodule ALU(op1,op2,out,opt,enb);input enb;input [3:0] op1; input [3:0] op2;input[3:0]opt;output [3:0] out;reg [3:0] out;always@(op1 or op2 or opt or enb) beginif(enb == 1) begincase(opt)4'b0000: out = (op1+op2);

4'b0001: out = (op1*op2);

4'b0011: out = (op1-op2);

4'b0010: out = (op1/op2);endcase

endendendmodule

module test_Alu;reg enb;reg [3:0] op1; reg [3:0] op2;reg [3:0]opt;wire [3:0] out;

ALU g1(op1,op2,out,opt,enb);initial begin

enb = 1'b1;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0000;#100enb = 1'b1;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0001;#100enb = 1'b1;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0010;#100enb = 1'b1;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0011;#100

enb = 1'b0;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0000;#100enb = 1'b0;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0001;#100enb = 1'b0;op1 = 4'b0100;

Page 2: Arithmetic logic unit Assembly Language Code

op2 = 4'b0010;opt = 4'b0010;#100enb = 1'b0;op1 = 4'b0100;op2 = 4'b0010;opt = 4'b0011;

endendmodule

Output