8085 Microprocessor Architecture

Course: BCA-2nd Sem

Subject: Introduction to

Microprocessor

Unit-2

1

1) Combinational

2) Sequential

• Combinational logic circuits (circuits without a memory):

Combinational switching networks whose outputs depend only on the current inputs.

• Sequential logic circuits (circuits with memory):

In this kind of network, the outputs depend on the current inputs and the previous inputs. These networks employ storage elements and logic gates.

LOGIC CIRCUITS

COMBINATIONAL CIRCUITS[1]

• Most important standard combinational circuits are:

• Adders

• Subtractors

• Comparators

• Decoders

• Encoders

• Multiplexers

Available in IC’s as MSI and used as

standard cells in complex VLSI (ASIC)

ANALYSIS OF COMBINATIONAL

LOGIC[1]

ANALYSIS OF COMBINATIONAL

LOGIC

ANALYSIS OF COMBINATIONAL

LOGIC

DESIGN OF COMBINATIONAL

LOGIC1. From the specifications of the circuit,

determine the number of inputs and outputs

2. Derive the truth table that defines the

relationship between the input and the output.

3. Obtain the simplified Boolean function using

x-variable K-Map.

4. Draw the logic diagram and verify the

correctness of the design.

DESIGN OF COMBINATIONAL

LOGIC[2]

• Example: Design a combinational circuit with three inputs and one output. The output is a 1 when the binary value is less than three.

• The output is 0 otherwise.

BINARY ADDER – Half Adder[2]

Implementation of Half Adder

BINARY ADDER - Full Adder[2]

Full Adder in SOP[2]

Implementation Full Adder with two

half Adders[2]

4-BIT FULL ADDER[2]

4 bit Adder

Magnitude Comparator

• A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.

A > B

A = B

A < B

• Algorithm Consider two numbers, A and B, with four digits each:

A=A3 A2 A1 A0

B=B3 B2 B1 B0

• xi=1 if A=B=0 or A=B=1

• xi=AiBi+ Ai’Bi’ for i=0,1,2,3 XNOR

• For equality to exist, all xi variables must be equal to 1:

• (A=B)=X3 X2 X1 X0AND Operation

Magnitude Comparator

• To determine if A is greater than or less than

B, we inspect the relative magnitudes of

significant digits.

• If the two digits are equal, we compare the

next lower significant pair of digits. The

comparison continues until a pair of unequal

digits is reached.

• The sequential comparison can be expressed

by:

DECODERS

• A decoder is a combinational circuit that converts binary information

• from n input lines to an 2nunique output lines.

• Some Applications:

a) Microprocessor memory system: selecting different banks of memory.

b) Microprocessor I/O: Selecting different devices.

c) Memory: Decoding memory addresses (e.g. in ROM).

d) Decoding the binary input to activate the LED segments so that the decimal number can be displayed.

3-to-8-line DECODER[3]

• If the input corresponds to minterm mi then the

decoder ouput i will be the single asserted

output.

3-to-8-line DECODER[3]

2-to-4-line DECODER with

Enable[3]• The decoder is enabled when E = 0. The output whose

value = 0 represents the minterm is selected by inputs A and B.

• The decoder is inactive when E=1 D0………D3 =1

• A Decoder with enable input is called a decoder/demultiplexer. Demultiplexer receives information from a single line and directs it to the output lines.

A 4 x 16 DECODER[3]

• When w = 0, the top decoder is enabled and the bottom is disabled.

• Top decoder generates 8 minterms 0000 to 0111, while the bottom decoder outputs are 0’s.

• When w = 1, the top decoder is disabled and the bottom is enabled.

• Bottom decoder generates 8 minterms 1000 to 1111, while the top decoder outputs are 0’s.

Full-Adder using Decoder[4]

MULTIPLEXERS/DATA

SELECTORS[4]• A multiplexer is a combinational circuit that

selects one of many input lines (2n ) and steers

it to its single output line. There are (2n ) and n

selection lines whose bit combinations

determine which input is selected.

4-to-1LINE MULTIPLEXER

DESIGN[4]

• In general, a 2n –to–1- line multiplexer is

constructed from an n–to 2n decoder by adding

to 2n it lines, one to each AND gate.

References

1. Computer Organization and Architecture, Designing for performance by William Stallings, Prentice Hall of India.

2. Modern Computer Architecture, by Morris Mano, Prentice Hall of India.

3. Computer Architecture and Organization by John P. Hayes, McGraw Hill Publishing Company.

4. Computer Organization by V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky, McGraw Hill Publishing Company.