8086-Special Purpose ProgrammableDevices and their Interfacing

D k J hDeepak JohnSJCET-Palai

Data transfer schemesData transfer schemes To transfer information between CPU and physical I/O devices,

may use the following techniques:may use the following techniques:

Data transfer schemes

Programmed I/ OMemory mapped

I/O mappedpp

Interrupt driven I/ O

Direct memory access

P d I/OProgrammed I/O Data transfer is accomplished through an I/O port controlledata t a s e s acco p s ed t oug a /O po t co t o ed

by software I/O operations are completely controlled by processor, then thep p y y p

system is said to be using “ Programmed I/O” Processor has to check I/O system periodically until the operation

completes “POLLING” Microprocessor has to check if any device need service.

When Programmed I/O techniques is used:I. Processor fetches I/O related instructions from memory and

Issues I/O commands to I/O system to execute the instruction.II. Memory Mapped I/O & I/O mapped I/O technique may apply.III. Processor has 2 separate instructions IN & OUT for data

t ftransfer.IV. When the I/O instruction is encountered by the processor the

I/O port is expected to be ready to responseI/O port is expected to be ready to response.

Memory-mapped I/OReading and writing are similar to memory read/writeReading and writing are similar to memory read/writeUses same memory read and write signalsMost processors use this I/O mapping

Memory Address SpaceMost processors use this I/O mapping

( ) S t I/O d (b) M d I/O ( ) H b idI/O Address Space

(a) Separate I/O and memory space (b) Memory-mapped I/O (c) Hybrid

I/O mappedSeparate I/O address spaceSeparate I/O address spaceSeparate I/O read and write signals are neededUses IN and OUT instructions

Memory AddressSpace I/O address Space

Total Address Space

M M d I/O I/O M d I/OMemory Mapped I/O I/O Mapped I/O

Memory & I/O share the entire Processor provides separateaddress range of processor address range for memory & I/OProcessor provides more addressli f i

Less address lines for accessingI/Olines for accessing memory I/O

More Decoding is required Less decoding is required

Memory control signals used tocontrol Read & Write I/O

I/O control signals are used tocontrol Read & Write I/O

operations operations

I t t I/OInterrupt I/O Overcomes CPU waiting. Overcomes CPU waiting. No repeated CPU checking of device, No need to poll device status. I/O device interrupts the processor and initiate data transfer I/O device interrupts the processor and initiate data transfer I/O module interrupts when ready

A h CPU fi i h h i i i f As soon as the CPU finishes the current instruction, it transfersits execution to an interrupt-service routine which responds to the

t l i t texternal interrupt.

Basic Operation

I. CPU issues read command.II. I/O module gets data from peripheral while CPU does otherg p p

work.III. I/O module interrupts CPU.IV. CPU requests data.V. I/O module transfers data

Direct Memory AccessDirect Memory Access It is a technique of transferring data between memory and I/O devices

i h i iwithout CPU intervention. CPU sets up transfer with DMA controller; then transaction occurs

ith t CPUwithout CPU . DMA channel: system pathway used by a device to transfer

information directly to and from memoryinformation directly to and from memory. DMA controller: dedicated hardware used for controlling the DMA

operationoperation. x86 Interrupt Pins HOLD: DMA request HOLD: DMA request. HLDA: DMA acknowledge signal.

3 techniques:l k f1. Block transfer- whole data block transferred- CPU can do non-related bus activities in the meanwhile

2. Cycle stealing- DMA controller freezes the CPU, and then does a DMA while

CPU frozen- word-by-word transfer

3. Interleaved- DMA controller uses CPU cycles that aren't using the bus,

DMA Controller 8257DMA Controller 8257Features: It is a 4-channel DMA. So 4 I/O devices can be interfaced to DMA. It is designed by Intel. Each channel have 16-bit address and 14 bit counter. It provides chip priority resolver that resolves priority of channels

in fixed or rotating mode.

Functional Block diagramIt containing Five main BlocksIt containing Five main Blocks.1. DMA channels

D t b b ff2. Data bus buffer3. Read/Write logic

C l l i bl k4. Control logic block5. Priority resolver

DMA channels

Each of four channels of 8257 has a pair of two 16-bit registers,named DMA address register (store the address of the startingmemory location, which will be accessed by the DMA Channel) andterminal count register(used for ascertaining that the data transferthrough a DMA channel ceases or stops after the required number ofthrough a DMA channel ceases or stops after the required number ofDMA cycles.).

There are two common registers for all the channels, namely, mode setg , y,register and status register.

Thus there are a total of ten registers. The CPU selects one of theseten registers using address lines Ao-A3.

The count register is used to count the number of byte or wordf d b h f f i itransferred by DMA. The format of count register is,

14-bits B0-B13 is used to count value and a 2-bits is used for indicatethe type of DMA transfer (Read/Write/Veri1 transfer).

Data Bus Buffer: It contain 8 bit bi-directional buffer. Slave mode ,it transfer data between microprocessor and internal

data bus. Master mode ,the outputs A8-A15 bits of memory address on data

li (U idi i l)lines (Unidirectional).Read/Control Logic: It control all internal Read/Write operation. Slave mode ,it accepts address bits and control signal from

imicroprocessor. Master mode ,it generate address bits and control signal.

Control logic block:i It contains ,

1. Control logic2. Mode set register3. Status Register.Control Logic: Master mode ,It control the sequence of DMA operation during all

DMA cycles. It generates address and control signals. It activate a HRQ(Hold ReQuest) signal on DMA channel Request. Slave mode, it is disabled.

Mode Set Registers:It is a write only registersIt is a write only registers.It is used to set the operating modes.This registers is programmed after initialization of DMA channel.

The use of mode set register isThe use of mode set register is,1. Enable/disable a channel.2. Fixed/rotating priorityg p y3. Stop DMA on terminal count.4. Extended/normal write time.5. Auto reloading of channel-2.

Status Registers:Status Registers: It is read only registers, It tell the status of DMA channels. These status bits are cleared after a read operation by microprocessor These status bits are cleared after a read operation by microprocessor. Update flag is not affected during read operation and a one in this bit

position indicates that the channel-2 register has been reloaded fromposition indicates that the channel-2 register has been reloaded fromchannel-3 registers in the auto load mode of operation.

The UP bit is set during update cycle . It is cleared after completion of The UP bit is set during update cycle . It is cleared after completion ofupdate cycle.

Interfacing 8257 with 8086 The DMA controller sends a HOLD request to the CPU and waits fore co t o e se ds a O equest to t e C U a d wa ts o

the CPU to assert the HLDA signal. The CPU relinquishes thecontrol of the bus before asserting the HLDA signal.

Programmable Interval Timer 8253 (PIT)Features

Programmable Interval Timer 8253 (PIT)

1. Three 16-bit independent counters.2. Three counters are identical pre-settable, and can be programmed

f ith bi BCD tfor either binary or BCD count.3. Counter can be programmed in six different modes.4 Compatible with all Intel and most other microprocessors4. Compatible with all Intel and most other microprocessors.5. can operate upto 2.6 MHz.6. Used for controlling real time events RT clock, events counter etc

Block Diagram

Counter

Each counter is assigned an individual port address.

The control register common to all 3 counters. Each counter in the block diagram has 3 lines connected to it. Two of these lines, clock and gate, are inputs. The third, labeled OUT, g , p ,

is an output. The function of these lines changes and depends on how the device is

initialized or programmed.

control word Allows the programmer to select the counter, model of operation,

bi BCD d f ibinary or BCD count and type of operation

Data Bus Buffer bi-directional, 8-bit buffer is used to interface the 8253 to the system

data bus. The Data bus buffer has three basic functions.1. Programming the modes of 8253/54.2. Loading the count registers.3. Reading the count values.

Operation ModesMode 0: Set Output Bit when timer done. The output will start off zero. The count is loaded and the timer

ill t t t t dwill start to count down. When the count has reached zero the output will be set high, and

remain high until the next count has been reloadedremain high until the next count has been reloaded.

Mode 1: Programmable One-Shot. The output will go low following the rising edge of the gate input. Th ill d h ill hi h h The counter will count and the output will go high once the counter

has reached zero..

Mode 2: Rate Generator. The counter will continually count down when the count reaches The counter will continually count down, when the count reaches

zero, the output will pulse low and the counter will be reloaded

Mode 3: Square Wave Generator. This mode is similar to Mode 2 except the t t remains low for This mode is similar to Mode 2 except the output remains low for

half of the timer period and high for the other half of the period.

Mode 4: Software Triggered Pulse. The output will remain high until the timer has counted to zero, atp g ,

which point the output will pulse low and then go high again.

Mode 5: Hardware Triggered Pulse. The counter will start counting once the gate input goes high, wheng g p g g

the counter reaches zero the output will pulse low and then go highagain.

P bl I t t C t ll 8259Programmable Interrupt Controller 8259The Programmable Interrupt Controller (PIC) functions as an overallThe Programmable Interrupt Controller (PIC) functions as an overall

manager in an Interrupt-Driven system environment.Able to handle a number of interrupts at a time. Takes care of a number of simultaneously appearing interrupt requests

along with their types and priorities. Compatible with 8 bit as well as 16 bit processors Compatible with 8-bit as well as 16-bit processors. deal with up to 64 interrupt inputs. interrupts can be masked.te upts ca be as ed. various priority schemes can also programmed.

8259A PIC- BLOCK DIAGRAM

It includes 8 blocks. Control logic Read/Write logic Data bus buffer Three registers (IRR,ISR and IMR) Priority resolver Cascade Buffer

Interrupt Request Register (IRR) and In-Service Register (ISR)h i h i li h dl d b i i The interrupts at the IR input lines are handled by two registers in

cascade, the Interrupt Request Register (lRR) and the In- ServiceRegister (lSR)Register (lSR).

The IRR is used to indicate all the interrupt levels which arerequesting servicerequesting service.

ISR is used to store all the interrupt levels which are currently beingserviced

Priority Resolver This logic block determines the priorities of the bits set in the lRR. This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the corresponding bit

of the lSR during the INTA sequence.g q

Interrupt Mask Register (IMR) The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR.Data Bus Buffer This bidirectional 8-bit buffer is used to interface the 8259A to the

system Data Bus. Control words and status information are transferred through the Data

Bus Buffer

Read-Write Logic accept OUTput commands from the CPU accept OUTput commands from the CPU. contains the Initialization Command Word (ICW) registers and

Operation Command Word (OCW) registers which store the variousOperation Command Word (OCW) registers which store the variouscontrol formats for device operation.

allows the status of the 8259A to be transferred onto the Data BusThe Cascade Buffer/Comparator stores and compares the IDs of all 8259A's used in the system. The

associated three I/O pins (CAS0-2) are outputs when the 8259A isused as a master and are inputs when the 8259A is used as a slave.A h 8259A d h ID f h i i l d i As a master, the 8259A sends the ID of the interrupting slave deviceonto the CAS 0-2 lines. The slave thus selected will send itspreprogrammed subroutine address onto the Data Bus during thepreprogrammed subroutine address onto the Data Bus during thenext one or two consecutive INTA pulses.

Interfacing 8259 with 8086

I t t SInterrupt Sequence1. One or more of the INTERRUPT REQUEST lines are raised high,

setting the corresponding IRR bit(s)setting the corresponding IRR bit(s).2. The 8259A evaluates these requests, and sends an INT to the CPU, if

i tappropriate.3. The CPU acknowledges the INT and responds with an INTA pulse.4 U i i INTA f h CPU h hi h i i ISR bi i4. Upon receiving an INTA from the CPU , the highest priority ISR bit is

set and the corresponding IRR bit is reset.5 The 8086 ill initiate another t o INTA p lses5. The 8086 will initiate another two INTA pulses.6. This completes the interrupt cycle. In the AEOI(Automatic End of

Interrupt) mode the ISR bit is reset at the end of the second INTAInterrupt) mode the ISR bit is reset at the end of the second INTApulse. Otherwise, the ISR bit remains set until an appropriate EOI(Endof Interrupt Mode) command is issued at the end of the interruptp ) psubroutine.

PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the

CPU:1 I iti li ti C d W d (ICW ) B f t t f ti i 82591. Initialization Command Words (ICWs):Before start functioning, 8259

must be initialized by writing two to four command words into theirrespective command word registersrespective command word registers.

2. Operation Command Words (OCWs): These are the command wordswhich command the 8259Ato operate in various interrupt modes.which command the 8259Ato operate in various interrupt modes.

8259A- OPERATING MODES1 FULLY NESTED1. FULLY NESTED2. AUTOMATIC ROTATION3 SPECIFIC ROTATION3. SPECIFIC ROTATION4. END OF INTERRUPT5 AUTOMATIC EOI5. AUTOMATIC EOI1. FULLY NESTED G l d All IR d f hi h t t l t General purpose mode, All IRs are arranged from highest to lowest. IR0 Highest IR7Lowest2 AUTOMATIC ROTATION MODE2. AUTOMATIC ROTATION MODE In this mode, a device after being serviced, receives the lowest

prioritypriority.

3. SPECIFIC ROTATION MODE Similar to automatic rotation mode, except that the user can select

any IR for the lowest priority, thus fixing all other priorities.4. END OF INTERRUPT (EOI) After the completion of an interrupt service, the corresponding ISR

bi d b d h i f i i h ISR Thi ibits needs to be reset to update the information in the ISR. This iscalled EOI command

5 AUTOMATIC EOI5. AUTOMATIC EOI In this mode, no command is necessary. D i th thi d i t t k l d l th ISR bit i t During the third interrupt acknowledge cycle, the ISR bit is reset.

8251A programmable Communication Interface USART (Universal Synchronous Asynchronous Receiver

i )

p g

Transmitter) designed for synchronous /asynchronous serial data

i ti k d i 28 i DIPcommunication, packaged in a 28-pin DIP. Receives parallel data from the CPU & transmits serial data after

conversionconversion. Also receives serial data from the outside & transmits parallel data

to the CPU after conversionto the CPU after conversion.

F ti l Bl k f 8251ABlock diagramFunctional Blocks of 8251A

1. Data Bus buffer2 Read/Write Control Logic2. Read/Write Control Logic3. Modem Control4 Transmitter4. Transmitter5. Receiver

1. Data Bus Buffer

D0-D7 : 8-bit data bus used to read or write status command wordD0 D7 : 8 bit data bus used to read or write status, command wordor data from or to the 8251A

2. Read/Write Control logic I l d t l l i & th b ff i t D t i t Includes a control logic & three buffer registers: Data register,

control register & status register.a Control logic : Interfaces the chip with MPU determines thea. Control logic : Interfaces the chip with MPU, determines the

functions of the chip according to the control word in the controlregister & monitors the data flow.g

b. Control Register:16-bit register for a control word consist of twoindependent bytes namely mode word & command word.

i. Mode word : Specifies the general characteristics of operationsuch as baud, parity, number of bits etc. (fig 2 and 3)

ii. Command word : Enables the data transmission and reception.

c. Status register Checks the ready status of the peripheral Checks the ready status of the peripheral. Status word in the status register provides the information concerning

register status and transmission errorsregister status and transmission errors.d. Data register Used as an input and output port when the C/D is low Used as an input and output port when the C/D is low

CS C/D WR RD Operation

000

001

100

011

MPU reads data from data bufferMPU writes data from data bufferMPU it d t t l i t0

01

11×

01×

1 0 ×

MPU writes a word to control registerMPU reads a word from status registerChip is not selected for any operation1 × × × Chip is not selected for any operation

3. Modem ControlThe modem control unit handles the modem handshake signals toThe modem control unit handles the modem handshake signals to

coordinate the communication between the modem and the USART.4 Transmitter section4. Transmitter section Accepts parallel data from MPU & converts them into serial data. Has two registers:g Buffer register : To hold eight bits Output register : To convert eight bits into a stream of serial bits.p g g

The MPU writes a byte in the buffer register. Whenever the output register is empty; the contents of bufferp g p y;

register are transferred to output register.

5. Receiver SectionAccepts serial data on the RxD pin and converts them to parallel dataAccepts serial data on the RxD pin and converts them to parallel data. Has two registers :

Receiver input registerReceiver input registerBuffer register

Operating Modes of 82511 Asynchronous mode(Txt and Rcv)1. Asynchronous mode(Txt and Rcv)2. Synchronous mode(Txt and Rcv)

Asynchronous Mode (Transmission)Asynchronous Mode (Transmission) When a data character is sent to 8251A by the CPU, it adds start bits

prior to the serial data bits followed by optional parity bit and stop bitsprior to the serial data bits, followed by optional parity bit and stop bitsusing the asynchronous mode instruction control word format. Thissequence is then transmitted using TXD output pin on the falling edgeof TXC.

Asynchronous Mode (Receive) The receiver requires only one stop bit to mark end of the data bit

string. The 8-bit character is then loaded into the into parallel I/Ob ff f 8251 RXRDY i i i d hi h t i di t t th CPU th tbuffer of 8251. RXRDY pin is raised high to indicate to the CPU that acharacter is ready for it.

Synchronous Mode (Transmission) The TXD output is high until the CPU sends a character to

8251 which usually is a SYNC character. If the CPU bufferbecomes empty the SYNC character or characters are insertedbecomes empty, the SYNC character or characters are insertedin the data stream over TXD output.

Synchronous Mode (Receiver) In this mode, the character synchronization can be achieved, y

internally or externally. The content of the receiver buffer iscompared with the first SYNC character at every edge until it

hmatches.

8255-Programmable Peripheral Interface8255-Programmable Peripheral Interface is a popular interfacing component, that can interface any TTL-

compatible I/O de ice to a microprocessorcompatible I/O device to a microprocessor. is used to interface to the keyboard and a parallel printer port in PCs

(usually as part of an integrated chipset).(usually as part of an integrated chipset). PPI has 24 pins for I/O that are programmable in groups of 12 pins

and has three distinct modes of operation. three i/o ports A 8 bits A1 A0 Select

B 8 bits C 4 bits upper and 4 bits lower

0 0 PA

0 1 PB

1 0 PC

1 1 Control reg.

Block Diagram

Data Bus buffer: It is a 8-bit bidirectional Data bus. Used to interface between 8255 data bus with system bus.

Th di ti f d t b ff i d id d b R d/C t l L i The direction of data buffer is decided by Read/Control Logic.Read/Write Control Logic:

Thi i i h i i l f l b d Add b This is getting the input signals from control bus and Address bus Control signal are RD and WR. Address signals are A0,A1,and CS. 8255 operation is enabled or disabled by CS.

Group A and Group B control: Group A and B get the Control Signal from CPU and send the

command to the individual control blocks. Group A send the control signal to port A and Port C (Upper) PC7-

PC4.G B d h l i l B d P C (L ) Group B send the control signal to port B and Port C (Lower)PC3-PC0.

PORT A:hi i bi b ff d / l h This is a 8-bit buffered I/O latch.

It can be programmed by mode 0 , mode 1, mode 2 .PORT B: This is a 8-bit buffer I/O latch. It can be programmed by mode 0 and mode 1.PORT C: This is a 8-bit Unlatched buffer Input and an Output latch. It is splitted into two parts. It can be programmed by bit set/reset operation.

Operation modes:A. BIT SET/RESET MODE: The PORT C can be Set or Reset by sending OUT instruction to the

CONTROL i tCONTROL registers.B. I/O Modes1 O 0(Si i / O )1. MODE 0(Simple input / Output): Ports A, B, and C can be individually programmed as input or

t t toutput ports Port C is divided into two 4-bit ports which are independent from

each othereach other

2. MODE 1(Input/output with Hand shake) Ports A and B are programmed as input or output ports Port C is used for handshaking3. MODE 2 (bi-directional I/O data transfer) Port A is programmed to be bi-directional Port C is for handshaking Port B can be either input or output in mode 0 or mode 1

Functions of Control Word.