Embed Size (px)
DESCRIPTION
https://www.udemy.com/vlsi-academy http://vlsisystemdesign.com/noise_margin.php Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognised as logic '1' and not logic '0'. It is basically the difference between signal value and the nosie value.
Citation preview
Circuit
Circuit
Ideal Scenario
Practical Scenario
In
In
Out
Out
Circuit
Practical Scenario
InOut
Due to the behavioral aspects of the passive components (R,L,C), the ideal characteristicsof the circuits are affected.
To understand this behavior, let’s focus on below mentioned terms
1. Noise Margin2. Switching Activity of CMOS
04/13/2023 3
1. Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit.
2. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognized as logic '1' and not logic '0'.
3. It is basically the difference between signal value and the noise value
Noise Margin
0 1
Let’s Begin with a example, Consider a Inverter
0 1/1 /0
Input and Output of an Inverter
0 1/1 /0
Vin
Vout
0
I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
VddVdd/20
Ideal I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
0
Ideal I/O Characteristic of a Inverter with Infinite Slope
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/20
Actual I/O Characteristic of a Inverter with Finite Slope
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/2
Finite Slope
0
Actual I/O Characteristic of a Inverter with Finite Slope
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VIL is Input Low Voltage => Any input voltage level between 0 and VIL will be treated as logic ‘0’
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOL is Output Low Voltage=> Any output voltage level between 0 and VOL will be treated as logic ‘0’
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VIH is Input High Voltage=>Any input voltage level between VIH and VDD will be treated as logic ‘1’
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2
Infinite Slope
Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VOH is Output High Voltage=>Any output voltage level between VOH and VDD will be treated as logic ‘1’
0 1/1 /0
Vin
Vout
Vdd
VddVdd/2 Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VIL
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VIL VIH
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VIL VIH
VOL
Actual I/O Characteristic of a Inverter
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VIL VIH
VOL
Actual I/O Characteristic of a Inverter
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd Vin
Vout
Vdd
VddVdd/2VIL VIH
Finite Slope
0
VOL
VOH
VIL VIH
VOL
Slope = -1
Slope = -1
Actual I/O Characteristic of a Inverter
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VIL
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
I/O Characteristic plotted on Scale
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
NMH
Noise Margin High
NMH is the Noise Margin High => Any voltage level in “NMH” range will be detected as logic ‘1’
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
NMH
Noise Margin High
NML
Noise Margin Low
VOH
NML is the Noise Margin Low => Any voltage level in “NML” range will be detected as logic ‘0’
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
NMH
Noise Margin High
NML
Noise Margin Low
NMH = VOH - VIH
NML = VIL - VOL
VOH
0 1/1 /0
Vin
Vout
Vdd
Vdd0 VIL VIH
VOL
Slope = -1
Slope = -1
Vdd
0
VOH
VIH
VOL
VIL
NMH
Noise Margin High
NML
Noise Margin Low
Any Signal in ‘Undefined Region’ will be indefinite logic level
VOH
Undefined Region
Noise Margin Summary
04/13/2023 35
For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively
![Noise of Induction Machines - IntechOpen · Noise of Induction Machines 209 Where - p… Static pressure [Pa] - L 4…Minimum value of static pressure, which is able to capture the](https://img.pdfslide.net/doc/110x75/5e7da0bdad6ad6440d193d94/noise-of-induction-machines-intechopen-noise-of-induction-machines-209-where-.jpg)
![BGU6101 Wideband silicon low-noise amplifier MMIC · Wideband silicon low-noise amplifier MMIC 7. Static characteristics Table 7. Static characteristics [1] ICC(tot) = ICC + IRF_OUT](https://img.pdfslide.net/doc/110x75/5f8bbe3820a0400a6155b583/bgu6101-wideband-silicon-low-noise-amplifier-mmic-wideband-silicon-low-noise-amplifier.jpg)
