Optimized Floating- Point Complex Number Multiplier on

FPGA 

Presented ByM. Jaya Lakshmi (10B01D5705)

Under the esteemed guidance of Dr. K. Pushpa

Professor in ECE ,Head of ATL

Shri Vishnu Engineering College for Women, Bhimavaram, AP

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AgendaAimMotivationBackground IntroductionProposed Architecture of Complex Number Multiplier . Floating point Adder/Subtractor . Floating Point Multiplier

Work doneSimulation ResultsStatus of the ProjectReferences

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AimTo design floating point complex number multiplier which

# Occupies less area

# Consumes less power

# High Speed

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MotivationIn general signals are represented as complex numbers.

Operations on complex numbers represent a large part of DSP operations

Every modern DSP includes a Floating-Point (FP) multiplier that complies with the IEEE- 754 Standard.

Large portion of the FP instructions consists of FP multiplications, nearly 37% percent in benchmark applications.

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BackgroundOne Complex Number Multiplier was reported by Akinwande . It is very fast implementation in GaAs hetero structure FET technology. But the level of integration for this multiplier is very low

It is also possible to use CORDIC algorithm for computation of product of two complex numbers, but CORDIC algorithm design was complex and should be designed with rotation algorithms with reference to angles.

Many complex number multipliers are designed previously using four IEEE-754 floating Point Multipliers .

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Introduction Multiplication of two complex numbers is a very frequent operation in many signal processing algorithms

A general complex number multiplication is as follows

(a+jb) (c+jd) = (ac-bd) + j(ad+bc)

-Here 4 multipliers and 3 Adder/Subtractor blocks are used

-floating point multiplier occupies large area on FPGA.

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Contd. . . Representation of IEEE-754 Floating point Number

• 1-bit sign, S: A value of ‘1’ indicates that the number is negative, and a ‘0’ indicates a positive number

• Exponent: e = E + bias: This gives us an exponent range from Emin = -126 to Emax = 127

• Fraction /mantissa: The fractional part of the number

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Proposed Architecture Of Complex Number MultiplierThree intermediate multiplications are defined as follows

Real Part : P+QImaginary part : Q- P

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Contd. . .

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FLOATING -POINT ADDER/SUBTRACTOR

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Floating Point Multiplier

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Work doneSimulated Floating point Adder/Subtractor

Simulated Floating Point Multiplier

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Simulation Results

Fig. Simulation results for Floating Point Multiplier

IEEE-754 FP number

Decimal Equivalent

40133333 2.3

3fa66666 1.3

403f5c28 2.9

3fd851ea 1.69

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Contd . . .IEEE-754 FP number

Decimal Equivalent

40133333 2.3

3fa66666 1.3

40666666 3.6

3f800000 1

Fig. Simulation results for Floating Point Adder/ Subtractor

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Status of the Project I have Presented my project in a National Conference on “ Expanding

Horizon in Computer, Information Technology, Telecommunication & Electronics” organized by IETE at Layola ICAM college, Chennai.

I have designed IEEE-754 single precision Floating-point arithmetic and I have to implement complex number multiplier using this arithmetic block.

I would like to implement this complex number multiplier using inbuilt Wallace tree, Dadda , Modified Booth algorithms and compare the results

In future I would like to use the complex number multiplier to calculate FFT

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References G. Even and P.-M. Seidel. “A comparison of three rounding algorithms for IEEE floating-

point multiplication”. Technical Report EES1998-8, EES Dep., Tel-Aviv Univ., 1998. http://www.eng.tau.ac.il/Utils/reportlist/reports/repfram.html

C. Hinds, E. Fiene, D. Marquette, and E. Quintana. “Parallel method and apparatus for detecting and completing floating point operations involving special operands”. U.S. patent 5339266, 1994.

IEEE standard for binary floating point arithmetic. ANSI/ IEEE754-1985, New York, 1985.

S. Oberman, H. Al-Twaijry, and M. Flynn. The SNAP project:Design of floating point arithmetic units. In Proceedings of the 13th Symposium on Computer Arithmetic, volume 13, pages 156–165. IEEE, 1997.

Akinwande “A 500 MHz 16x16 Complex Multiplier using Self -Aligned gate GaAs Hetero Structure FET technology”, IEEE journal of Solid-State circuits, 2009

http://www.etsimo.uniovi.es/~antonio/uned/ieee754/IEEE-754hex32.html www.xilinx.com

 

Thank You