RF Module Design - [Chapter 8] Phase-Locked Loops

RF Transceiver Module DesignChapter 8

Frequency Synthesis and Phase-Locked Loops

李健榮助理教授

Department of Electronic EngineeringNational Taipei University of Technology

Outline

• Frequency Synthesis Techniques

• Frequency Synthesizers based on the Phase-Locked-Loop

• Loop Analysis and Stability

• Settling Time

• Loop Filters

• Noise Analysis

• PLL Architectures

• Summary

2/55 Department of Electronic Engineering, NTUT

Generic Transceiver Front End

• Local oscillator (LO) provides the carrier signal for both thereceive and transmit paths.

• If the LO output contains phase noise, both downconvertedand upconverted signals are corrupted.

BPFLNA

Duplexer

Antenna

vFrequency Synthesizer LO

PABPF

Department of Electronic Engineering, NTUT3/55

Effect of Phase Noise in Receivers

f0f

Wanted Signal

LO Output

Wanted Signal

DownconvertedSignal

f

DownconvertedSignals

ff0f

Wanted Signal

LO Output Interferer

• Reciprocal mixing


Effect of Phase Noise in Transmitters

f1f

Wanted Signal

Nearby Transmitter

2f

f0f

Multi-carrier signal (or OFDM)

f0f

• Receiver desensitization

• Orthogonality


• Meaning of frequency

• Meaning of frequency synthesisGeneration of a frequency or frequencies that are exact multiples of a referencefrequency. Usually the reference is very precise and the synthesized frequencies areselectable over some range of whole-number multiples of a submultiple of .

Frequency Synthesis

out ref

nf f

M=

wheren andM are integers,n varies fromNmin to Nmax, andM is constant.

( )v t

t

1T

1

1

f

( )V f

f1f

reff


Transformation To and From Voltage or Current

A B1f

Frequency Discriminator

∫

C D

d

dt

Voltage Controlled Oscillator (VCO)

Phase Detector Phase Modulator

1 1v Af=2 1f Bv=

1 1f dtφ = ∫ 2 1v Cφ= 2 2Dvφ =

3 2

df

dtφ=

V/Hz Hz/V

V/rad or V/cycle rad/V or cycle/V


Demonstration of the Transfer Functions

rms rms rms rms rms

1 rad 2 V rad rad 11 V 2 V 2 V V 0.32 V

V cycle cycle 2 radAVπ π

= ⋅ = = = =

RMS voltage at point A:

1 rms

MHz0.32 V 1.5 0.48 MHz

Vf∆ = ⋅ = rms

2

0.32 V MHz1 0.32 MHz

1 k mAf∆ = ⋅ =

Ω( ) rms

5 V0.48 MHz-0.32 MHz 0.8 V

MHzDV = ⋅ =

Phase Modulator1 rad/V

Phase Detector2 V/Cycle

220 MHz VCO1.5 MHz/V

1 kΩ

200 MHz ICO1 MHz/mA

100 MHz signal

Low-pass Filter

50 MHz Cut-off

Frequency Discriminator

5 V/MHz

AB

DModulation voltage(1 Vrms at 10 kHz)

C

and


• Frequency addition and subtraction:

Mathematical Operations on Frequency

( ) ( )cos 2RF RF RFv t A f tπ θ= +

( ) ( ) ( ) ( ) ( )cos 2 cos 2IF RF LO RF RF LO LOv t v t v t A f t B f tπ θ π θ= ⋅ = + × +

For the practical mixer with nonlinear operation:

IF RF LOf mf nf= +

( ) ( )cos 2LO LO LOv t B f tπ θ= +

( ) ( ) ( ) ( ) cos 2 cos 22 RF LO RF LO RF LO RF LO

ABf f t f f tπ θ θ π θ θ= + + + + − + −

( ) ( ) ( )cos 2 cos 2 for 02 RF LO RF LO RF LO

ABf f t f f tπ π θ θ= + + − = =

( ) ( ), cosIF m nv t K m nα β= + 2 1f Bv= 2 LO LOf tβ π θ= +where and

or we can say the intermediate frequency is:

RF

LO

IF

Mixer


Frequency Synthesis Techniques

• Direct Analog Synthesis (DAS)

• Direct Digital Synthesis (DDS)

• Indirect Synthesis : Phase-Locked Loops (PLLs)

• Hybrid DDS/PLL


• Frequency generated by mixed frequencies

Direct Analog Synthesis (DAS) (I)

1f

2f

3f

2Nf −

1Nf −

Nf

outf

filter1

filter2

filter3

filterN-2

filterN-1

filterN

out a bf mf nf= ±


• More stages are required for flexibly frequency planning.

Direct Analog Synthesis (DAS) (II)

1f

2f

3f

2Nf −

1Nf −

Nf

filter1

filter2

filter3

filterN-2

filterN-1

filterN

filter1

filter2

filter3

filterN-2

filterN-1

filterN

outf

1f ′ 2f ′3f ′ 2Nf −′ 1Nf −′ Nf ′

( )out a b cf p mf nf qf= ± ±


Direct Digital Synthesis (DDS) (I)

ref cf f=

• Waveform construction is based on the lookup table (LUT)and a digital to analog converter (DAC).

• Direct synthesis

• Generated frequency is lower than input frequency

Ref. Clk

PhaseAccumulator

Amplitude/SinConv. Algorithm

DACTuning word

N

Digital Analog

2o cN

Mf f= ⋅

M

Jump size

0000…0

1111…1

1111…0


Direct Digital Synthesis (DDS) (II)

• Hardware technique to reduce the spur level of a DDS

• Reduce bandwidth

1000 MHz

100−150 MHz 1100−1150 MHz 110−115 MHz

div-by-10

DDS FilterFrequency

Divider

0f

outf

BW=50 MHz BW=15 MHz

reff


Hybrid DDS/DAS

1f ′ 2f ′ 3f ′2Nf −′ 1Nf −′ Nf ′

outf

filter1

filter2

filter3

filterN-2

filterN-1

filterN

DDS FrequencyDivider

reff

• Scheme to increase a DDS output bandwidth


• The main goal of the PLL is to sync the divided oscillatorfrequency with the reference frequency .

Indirect Frequency Synthesis

( )outf N reff

( )out reff N f= out reff N f= ⋅

PFD: Phase frequency detector LPF: Loop filter VCO: Voltage controlled oscillator /N: Divided-by-N frequency divider

Frequency divider

reffoutf

/N

PFD LPF

VCO


Fractional-N Frequency Synthesis

• Lower division ratioN to reduce inband phase-noise gain

• Effectively produce a fractional division value

• Generally employee a delta-sigma modulator for division ratiodithering

PFD LPF

Dual-modulusFrequency Divider

reff outf

/N, (N+1)

FCW


Phase-Locked Loop Analysis


Feedback System

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )o i o i oV s V s V s H s G s G s V s V s G s H s= − = −

( )( ) ( ) ( )

( ) ( )1o

i

V s G sT s

V s G s H s= =

+

Closed-loop transfer function T(s)

G(s)H(s) is the open-loop transfer function

( )iV s ( )oV s( )G s

( )H s

error

• Feedback loop:


Loop Analysis – Use Frequency as I/O

( ) ( )pv

KG s F s K

s=

( ) 1H s

N=

( )( )

( )( ) ( )

( )

( )111

pv

out

prefv

KF s Kf s G s s

Kf s G s H sF s K

N s

= =+ +

• Relation between input and output frequencies:

Phase differenceFrequency difference

Frequency Divider

( )reff s ( )outf s1

spK

vK

1

N

( )outf s

N

PFDLPF VCO

( )F s


• Relation between input and output phases:

Loop Analysis – Use Phase as I/O

( ) ( ) vp

KG s K F s

s=

( ) 1H s

N=

( )( )

( )( ) ( )

( )

( )11 1

vp

out

vrefp

KK F ss G s s

Ks G s H s K F sN s

φφ

= =+ +

Frequency Divider

( )ref sφ ( )out sφpK ( )F s

vK

s

1

N

Phase difference Frequency to Phase

PFDLPF VCO


Loop Transfer Functions

( ) ( )( )

( )( )

( )( ) ( )

0 0

0 01 1p po

i p p

K F s K s K F s K G sT s

K F s K Ns Ns K F s K G s H s

φφ

= = = =+ + +

T(s) : closed-loop PLL transfer function

G(s) : forward-path transfer function

F(s) : loop filter transfer function

Kp: phase detector gain

K0/s: VCO transfer function

( ) ( )1 0G s H s+ = ( ) ( ) 1 0 dB@ 180G s H s = − = ∠ −

H(s) : feedback-path transfer function

G(s)H(s) : open-loop transfer function

or

• A PLL is unstable when

The condition of unity open loop gain and a phase angle of 180 degrees must be avoided.


PLL Response w/o a Loop Filter (I)

( ) 0 0

0 01

Fp LPFo

Fi p LPF

KK K K s NT s N N

KK K K Ns ss N

φ ωφ ω

= = = =+ ++

( ) LPFF s K=

0ω

logω

dB

0FK

Nω ω= =

20 logN

3 dB

0ω

• Closed-loop transfer function:

Without the loop filter, the feedback loop is equivalent to a DC gain of N plus a low-pass filter (in dB) with cutoff at .

3 dB cutoff frequency is KF/N = KpKLPFK0/N .

With


• The simplest PLL is called a type-I loop because the open-loopgain has one pole at DC (pure integration). It is also a first-order loop because the open-loop gain has one significant pole:

• The open loop gain has a slope of−6 dB/octave or−20dB/decade for all frequencies.

• The phase angle is always−90 degrees at all frequencies.Hence with no low-pass filter, the PLL is always stable. But themain drawback is that designers loose control over the loop.

PLL Response w/o a Loop Filter (II)

( ) ( ) ( )p vK F s KG s H s

Ns=


• The function of the LPF is to filter out any high frequencyharmonics in the loop.

• Adding a LPF also affects the loop response includingparameters such as the loop time response, bandwidth, and thedamping factor.

• If we add a low-pass filter with a pole located at , the loopwill be still type-I, but it will become a second-order loop.

Single Pole Loop Filter

( ) ( )1LPF

p

KF s

s ω=

+( ) ( )

1 1

p LPF v F

p p

K K K KN NG s H s

s ss s

ω ω

= =

+ +

pω


Bode Plot of Open-Loop Transfer Function

( ) ( ) ( )1

G sG s H s

N= = ( )G s N= (forward-loop gain )

log mω

( ) ( )m mG Hω ω

6 dB/oct−1020log FK

N

0 dB

Lωpω1mω =

90−

135−

180−

( )mG ω∠

12 dB/oct−

Phase margin

• Where the curves cross, the open-loop gain equals unity.


• Prototype 2nd-order equation:

• Natural frequency:

• Damping ratio:

Natural Frequency and Damping Ratio

( ) ( )( ) ( )

( )( )

0

0

1

1 1 1 11

F

ppo F

Fi pF

p

p

K

ssK F s K sG s NK

T sKG s H s K F s K Ns sNs KsNs

ωφφ

ωω

+ = = = = =

+ + + + + +

0F p

n p

K

N

ωω ω ω= =

0

1 1 1

2 2 2p p

pn F

N

K

ω ως ω

ω ω= = =

It is geometric mean of the loop bandwidth in the absence of a filter and the filtercorner frequency.

2

2 2 2 22 2 2

p F p F n

p F n n n np

K KN

K s s s ss s

N

ω ω ωω ςω ω ςω ωω

= = =+ + + ++ + Characteristics equation


• The poles of the closed-loop function:

• As long as damping ratio is greater than one, the poles are realand a tangential plot of closed loop gain looks like:

Closed-Loop Gain for Large Damping

20logN

6 dB/oct−

12 dB/oct−

log mω

( )out

ref

fs

f

2 202 1 1 1ω ω ς ς = − −

21 1 1

2pω

ω ς = + −

The characteristics are similar to the case with no loop filter, except for theincreasing rate of attenuation in fout/fref beyond approximately the filter cornerfrequency .

2 1p n ns ςω ω ς= − ± −

0ω

pω

pωDepartment of Electronic Engineering, NTUT28/55

• As decreases toward , the damping ratio decreases andthe phase shift at increases. Correspondingly, the transientresponse of the loop becomes less damped (more ringing) andthe response peaks near .

Close-Loop Responses

0F p

n p

K

N

ωω ω ω= =

0

1 1 1

2 2 2p p

pn F

N

K

ω ως ω

ω ω= = =

pω 0ω0ω

nω

m nω ω0.25 0.5 1 2 4

12 dB

6 dB

0 dB

−6 dB

−12 dB

−18 dB

−24 dB

0.1ς =0.3

0.50.7

1 ( )1 out

ref

f

N fω

0mω ω

0.1ς =12 dB

6 dB

0 dB

−6 dB

−12 dB

−18 dB

−24 dB

−30 dB

0.25 0.5 1 2 4

( )1 out

ref

f

N fω

0.3

2

0.5 0.71

Tangent for no filter


Relative Stability – Phase Margin

• Right figure shows the phase margin(relative stability) as a function of thedamping factor. More highly dampedloops are safer, in that more parametervariation is allowable before instabilityoccurs.

log mω

( ) ( )m mG Hω ω

6 dB/oct−1020log FK

N

0 dB

Lωpω1mω =

90−

135−

180−

( )mG ω∠

12 dB/oct−

Phase margin

• With a single-pole low-pass filter, theloop is inherently stable, sine−180o

phase shift cannot be attained for anyfinite frequency.(not always true practically)

Department of Electronic Engineering, NTUT

ς0.2 0.3 0.5 0.7 1.0 2.00.1

10

20

30

40

50

60

70

80

0

90

14

1 190 tan 1 1

2 4PM

ς−

= − + −

Pha

se M

arg

in (

degr

ee

s)

30/55

Transient Response

0t = t

oldf

newf

Synthesizer output frequency

A

B

CD

Overshot

Ringing• Lower damping ratio brings

a higher percent overshootcan cause the loop to go outof lock. (more unstable)

• Narrower bandwidth withsmaller damping ratio andlonger settling time.


1N

2N

1 refN f

2 refN f

( )2 1N N>

e

1

2

1 ref

Nf

N

−

t

reff outf( )G s

1 N

e

31/55

Settling Time

( )( )0

02.3log

fT

f Tω∆∆

≃

oldf

newf( )0f∆

0t = t T=

( )f T∆

3 -11 MHz/cycle 10 secFK = =10 kHzreff =

11 MHz 10 MHzoutf = →

Find the settling time for the output frequency of 10.1 MHz is attained:6

0

101000

1000FK

Nω = = =

0

2.3 1log 2.3 ms

0.1T

ω=≃


• Settling time:The frequency error changes one decade approximately each 2.3 time constant, i.e.,

• Example (no filter):

32/55

• The addition of a pole in the transfer function causes theslope to drop at a rate of−6 dB/oct whereas the addition of azero has the opposite effect.

• The open loop transfer function is:

• The closed-loop transfer function is:

A Pole-Zero Filter

( ) ( )( )

1

1z

p

sF s

s

ωω

+=

+

( ) ( ) ( ) ( )( )

1

1

p v zp v

p

K K sK F s KG s H s

Ns Ns s

ωω

+ = = +

pω

zω

6 dB/oct−

12 dB/oct−

log mωzωpω

6 dB/oct−

( ) ( )( )

0

01po

i p

K F s K sT s

K F s K Ns

θθ

= =+


Open-Loop Gain with a Pole-Zero LPF (I)

( )( )

2

1

1

p Fz

p F p Fp

z

Ks

NT s NK K

s sN N

ωω

ω ωω

ω

+=

+ + +

0F

n p p

K

Nω ω ω ω= =

1

2p n

n z

ω ωςω ω

= +

6 dB/oct−

12 dB/oct−

log mωzωpω

6 dB/oct−

( )22 2

1

2z

nn n

sN

s s

ωω

ςω ω+

=+ +


• Given the pole frequency location, a zero can be placed afterthe so as to avoid the magnitude fromcrossing the unity gainaxis at a slope of−12 dB/oct, and therefore avoiding instability.To determine the closed loop response, simply plotT(s):

34/55

• Fromthe results:

Selecting the pole frequency sets the natural frequency and subsequently theloop bandwidth.

Selecting the zero (based on the pole location in the open loop gain response)determines the desired percentage overshoot.

• Therefore, a pole-zero filter allows the designer to select theloop bandwidth and the damping factor independently and stillachieve stability.

Open-Loop Gain with a Pole-Zero LPF (II)

0F

n p p

K

Nω ω ω ω= =

1

2p n

n z

ω ωςω ω

= +


• The simplest PLL is the type-I loop because the open-loop gainhas one pole at DC (pure integration). It is also a first-orderloop because the open-loop gain has one significant pole.

Type and Order of the Loop

( ) ( )( ) ( )

( )( )1

G s N sT s

G s H s D s= =

+

( ) 11 0

n nn nN s a s a s a−

−= + + +⋯

( ) 11 0

m mm mD s b s b s b−

−= + + +⋯Order = m (m roots)Type = n (n roots at DC)

( )ref sφ ( )out sφpK ( )F s

vK

s

1

N

PFDLPF VCO


• First order, type I (no loop filter)

First-order Type I

Lωlog mω0 dB

G

6 dB/oct.−

1Riv ov

2R

2

1 2

oLPF

i

v RG

v R R= =

+

A−3R

iv

4R

ov′A → ∞

4

3

oLPF

i

v RG

v R

′′− = = −


• Second order, type I (lag-and-lead filter)

Second-order Type I (I)

1Riv

ov

2R

1C

A−3R

iv5R

ov

2C

4R

Lωlog mω0 dB

G

12 dB/oct.−

6 dB/oct.−zωpω

1

1

zLPF

p

s

Gs

ω

ω

+=

+

2 1

1z R C

ω =( )1 2 1

1p R R C

ω =+

1

1

zLPF

p

s

Gs

ω

ω

+′′− =

+′

4 52

4 5

1z R R

CR R

ω′ =

+5 2

1p R C

ω′ =


• Second order, type I (lag filter)

Second-order Type I (II)

Lωlog mω0 dB

G

6 dB/oct.−

pω

12 dB/oct.−

2

1 2

1

1LPF

p

RG

sR Rω

−=+ +

4

3

1

1LPF

p

RG

sRω

′− = −+

′1 1 2

1 1 1p C R R

ω = +

4 2

1p R C

ω′ =


1Riv

ov

2R 1C

A−3R 4R

ov′

2C

A → ∞iv

39/55

• Second order, type II (integrator and lead filter)

Second-order Type II

Lωlog mω0 dB

G12 dB/oct.−

6 dB/oct.−zω

1 1

11 z

LPF

s

GR C s

ω+

− = −

2

1z R C

ω =


A−1R

iv

2R

ov

C

A → ∞

40/55

• Third order, type II (integrator plus lead-lag filter)

Third-order Type II

Lωlog mω0 dB

G

12 dB/oct.−

pω

12 dB/oct.−6 dB/oct.−

zω

1 1

11

1

zLPF

p

s

GR C s

s

ω

ω

+− = −

+

3 3

11

1

zLPF

p

s

GR C s

s

ω

ω

+′′− = −

+ ′

( )2 1 2

1z R C C

ω =+ 2 2

1p R C

ω =4 3

1z R C

ω′ =5 4

1p R C

ω′ =


A−1R

iv2R

ov

2C

1C

A → ∞

A−3R

iv

4R

ov′

3C

5R

4CA → ∞

41/55

PLL Phase Noise Model


Frequency Divider

Xtal

,ref nφ

outφ

1

N

PFD LPF

,pfd nV ,op nV ,vco nφ

,div nφ

VCO

+ ++ +

+

( ) ( ) ( ) ( ) ( ), , , , , ,out n pfd n op n ref n div n e vco nd

T sV V T s H s

Kφ φ φ φ= + + + +

( ) ( )( ) ( )1

G sT s

G s H s=

+

( ) ( ) ( )1

1eH sG s H s

=+

( ) ( )( ) ( ) ( )

for

for1c

c

NG sT s

G sG s H s

ω ωω ω

<<= ≈ >>+

( ) ( ) ( )( ) for 1

for11

ce

c

N

G sH sG s H s

ω ωω ω

<<= ≈ >>+

where

Very useful results

42/55

Responses of Noise Transfer Functions

cωlog mω

( )( ) ( )1

G s

G s H s+N

( )G s

Transfer function multiplyingall sources except VCO

cωlog mω

( ) ( )1

1 G s H s+1

( ) ( )1

G s H s

Transfer function for VCO

cω log mω

20logN

( )dB

0


Other sources dominateinband noise

VCO dominatesoutband noise

43/55

Typical VCO and PLL Noise Performance


( )L f∆(dBc/Hz)

VCOPLL

( )log f∆1 kHz 10 kHz 100 kHz 1 MHz 10 MHz

−120

−90

−60−30 dB/dec

−20 dB/dec

44/55

Phase-Locked Loop Architectures


• Integer-N PLL• Offset PLL• Fractional-N PLL• DDS offset PLL• Dual loop PLL• Multi-loop PLL

45/55

• Lower division ratio N to reduce inband phase-noise gain• Extend bandwidth with different • Avoid LO pulling

Offset PLL

out ref offsetf N f f= ⋅ +

offsetf


PFD LPF

Frequency Divider

reff outf

/N

offsetf ?

46/55

Offset PLL − Dual-Loop PLL (I)


PFD LPF

Frequency Divider

reff outf

/N

PFD LPF

Frequency Divider

offsetf

/M

47/55

Offset PLL − Dual-Loop PLL (II)

PFD LPF

Frequency Divider

1reff outf

/N

PFD LPF

Frequency Divider

offsetf

/M

2reff


Offset PLL − Hybrid DDS/PLL

PFD LPF

Frequency Divider

reff outf

/N

DDS

offsetf


Multi-Loop PLL


PFD LPF

Frequency Divider

reff outf

/N

1offsetf

PFD LPF

/M

PFD LPF

/P

2offsetf

3offsetf

50/55

• Lower division ratio N to reduce inband phase-noise gain• Effectively produce a fractional division value• Generally employee a delta-sigma modulator for division ratio

dithering

Fractional-N Frequency Synthesis


PFD LPF

Dual-modulusFrequency Divider

reff outf

/N, (N+1)

FCW

51/55

• DDS acts a reference source or phase/frequency modulator• A variable reference frequency source can drive a fractional

frequency output.

DDS-Driven Fractional-N Synthesizer


PFD LPF

Frequency Divider

reff outf

/N

Hybrid DDS/PLL

FCW

DDS

52/55

DDS-feedback Fractional-N Synthesizer

2out ref offsetn

Mf f f= ⋅ +


PFD LPF

DDS as aFrequency Divider

reff outf

DDS

FCW

Hybrid DDS/PLL

• DDS acts a frequency divider

• DDS output frequency:

53/55

Comparison of Frequency Synthesizers

DDSSingle-Loop

PLLMulti-Loop

PLLDDS/DAS

DDS OffsetPLL

DDS DrivenPLL

BW(output)

Narrow

< 100MHz

Broad

> 1GHz

Broad

> 1GHz

Broad

> DDS

Broad

(carefully design)

Broad

ResolutionExtremely

Fine

< 0.02 Hz

Very Course

> 250kHz

(typical)

Medium

> 1kHz

(typical)

Extremely Fine

< 0.01 Hz

Extremely Fine

< 0.01 Hz

Extremely Fine

< 1Hz

SwitchingTime

Very Fast

< 100 ns

Fast

< 100us

(typical)

Very Slow

> 1ms

(typical)

Very Fast

< 1us

(limited by RF switch)

Fast

< 100us

(typical)

Trade-off vsclose-in spurious

tones

SpuriousNoise

< 75dBc

(limited by DAC)

Very GoodGood

(carefully design)

Minimum Close-in Spurious

Minimum Close-in Spurious

Excellent over Broad Bandwidth

PhaseNoise

Better than clock

referenceVery Good Very Good Very Good Very Good Good

Circuitry Simple Simple Very Complex Moderate Moderate Moderate


Summary

• In this chapter, the basic idea of the phase-locked loopsderived fromthe feedback systemwas introduced. One mayput attention on that the PLL is processing the phase (orfrequency) by transforming the phase error into voltage orcurrent signals.

• The PLL transient response and the phase noise were alsopresented in this chapter. We can simply conclude that, as loopbandwidth increases, the locking time is going faster and theVCO inband phase noise can be suppressed with moreattenuation while the other components contribute more noisewithin the loop bandwidth.
