Computer Arithmetic

Prepared by: Buddha Shrestha Devendra Bhandari Diasy Dongol

• Arithmetic means the operation with operand.

– Like

•ADDITION ( + )• SUBTRACTION ( - )•MULTIPLICATION ( * )•DIVIDE ( / )

Eight Conditions for Signed-Magnitude Addition/Subtraction

OperationADD

Magnitudes

SUBTRACT Magnitudes

A > B A < B A = B

(+A) + (+B) + (A + B)

(+A) + (-B) + (A – B ) - (B – A ) + (A – B )

(-A) + (+B) - (A – B ) + (B – A ) + (A – B )

(-A) + (-B) - ( A + B)

(+A) - (+B) + (A – B ) - (B – A ) + (A – B )

(+A) - (-B) + (A + B)

(-A) - (+B) - ( A + B)

(-A) - (-B) - (A – B ) + (B – A ) + (A – B )

12345678

Hardware for signed-magnitude addition and subtraction

A register

AVF

E

Bs

AS

B register

Complementer

Parallel AdderS

Load Sum

MMode Control

Input CarryOutput Carry

Add operation

≠ 0 =0

A>=B

As = BS

=0=1

Augend in A Added in B

END

As BS+

EA A + B

AVF E

EA A + B +1AVF 0

EA

As 0

A A

A A+1As As

As ≠ BS

=0 =1A<B

• For Example of Addition

• (+1) + (+2)

(+A) + (+B)

Add operation

≠ 0 =0

A>=B

As = BS

=0=1

Augend in A Added in B

END

As BS+

EA A + B

AVF E

EA A + B +1AVF 0

EA

As 0

A A

A A+1As As

As ≠ BS

=0 =1A<B

(+1) + (+2)

• (-1) + (+2)

(-A) + (+B)

Add operation

≠ 0 =0

A>=B

As = BS

=0=1

Augend in A Added in B

END

As BS+

EA A + B

AVF E

EA A + B +1AVF 0

EA

As 0

A A

A A+1As As

As ≠ BS

=0 =1A<B

(-1) + (+2)

• For Example of Subtraction

• (+1) - (-2)(+A) - (-B)

As ≠ BS

Subtract operation

≠ 0 =0

A>=B

As = BS

=0 =1

Miuend in A Subtrahend in B

END

As BS+

EA A + B

AVF E

EA A + B +1AVF 0

EA

As 0

A A

A A+1As As

=0 =1A<B

(+1) - (-2)

• (+5) – (+2)

(+A) – (+B)

As ≠ BS

Subtract operation

≠ 0 =0

A>=B

As = BS

=0 =1

Miuend in A Subtrahend in B

END

As BS+

EA A + B

AVF E

EA A + B +1AVF 0

EA

As 0

A A

A A+1As As

=0 =1A<B

(+5) – (+2)

Figure: Hardware for signed-2’s complement addition and subtraction.

BR register

Complementer and parallel adder

AC register

V

Overflow

Subtract

Figure: Algorithm for adding and subtracting numbers in signed-2’s complement representation.

Add

Augend in ACAddend in BR

AC AC + BR V overflow

END

Minuend in ACSubtrahend in BR

AC AC + BR + 1V overflow

END

Figure: Hardware for multiply operation

Bs

B register Sequence counter (SC)

Complementer and parallel adder

A register Q register

As

E

Qs

(rightmost bit)Qn

0

SC

Qn

Multiply operation

Multiplicand in BMultiplier in Q

As Qs Bs

Qs Qs Bs

A 0,E 0SC n-1

EA A + Bshr EAQSC SC-1

END(products is in AQ)

= 0

= 0 = 1

≠ 0

Figure: Flowchart for multiply operation.

BOOTH MULTIPLICATION ALGORITHM

Introduction Hardware for Booth Algorithm Booth Algorithm for multiplication of signed 2’s

complement numbers

INTRODUCTION

multiplication algorithm that multiplies two signed binary numbers in two's complement notation.

 was invented by Andrew Donald Booth in 1950  used desk calculators that were faster at shifting

 than adding and created the algorithm to increase their speed

is of interest in the study of computer architecture.

Hardware for Booth Algorithm

Sign bits are not separated from the rest of the registers

rename registers A,B, and Q as AC,BR and QR respectively

Qn designates the least significant bit of the multiplier in register QR

Flip-flop Qn+1 is appended to QR to facilitate a double bit inspection of the multiplier

BR register Sequence COUNTER (SC)

Complementer and parallel adder

AC register QR register

Qn Qn+1

Booth Algorithm for multiplication of signed 2’s

complement numbers

= 10

=00=11

Multiplicand in BRMultiplier in QR

AC<-0Qn+1<-0

SC<-n

Qn Qn+1

AC<-AC+BR+1 AC<-AC+BR

ASHR(AC & QR)SC<-SC-1

SC END

Multiply

≠ 0 = 0

= 01

Thank You