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About AldecAbout AldecCelebrating 25 Years
Aldec® Corporation
FounderFounder andand PresidentPresidentDrDr.. StanleyStanley HydukeHyduke
Market Position
Aldec UNITE Partners
Aldec RTL Simulation Customers
© Aldec, Inc. 2009 www.aldec.com Page 5
Aldec Hardware Customers
Key Technology Focus
Assertion-Based Verification (ABV)
System Level Verification System-Level Verification
- ESL
- SystemVerilog
S t C- SystemC
OVM and VMM Integration
DSP System Design and Verification – MATLAB and Simulink users
PCB-FPGA/ASIC Design and Verification
Design Rule Checking
Transaction-based Emulation
Hardware In-Loop Acceleration
Prototyping for Actel RTAX-S/SL and RTSX-SU RAD-HARD Devices
End-to-End DO-254 compliant Functional Verification
Enhancing our Core Simulation Kernel & Feature Set
Products
9Active-HDL ™ 8.2RTL Design and Simulation
Common-Kernel Mixed Language SimulatorSimulator
Languages: VHDL, Verilog®, SystemVerilog (Design), SystemC & EDIF
HDL Design Tools: Design entry, Design Creation, Code2Graphics™, Block and State Diagram, Waveform editor, stimulus generation, Language templates & auto-complete, scripting, legacy design support.
Design Flow Manager: use popular third-party tools throughout the design flow within p y g gthe same FPGA environment.
Debugging: Code execution tracing, Waveform/Compare, Memory Viewer, Xtrace, Advanced Dataflow and Profiler.
C C d C T l & Coverage: Code Coverage, Toggle & Functional Coverage.
Additional Interfaces: DSP/HDL algorithm MATLAB® and Simulink® Interfaces & Zuken CADSTAR PCB Design
Assertion and Coverage(OPTION) SystemVerilog PSL & OVA support. Dedicated Assertion viewer, coverage, breakpoint editor.
10Riviera-PRO™ 2009.06Fast RTL Simulation Advanced Verification
Common-Kernel Mixed Language Simulator
Multi-Platform (32/64bit Linux®, Windows®) u t at o (3 /6 b u , do s )
Languages: VHDL, Verilog® , SystemVerilog (Design, Verification & Assertions), Assertions (SVA, OVA, PSL), SystemC & EDIF 200
Debugging: Code execution tracing, Waveform/Compare Memory Viewer XtraceWaveform/Compare, Memory Viewer, Xtrace, Advanced Dataflow and Profiler. Universal HDL/SystemC code level Debugging, Post-Simulation Debugging.
Code Coverage, Functional Coverage, Toggle/Expression/Branch coverage.
Assertion and Coverage based verification. Assertion waveform viewer, functional coverage, breakpoint editor.
Co-Simulation: DSP/HDL algorithm MATLAB® and Simulink® Interfaces
ALINT Design Rule Checking: VHDL, Verilog, Mixed language designs, Violation Viewer, Configuration Manager
Third-Party support: Synopsys SmartModels™ SWIFT SpringSoft® FSDB Denali® MemorySWIFT, SpringSoft® FSDB, Denali® Memory Models, Xilinx Secure IP OVM 2.0 Support –Future.
Simulation Regression Manager (SFM)
ALINT™ 2009.06Design Rule Checking
11
ALINT is a robust environment forD i R l Ch ki iDesign Rule Checking in:
VHDL or Verilog Designs
Mixed-Language Designs
300+ rules from STARC® 2006 Design Guides and Aldec native
Interactive Debugging
Violation Viewer
HDL Editor
Ruleset Editor
Policy Editor
Custom Rules creation
Tracking Results Analysis Reporting Tracking, Results Analysis, Reporting
Design and library management
HES™ 2009.07Hardware Emulation System
ASIC FPGA SOC ASIC, FPGA, SOC
Emulation 1-100MHz
Acceleration 10X or more
Prototyping 1-100MHz
Simulator Independent
L VHDL V il ®Languages: VHDL, Verilog® , SystemC/C/C++, Assertions, EDIF
Transaction Level Interface(SCE MI 2 0 S t C C/C )(SCE-MI 2.0, SystemC C/C++)
Ultra-Fast DebuggerTM
off-the-shelf DINI and HAPS hardware support
DO-254/CTS™End-to-End Verification of AvionicDesigns for DO-254/ED80 Compliance
Advantages• At-Speed Design Verification in Target Devices• Supports Actel™ Altera® Lattice® QuickLogic® and• Supports Actel , Altera®, Lattice®, QuickLogic® and Xilinx®• Automatic Test Vectors Generation for Target Devices• Auto-Capture and Analysis of results at all Design Stages• Easy Design Requirements Traceability• Independent EDA Tool Assessmentp• Significantly shortens Device Verification Time
Included Software• Aldec HDL Simulator (optional)• Aldec Waveform Viewer
C d C• Code Coverage• Design Rule CheckingIncluded Hardware• PCI/PCIe Motherboard• Custom Daughterboard with target device• CVT Application (TVD VT drivers API diagnostic CVT Application (TVD, VT, drivers, API, diagnostic designs and
documentation)AnalysisResults Compare EDA Tool Qualification
ComplianceDO-254/CTS supports the “Design Assurance Guidance for Airborne Electronic Hardware” ( DO-254/ED80) chapter 6.2 “Verification Process” and chapter 11.4 “Tool Assessment and pQualification Process”. Levels A-D.
ALDEC INDIA OPERATIONS
Aldec India office is based in Bangalore.
P-186, Sector 10Jiwan Bima NagarBangalore 560075
Focusing mainly on marketing and customer support.
India
Visit us at: www.aldec.com
CHANNEL PARTNERS IN INDIA
www.amdlcorp.comHeadquartered in Bangalore
Offices in Delhi, Mumbai, Hyderabad and other major cities
a d co p co
Its customer base includes major Corporate and Defenseestablishments, Software Technology parks, MNC's and Super-Specialty Hospitals.p y p
The company's commitment to technology and support hasbeen its areas of strength and the reason for its customers tochoose AMDL as a vendor of choice.
CHANNEL PARTNERS IN INDIA
www.arts.net.in
Incorporated in 1995 Arts Agencies a vibrant and dynamic marketing company strives to provide a complete suite of solutions to its customers in the areas of Analog Digital RF & Embedded Designcustomers in the areas of Analog, Digital, RF & Embedded Design.
Take care of Aldec product distribution in Defense organizations like DRDO Labsorganizations like DRDO Labs.
Thank You!