PLL in LPC2148 By- Aarav Soni

Pll in lpc2148

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Page 1: Pll in lpc2148

PLL in LPC2148

By-Aarav Soni

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What is PLL ?

• PLL is used to generate system clock from between 10 MHz to 25 Mhz. PLL may multiply frequency to range from 10 MHz to 60 MHz (LPC21xx Series) and 48 MHz for USB if used.

• PLL uses frequency multiplier which can be in a range from 1 to 32, in real world situation this value should not be higher than 6 due to upper frequency limit.

• In LPC2148 microcontrollers there are two PLLs which provide programmable frequencies to the CPU and USB System. [PLL0: For System Clock, PLL1: For USB Clock.

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• System clock can be generated from 10MHz to 25 MHz.• PLL (Phase Locked Loop) can be used to multiply frequency to

range from 10MHz to 60MHz.• PLL generator allows running ARM at high speed even low

speed oscillator connected.• The most important is you can change the frequency

dynamically• As minimum divider is 2 so output of PLL will be always 50%

duty cycle

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• ARM7 LPC2148 Microcontroller needs two clocks; one is for its peripherals and other for its CPU.

• CPU works faster with higher frequencies whereas peripheral needs lower frequency to work with.

• The Peripheral Clock (PCLK) and CPU Clock (CCLK) gets clock input from a PLL or from external source.

• After RESET, configuration of PLL (Phase Lock Loop) and VPB (VLSI Peripheral Bus) Divider would be first thing to do.

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• PLL unit itself uses CCO (Current Controlled Oscillator) which operates in the range between 156 MHz to 320 MHz, so there is additional divider which keeps CCO within its range, while PLL provides desired frequency.

• Output clock is generated by dividing CCO frequency by 2, 4, 8, 16. Minimum divider is ‘2’ so output of PLL will always have duty cycle 50% for sure.

• VPBDIV=0x00APB bus clock (PCLK) is one fourth of the CCLK.• VPBDIV=0x01APB bus clock (PCLK) is the same as the CCLK.• VPBDIV=0x02APB bus clock (PCLK) is one half of the CCLK.• VPBDIV=0x03Reserved. If this value is written to the APBDIV

register, it has no effect (the previous setting is retained).

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Now , PLL output clock is given by the formula:

CCLK = M x FOSC=or=CCLK = FCCO / (2 x P)CCO output clock is given by:FCCO = CCLK x 2 x P=or=FCCO = FOSC x M x 2 x P

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PLL Registers in LPC2148

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1. Select the desired operating frequency for your system (CPU Operating Frequency) CCLK.

2. Check the oscillator connected to the controller on board FOSC.3. Calculate the value of PLL Multiplier ‘M’ CCLK=M x FOSC.4. Find the value of PLL Divider ‘P’ in such a way that is in the

range of 156 MHz to 320 MHz, 156<FCCO<320 = CCLK x 2 x P.5. Write the value PLLCON and PLLCFG.6. Write the PLLFEED values 0xAA and 0x55.7. Wait for PLL to lock.8. Connect the PLL.9. Write the PLLFEED values 0xAA and 0x55 once again.

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Setting-up and using PLL

• To access PLL we need to have a key to open the safe in order to use or configure it. The key here is the ‘Feed Sequence’.

• Feed Sequence is nothing but assignment of 2 particular ‘fixed’ values to a register related to the PLL block. This register is called ‘PLL0FEED’. And those fixed values are 0xAA and 0x55 are ‘in order’!. Hence the code for feed sequence must be :

PLL0FEED = 0xAA; PLL0FEED = 0x55;

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PLL Control Register (PLLCON)

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PLLE:• PLLE means PLL Enable Bit.• It is set to active the PLL and allows it to lock

to the requested frequency. PLLC:• PLLC means PLL connect• Is set to connect the PLL as clock source. A

successful connect requires the PLLE bit set.

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PLL Configuration Register (PLLCFG

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• Calculate the value of M to configure the MSEL bits. M = CCLK / FOSC. M must be in the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1.

• Find a value for P to configure the PSEL bits, such that FCCO is within its defined frequency limits. FCCO is calculated using the equation given above. P must have one of the values 1, 2, 4, or 8.

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• We have 12 MHz crystal connected to LPC2148 on our microcontroller development board. We can say FOSC=12 MHz. And we want core to be run at 60 MHz. In this case, we have to multiply crystal frequency i.e.12 MHz by ‘5’.

• CCLK = M x FOSC = 5 x 12 = 60 MHz. Also we have to keep FCCO (Frequency of the PLL Current Controlled Oscillator) within its range i.e. [156 MHz – 320 MHz], so we have to control another constant ‘P’:

• FCCO = CCLK x 2 x PFCCO = 60 MHz x 2 x 2 = 240 MHz. • So we found P = 2 meets FCCO requirements (156 MHz

Programming PLL has to be done in some sequence to make new PLL setting effective. First of all we have to write multiplier M and divider P values to PLLCFG Register. Since M & P values can be very specific.

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PLL Status Register (PLLSTAT)

Used for monitoring and check status of opearation.

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Example:Here I am generating 60Mhz through PLL.

void PLL_Init(void){PLL0CON = 0x01; //Enable PLLPLL0CFG = 0x24; //Multiplier and divider setupPLL0FEED = 0xAA; //Feed sequencePLL0FEED = 0x55;while(!(PLL0STAT & 0x00000400)); //is locked?PLL0CON = 0x03; //Connect PLL after PLL is lockedPLL0FEED = 0xAA; //Feed sequencePLL0FEED = 0x55;VPBDIV = 0x01; // PCLK is same as CCLK i.e.60 MHz}

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For any suggestion,Please contact me on-Mail id- [email protected] https:www.facebook.com/arav.soni.98Twitter- https://twitter.com/AaravSoni1