Architecture and instruction set

Architecture and instruction setArchitecture and instruction set

Microcontroller Core Features: Operating speed: DC - 20 MHz clock input DC - 200 ns instruction

cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory

Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for

reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options

Peripheral Features Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler, can be incremented

during SLEEP via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and

postscaler Two Capture, Compare, PWM modules

Capture is 16-bit, max. resolution is 12.5 ns Compare is 16-bit, max. resolution is 200 ns PWM max. resolution is 10-bit

10-bit multi-channel Analog-to-Digital converter Synchronous Serial Port (SSP) with SPI (Master mode) and I2C

(Master/Slave) Universal Synchronous Asynchronous Receiver Transmitter

(USART/SCI) with 9-bit address detection Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS

controls (40/44-pin only) Brown-out detection circuitry for Brown-out Reset (BOR)

Program Memory Program Memory OrganizationOrganization

The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space.

The PIC16F877/876 devices have 8K x 14 words of FLASH program memory.

Accessing a location above the physically implemented address will cause a wraparound.

The RESET vector is at 0000h and the interrupt vector is at 0004h.

Data Memory OrganizationData Memory Organization The data memory is partitioned into multiple banks which contain the The data memory is partitioned into multiple banks which contain the

General Purpose Registers and the Special Function Registers. Bits General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function The lower locations of each bank are reserved for the Special Function

Registers. Registers. Above the Special Function Registers are General Purpose Registers, Above the Special Function Registers are General Purpose Registers,

implemented as static RAM. implemented as static RAM. All implemented banks contain Special Function Registers. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may Some frequently used Special Function Registers from one bank may

be mirrored in another bank for code reduction and quicker access.be mirrored in another bank for code reduction and quicker access.

What are the two/four banksfor?

Memory space is organized in 128Byte banks. PIC 16F684 has two banks - Bank 0 and Bank 1. Bank 1 is used to control the actual operation of

the PIC for example to tell the PIC which bits of Port A are input and which are output.

Bank 0 is used to manipulate the data. An example is as follows:

Let us say we want to make one bit on Port A high. First we need to go to Bank 1 to set the particular bit,

or pin, on Port A as an output. We then come back to Bank 0 and send a logic 1 (bit

1) to that pin.

Special Function Registers W, the working register. To move values from

one register to another register, the value must pass through the W register.

FSR (04h,84h,104h,184h), File Select Register Indirect data memory addressing pointer

INDF (00h,80h,100h,180h) accessing INDF accesses the location pointed by IRP+FSR

PC, the Program Counter, PCL (02h, 82h, 102h, 182h) and PCLATH (0Ah, 8Ah, 10Ah, 18Ah)

Direct/Indirect Addressing

Direct Addressing Use only 7 bits of instruction to identify a register file

address. The other two bits of register address come from RP0 and

RP1 bits in the STATUS register Example: Bank switching (Note: case of 4 banks)

CLRF STATUS ; Clear STATUS register (Bank0) : ; BSF STATUS, RP0 ; Bank1 : ; BCF STATUS, RP0 ; Bank0 : ; MOVLW 0x60 ; Set RP0 and RP1 in STATUS register, other XORWF STATUS, F ; bits unchanged (Bank3) : ; BCF STATUS, RP0 ; Bank2 : ; BCF STATUS, RP1 ; Bank0

Indirect Addressing The INDF register is not a physical register. Addressing the

INDF register will cause indirect addressing. Any instruction using the INDF register actually access the

register pointed to by the File Select Register (FSR). The effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit in STATUS register. Example

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT: CLRF INDF ;clear INDF register INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? (to 0x2F) GOTO NEXT ;no clear next CONTINUE:

;yes continue

I/O Ports General I/O pins are the simplest of peripherals

used to monitor and control other devices. For most ports, the I/O pin’s direction (input or

output) is controlled by the data direction register TRISx (x=A,B,C,D,E).

A ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output

The PORTx register is the latch for the data to be output. Reading PORTx register read the status of the pins, whereas writing to it will write to the port latch.

Example: Initializing PORTD bcf STATUS, RP0 ; bank0 bcf STATUS, RP1 clrf PORTD ; initializing PORTD by clearing output

data latches bsf STATUS, RP0 ; select bank1 movlw 0xCF ; value used to initialize data direction

(1100 1111) movwf TRISD ;

PORTD<7:6>=inputs, ;PORTD<5:4>=outputs, PORTD<3:0>=inputs

Instruction FormatsInstruction Formats

INSTRUCTION 1INSTRUCTION 1

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INSTRUCTION 3INSTRUCTION 3

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INSTRUCTION 30INSTRUCTION 30

INSTRUCTION 31INSTRUCTION 31

INSTRUCTION 32INSTRUCTION 32

INSTRUCTIONS 33-35INSTRUCTIONS 33-35

SLEEPSLEEP CLRWDTCLRWDT NOPNOP